JP3780143B2 - DLL system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a DLL (delay locked loop) capable of inputting a clock signal whose phase is discontinuously changed by a trigger signal and outputting a multi-phase clock signal in which each clock phase is controlled. It relates to the circuit.
[0002]
[Prior art]
Description of PLL circuit
There is a PLL (Phase Locked Loop) circuit as a circuit similar to the DLL circuit. Before describing the DLL circuit, the PLL circuit will be described. FIG. 12 shows a configuration example of the PLL circuit. The X′tal oscillation circuit 8 outputs a reference clock signal of 30 MHz or less that can be easily generated only by a crystal resonator, and is input to the reference signal input R 2 of the phase comparison circuit 9. The variable frequency oscillation circuit 13 controlled by the control voltage VD2 outputs a reference clock K used for the system. The reference clock K is input to the frequency dividing circuit 12, outputs an N frequency divided clock signal, and is input to the comparison input V2 of the phase comparison circuit 9. The phase comparison circuit 9 outputs an up pulse U2 (down pulse D2) when the phase of the comparison signal V2 is delayed (the phase is advanced) with respect to the reference signal R2. If the phase of the comparison signal V2 and the reference signal R2 match, neither the up pulse U2 nor the down pulse D2 is output. These up pulse U2 and down pulse D2 are input to the charge pump circuit 10 to generate an error voltage VC2.
[0003]
The error voltage VC2 is input to the control signal generation circuit 11. The control signal generation circuit 11 creates a control voltage VD2 for generating a control current that determines the output frequency of the variable frequency oscillation circuit 13. The control voltage VD2 is input to the variable frequency oscillation path 13. A resistor Rd and a capacitor Co are connected to the output of the charge pump circuit 10, and the loop stability that is hindered by setting the AC conversion gain to a predetermined finite value and integrating the control phase error by the variable frequency oscillation circuit 13 is achieved. Secured.
[0004]
As the phase comparison circuit 9, a digital phase comparison circuit is generally employed at present. Since the digital phase comparison circuit 9 has a frequency detection capability in addition to the phase difference detection capability, the PLL circuit can realize a stable configuration free from malfunction conditions. As the output reference clock K, it is possible to generate a stable clock signal having a frequency N times that of the clock signal generated by the X′taI oscillation circuit 8, which is impossible with the X′taI oscillation circuit. The PLL circuit is generally used in a digital circuit (LSI) whose accuracy is increasing.
[0005]
Description of conventional DLL circuit
In a digital system, there is a case where signal processing with higher accuracy is performed using a clock signal whose phase changes discontinuously by a trigger signal. When the clock signal whose phase changes discontinuously is used as the reference signal R2, in the PLL circuit, the equilibrium state is lost every time the phase change occurs, and the pull-in operation must be performed again. In this case, a DLL circuit is used.
[0006]
FIG. 10 shows a configuration example of a conventional DLL circuit. The clock signal SCK whose phase changes discontinuously is input to the delay chain circuit 7 in which a plurality of delay circuits whose delay times can be controlled are connected in cascade, and the N multiphase clock signal groups P0 whose phases are sequentially delayed. Output ~ PN. The clocks P0 and PN are input to the phase comparison circuit 4 as the reference signal R1 and the comparison signal V1. The output up pulse U1 and down pulse Dl are input to the charge pump circuit 5 and output an error voltage VCl. The error voltage VC1 is generated by the control signal generation circuit 6 to generate the control voltage VD1, and is input to the delay chain circuit 7 to control the delay time in the internal delay circuit. In the DLL circuit, the control phase error is not integrated by the delay chain circuit 7 and the loop stability is not hindered. Therefore, unlike the PLL circuit, a filter that suppresses the AC gain to a finite value at the output of the charge pump circuit 5. No circuit is needed.
[0007]
Therefore, as shown in FIG. 11a, the clock signal PN is controlled so as to be balanced in a state where the clock signal is delayed in phase by a clock signal period with respect to P0. The clock signals P0 to P (N-1) are controlled timing signals within the clock cycle, and high-precision digital signal processing can be performed using these clock signals.
[0008]
As described above, the digital signal processing includes a PLL circuit that can improve the accuracy of a continuous clock (absolute time axis) and a DLL circuit that can improve the accuracy of a clock whose phase changes discontinuously (asynchronous time axis). To achieve high-precision signal processing.
[0009]
[Problems to be solved by the invention]
However, the conventional DLL circuit has the following malfunction problems.
[0010]
(Problem 1) When the comparison signal V1 (PN) is delayed by two cycles with respect to the reference signal Rl (P0) as shown in FIG. 11b, the up pulse U1 and the down pulse D1 are delayed by one cycle as can be seen from the figure. Just as in the case, both do not occur and the situation is balanced. In this state, this phenomenon occurs with an integer multiple cycle delay of 2 times or more. In order to avoid this malfunction, the control voltage generation range in the control signal generation circuit 6 may be limited. However, particularly in the case of a CMOS circuit (general), it is impossible to cope with a large element characteristic variation. is there.
[0011]
(Problem 2) When the comparison signal V1 (PN) advances from a desired desired cycle delay with respect to the reference signal R1 (P0) as shown in FIG. 11c, the up pulse U1 is not output and the down pulse D1 is output. Thus, the comparison signal V1 (PN) is delayed and balanced to a desired one-cycle delay. However, this operation is not guaranteed in the phase comparison circuit.
[0012]
On the contrary, as shown in FIG. 11d, the up pulse U1 is generated without generating the down pulse D1, and the phase of the comparison signal V1 (PN) is further advanced to the control capability limit of the control signal generating circuit 6 from this state. I can't escape.
[0013]
The frequency detection function of the digital phase comparison circuit that is effective in the PLL circuit has no effect on the malfunction of the DLL circuit described above. Although the DLL circuit is a very effective circuit, it cannot be used widely in a digital signal processing system unless this malfunction problem is fundamentally solved.
[0014]
The present invention has been made under such circumstances, and an object of the present invention is to provide a DLL system that does not have a balance (convergence) of malfunctions.
[0015]
[Means for Solving the Problems]
In the present invention, in order to achieve the above object, the DLL system is configured as follows (1) and (2).
[0016]
(1) Output signal of variable frequency oscillator In a DLL system having a delay chain circuit in which first control delay circuits are connected in cascade, to which a first clock signal is input, and controlling the signal delay time of the delay chain circuit,
Includes a plurality of second control delay circuits Said A PLL circuit that controls the output signal of the variable frequency oscillation circuit to a factor multiple of the input second clock signal frequency, and a first control signal that controls the first control delay circuit. And A second control signal for controlling the second control delay circuit; Issue Based on the comparison result of the comparison circuit and the comparison circuit, the operation of the phase comparison circuit included in the DLL circuit is stopped, and the output voltage of the charge pump circuit included in the DLL circuit is also compared with the comparison result. And a control circuit for making a transition in a desired voltage direction.
[0017]
(2) In the DLL system according to (1), each of the comparison circuits includes Setting value Each other Different first and second comparison circuits The And a control circuit that stops the operation of the phase comparison circuit based on the comparison result of the first or second comparison circuit and makes transitions to different desired voltage directions based on the comparison result of the first and second comparison circuits. Provided DLL system.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to examples of DLL systems.
[0019]
【Example】
FIG. 1 is a diagram illustrating a configuration of a DLL system according to an embodiment. This embodiment is roughly composed of a DLL circuit 2, a DLL malfunction prevention circuit 1, a PLL circuit 3, and a synchronous clock signal generation circuit 14.
[0020]
Description of PLL circuit 3 for generating a multiphase clock group
Since the PLL circuit 3 is basically the same as the configuration of FIG. 12, only the differences will be described. The variable frequency oscillation circuit 13 can generate multiphase clock groups K0 to Km (m is an integer). An example of the configuration of the variable frequency oscillation circuit 13 when m = 7 is shown in FIG. The positive output Po and the negative output No of the delay circuit 15a that delays the differential signal are input to the positive input Pi and the negative input Ni of the delay circuit 15b having the same configuration. Similarly, the positive output Po and the negative output No of the delay circuit 15b are input to the delay circuit 15c having the same configuration. The delay circuit 15d is also input in the same manner, but the positive output Po and the negative output No are input to the negative input Ni and the positive input Pi of the delay circuit 15a to constitute an oscillation circuit. The differential outputs Po and No of the delay circuits 15a to 15d output the multiphase clock groups K0 to K7 via the differential buffers 16a to 16d. The control voltage VD2 is input to the control terminals Vd of the delay circuits 15a to 15d, and the oscillation frequency is controlled by controlling the delay time of each delay circuit.
[0021]
Description of delay circuits 15a-15d for delaying differential signals
FIG. 3 shows a configuration example of the delay circuits 15a to 15d using a CMOS circuit. The drive voltage Vd is input to MN1 / G and MN3 / G. The drain current I1 of MN3 is connected to the sources of the source couples MN2 and MN4. A positive signal Pi and a negative signal Ni are input to MN2 / G and MN4 / G. MN1 / D is input to the gate-drain short circuit MPl / D, MP2 / G and MP3 / G. MP2 / D and MP3 / D that both output current I2 are connected to MN2 / D and MN4 / D, respectively, and gate-drain short circuit MN5 / S and MN6 / S are connected, and positive signal Po and negative signal No are output. Output. When I2 = I1 / 2, charging and discharging are performed by the current I2 during each transition period of Po and No. Since the current I2 is determined by the drive voltage VD, the input / output delay time can be controlled.
[0022]
Description of the synchronous clock signal generation circuit 14
The multiphase clock groups K0 to Km are output to a digital signal processing unit (not shown) that requires a high-precision absolute time axis and also input to the synchronous clock signal generation circuit 14. FIG. 9 is a time chart for explaining the operation of the synchronous clock signal generation circuit 14. FIG. 4A shows the synchronization trigger signal SYNC, and FIG. 2B shows the synchronization clock signal SCK. When an effective timing of the synchronization trigger signal SYNC occurs at time ts, a clock signal having the same cycle as that of the clock groups K0 to Km is immediately generated with a delay of T1 for a certain period (in synchronization). Since the clock groups K0 to Km and the synchronous trigger signal SYNC are completely asynchronous, the phase of the output clock signal jumps (becomes discontinuous) at the time ts when the effective timing of the synchronous trigger signal SYNC occurs. That is, the synchronous clock signal SCK controls an asynchronous time axis. Further, the synchronization accuracy Js of the synchronization clock signal SCK with respect to the synchronization trigger signal SYNC is determined by each phase difference of the multiphase clock groups K0 to Km.
[0023]
Description of DLL circuit for generating multi-phase clock
The synchronous clock signal SCK is input to the delay chain circuit 7 in the DLL circuit 2. Differences between the DLL circuit 2 and the conventional example of FIG. 10 will be described. A configuration example of the delay chain circuit 7 is shown in FIG. Here, the case where N = 8 will be described. The synchronous clock signal SCK is input to the differential buffer 17 and converted into a differential signal. This differential signal is input to nine delay circuit groups 15e to 15n having the same configuration and connected in cascade. The control voltage VD1 for controlling each delay time is input to the control terminal Vd, and the differential outputs Po and No of the delay circuits respectively output the multiphase clock groups P0 to P8 via the single-phase buffers 18a to 18h. To do. The delay circuit 15n in which the output differential signal is not used is for obtaining the same operation as in the other delay circuits 15e to 15m. Since the delay times of the delay circuits 15e to 15n in the delay chain circuit 7 and the delay circuits 15a to 15d in the variable frequency oscillation circuit 13 in the PLL circuit 3 can be made equal, the control current controlled by the control voltages VDl and VD2 is relative to the elements used. Only the difference due to variation. However, it cannot be driven by the control voltage VD2 of the PLL circuit 3 also using the delay chain circuit 7. This relative variation can be sufficiently suppressed to 10% or less even in a CMOS process with a large absolute variation of elements.
[0024]
Description of charge pump circuit
A general configuration of a charge pump circuit used in the PLL circuit 3 and the DLL circuit 2 is shown in FIG. The negative up pulse NU and the positive down pulse PD are input to MP1 / G and MN1 / G, respectively, and MP1 / D, MN1 / D and capacitor Cl are connected to output an error voltage VC. In MN1 / S, a down current I1 is generated by MN2, and in MP1 / S, an up current I2 is generated by MP2, MP3, and MN3.
[0025]
The same bias VB1 is input to MN2 / G and MN3 / G to ensure the correlation between the currents I1 and I2. Usually, the (W / L) ratio of the related transistors is set so that the down current I1 and the up current I2 are equal. However, this charge pump circuit has two problems. It is impossible to design the drain-source voltages of MN2 and MN3 and MP2 and MP3 to be approximately equal, and they vary with respect to device absolute variation (especially current drive capability) and environment (operating temperature, power supply voltage). Therefore, the down current I1 and the up current I2 cannot be balanced due to the Early effect. This means that, when considered on a regular basis, the input up-pulse width and the down-pulse width are in a balanced state, and the comparison signal V is out of phase with the reference signal R. It will converge. Further, when MP1 and MN1 are turned off by the up pulse and the down pulse, MP1 / S and MN1 / S move toward the power source and GND, respectively, and the current driving capability of MP2 and MN2 is lost. When MPl and MN1 are turned ON from this state, MPl / S (MN1 / S) is first lowered (increased), and then the current driving capability of MP2 (MN2) is restored to increase the up current I2 (down current I1). As a result, current is supplied to the charge pump terminal to change the error voltage VC.
[0026]
As described above, in the charge pump circuit of FIG. 2, transient characteristics are not ideally performed and not only high-speed operation but also a factor that the comparison signal V in the balanced state converges in a state where the phase is shifted from the reference signal R. have. The above operation is fatal in the DLL circuit 2.
[0027]
Therefore, the present inventor has proposed a charge pump circuit having the configuration example of FIG.
[0028]
Differential up-pulses (NU, PU) converted into differential signals are input to MP1 / G and MP4 / G, respectively, and differential down-pulses (PD, ND) converted into differential signals are respectively input to MN1 / G. G and MN4 / G are input. MP1 / S and MP4S are connected and connected to MP2 / D that supplies up current I2, while MN1 / S and MN4 / S are connected and connected to MN2 / D that supplies down current. MP1 / D and MlN1 / D and MP4 / D and MN4 / D are connected to each other, and the connection points of MP1 / D and MN1 / D are connected to the capacitors CI and C2 connected to the power supply and GND, and the error voltage VC. Is output as The error voltage VC is input to the voltage buffer 21, and its output is connected to the connection point of MP4 / D and MN4 / D. MN3 driven by the same bias VB1 as MN2 generates a coefficient current of down current I1 and is connected to MP3 / D. Since MP3 / G and MP2 / G are connected, a coefficient current of an up current is generated in MP3 / D. The current balance between the up current I2 and the down current Il is controlled by a control circuit including MN5, MN6, MN7, MP5, MP6 and resistors R1 and R2 so that the current value of MP3 / D becomes equal to the current value of MN3 / D. To do. The voltage in the current balance is determined by the resistors R1 and R2, and is normally set to half of the power supply voltage in which the usable voltage range of the error voltage VC is most widely obtained (that is, Rl = R2).
[0029]
The charge pump circuit of FIG. 6 not only dramatically improves the balance between the up current and the down current, but also when MP1 or MN1 related to the charge pump operation is OFF, MP4 or MN4 is ON and MP1 / S and By holding the MNl / S voltage, the up current source MP2 and the down current source MN2 can always be operated. In addition, since the error voltage VC is input to the connection point between MP4 / D and MN4 / D via the voltage buffer 21, the drain-source voltage when the transistors of MP1 and MP4 and MN1 and MN4 are turned on and off. Therefore, the charge pump operation with respect to the change of the up pulse and the down pulse becomes remarkably quick.
[0030]
With respect to the element values of the capacitors C1 and C2 connected to the error voltage VC terminal, the resistance value (R1 / R2) and the capacitance ratio (C2 / Cl) are set so as to be strong against power supply noise. The charge pump circuit configured as shown in FIG. 6 can also be used in the PLL circuit 2.
[0031]
Description of DLL malfunction prevention circuit
The DLL malfunction prevention circuit 1 included in the DLL circuit 2 will be described. The control voltage VD1 is input to MN1 / G and MN2 / G, and generates a coefficient current of a control current that determines the delay time of each of the delay circuits 15e to 15n in the delay chain circuit 7 at each drain terminal. On the other hand, the control voltage VD2 generated in the PLL circuit 3 is input to MP1 / G and MP2 / G, and the coefficient current of the control current that determines the delay time of each of the delay circuits 15a to 15d in the variable frequency oscillation circuit 13 is obtained. Occurs at the drain terminal. MP1 / D and MN1 / D and MP2 / D and MN2 / D are connected, and the connection points are named HERRB and LERR. It should be noted that the control voltage VD1 for driving the N-type transistor and the control voltage VD2 for driving the P-type transistor are conversely changed even if the type of transistors connected in the circuit configuration is changed so as to drive the P-type transistor and the N-type transistor, respectively. good. The ratio (W / L) of the gate width W and the gate length L of each transistor of MP1 and MN1 is set to set the current ratio [I (MP1 / D) / I (MN1 / D)]> 1. In the following description, the current ratio [I (MP1 / D) / I (MN1 / D)] = 4/3. The ratio (W / L) of the gate width W and the gate length L of each transistor of MP2 and MN2 is set to a current ratio [I (MP2 / D) / I (MN2 / D)] 1. In the following description, the electric ratio [I (MP2 / D) / I (MN2 / D)] = 3/4 is set.
[0032]
Terminals HERRB and LERR are input to a set terminal of DFF1 and DFF2 (asynchronous reset at L level) via INV2, INV1 and INV3, respectively. The outputs of INV2 and INV3 are input to MN3 / G and MP3 / G, and MP3 / S and MN3 / S are connected to the power supply and GND, respectively. MP3 / D and MN3 / D are both connected to an error voltage VC1 that is the output of the charge pump circuit 5. The data inputs of DFF1 and DFF2 are both connected to a power source, and a reference signal R1 (P0) and a comparison signal V1 (Pn) are connected to each clock input. The Q outputs of DFF1 and DFF2 are input to AND1, and the output of AND1 is input to the reset input (reset operation at L level) of the phase comparison circuit 4. When the phase comparison circuit 4 is reset, the output of the up pulse and the down pulse is stopped. When this reset operation is canceled, when the valid edge of the reference signal R (comparison signal V) first arrives, an up pulse (down pulse) is generated and the next valid edge of the comparison signal V (reference signal R) is increased. Normal operation to reset the pulse (down pulse).
[0033]
Operation explanation of DLL malfunction prevention circuit
When the DLL circuit 2 and the PLL circuit 3 are in a desired operation state, the HERRB point for detecting that the control current in the DLL circuit 2 is excessive (the delay time of the delay circuits 15e to 15n is small) becomes H level. The LERR point for detecting that the control current in the DLL circuit 2 is excessively small (the delay time of the delay circuits 15e to 15n is large) becomes L level. In this case, MP3 and MN3 are in the OFF state, and the Q outputs of DFF1 and DFF2 are both at the H level. Therefore, the output of AND1 becomes H level, the phase comparison circuit 4 is in the normal operation state, and the DLL malfunction prevention circuit 1 does not affect the main operation of the DLL circuit 2 in the desired operation state. If the control current of the DLL circuit 2 becomes abnormally smaller than 3/4 of the desired current, the LERR point changes to H level, immediately resets the DFF2 and sets the ANDl output to L level, and the phase comparison circuit 4 The input of the output up pulse and the down pulse to the charge pump circuit 5 is cut off. In addition to this, MP3 is turned on to forcibly increase the error voltage VCl, and the control current is increased until the LERR point changes to the L level.
[0034]
The operation of returning the DLL circuit 2 to normal control after the LERR point changes to the L level will be described with reference to the time chart shown in FIG. At this time, since the control current is still smaller than the desired control current value, the comparison signal V (Pn) is delayed by one cycle or more from the reference signal R (P0) as shown in the figure. For example, when the LERR point changes to the L level at time tx1, as shown in FIG. 7a, the first edge that arrives is the effective edge of the reference signal Rl. The generation of the up pulse Ul ends. By this up pulse, the error voltage VC1 output from the charge pump circuit 5 is increased, the control current is increased, the delay times of the delay circuits 15e to 15n are decreased, and the desired delay time is converged. However, if LERR changes to L level at time tx2, when the operation of the phase comparison circuit 4 is immediately restored, the effective edge of the comparison signal V1 first arrives as shown in FIG. The generation of the down pulse Dl is terminated at the next effective edge of the reference signal R1. In this case, on the contrary, the error voltage VC1 is lowered to decrease the control current, and the delay time of the delay circuits 15e to 15n is increased, so that the normal return operation cannot be performed. For this purpose, there is DFF2 using the comparison signal Vl as a clock. The Q output of DFF2 can change to the H level after the effective edge of the comparison signal Vl arrives. As shown in FIG. 7c, the phase comparison circuit 4 always starts operation from the effective edge of the reference signal R1, and is always up. A pulse U1 is generated to return to the normal control operation. Next, if the control current of the DLL circuit 2 becomes abnormally larger than 4/3 of the desired current, the HERRB point changes to L level, immediately resets DFFI and sets the ANDl output to L level, and the phase comparison circuit 4 The input of the output up pulse and the down pulse to the charge pump circuit 5 is cut off. In addition, MN3 is turned on to forcibly lower the error voltage VCl, and the control current is decreased until the HERRB point changes to H level. The operation of returning the DLL circuit 2 to normal control after the HERRB point changes to the H level will be described with reference to the time chart shown in FIG. At this time, since the control current is still larger than the desired control current value, the comparison signal V (Pn) is advanced from the reference signal R (P0) by a desired one cycle delay as shown in the figure. For example, when the HERRb point changes to the H level at time tx1, as shown in FIG. 8a, the first edge that arrives is the effective edge of the comparison signal V1, so the down edge D1 is generated and the effective edge of the reference signal R1 that arrives next is reached. Then, the generation of the down pulse D1 is completed. Due to this down pulse, the error voltage VC1 output from the charge pump circuit 5 is lowered to decrease the control current, thereby increasing the delay time of the delay circuits 15e to 15n to converge to the desired delay time. However, if HERRB changes to H level at time tx2, when the operation of the phase comparison circuit 4 is immediately restored, the effective pulse of the reference signal R1 first arrives as shown in FIG. The generation of the up pulse U1 is terminated at the next valid edge of the comparison signal V1. In this case, on the contrary, the error voltage VC1 is increased to increase the control current, and the delay time of the delay circuits 15e to 15n is decreased, so that the normal return operation cannot be performed. For this purpose, there is DFFl using the reference signal R1 as a clock. The Q output of DFF1 can change to the H level after the effective edge of the reference signal R1 arrives. As shown in FIG. 8c, the phase comparison circuit 4 always starts operation from the effective edge of the comparison signal V1 and is always down. A pulse D1 is generated to return to the normal control operation. Therefore, malfunction of the DLL circuit of this embodiment can be prevented.
[0035]
In this embodiment, the DLL circuit 2 and the delay circuit included in the PLL circuit are set to be in the same operation state (delay time = 1/8 cycle) in order to simplify the explanation, but the relative values of the control currents can be generally managed. It is clear that the DLL circuit according to the present invention can be implemented if configured.
[0036]
【The invention's effect】
As described above, the present invention has the following effects.
[0037]
There is no equilibrium (convergence) state of malfunction that is in the conventional DLL circuit. This is always realized as well as limited conditions such as when the power is turned on. That is, even if an abnormal state is entered, it can be automatically restored, and this restoration operation can be performed in a short time. For this reason, it can be applied to a general digital signal processing system as well as a PLL circuit. Therefore, the accuracy of the absolute time axis by the PLL circuit and the accuracy of the asynchronous time axis by the DLL circuit can be increased, and various digital signal processing can be performed with high accuracy, which can be easily realized by LSI technology using the CMOS process.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of an embodiment
FIG. 2 is a block diagram showing the configuration of the variable frequency oscillation circuit 13
FIG. 3 is a block diagram showing a configuration of control delay circuits 15a to 15d.
FIG. 4 is a block diagram showing the configuration of the delay chain circuit 7
FIG. 5 is a diagram showing a general charge pump circuit
FIG. 6 is a diagram showing a charge pump circuit to be used
FIG. 7 is a time chart for returning the DLL circuit 2;
FIG. 8 is a time chart for returning the DLL circuit 2;
FIG. 9 is a time chart of the synchronous clock generation circuit 14;
FIG. 10 shows a conventional DLL circuit.
FIG. 11 is a time chart showing the operation of a conventional DLL circuit.
FIG. 12 is a diagram showing a general PLL circuit
[Explanation of symbols]
1 DLL malfunction prevention circuit
2 DLL circuit
3 PLL circuit
4 Phase comparison circuit
5 Charge pump circuit
6 Control signal generation circuit
7 Delay chain circuit
8 Crystal oscillator circuit
12 divider circuit
13 Variable frequency oscillator
15a to 15n control delay circuit

Claims (2)

A DLL system that includes a delay chain circuit in which first control delay circuits are connected in cascade, to which a first clock signal that is an output signal of a variable frequency oscillation circuit is input, and that controls a signal delay time of the delay chain circuit In
A PLL circuit for controlling the output signal of the variable frequency oscillating circuit including a plurality of second controlled delay circuit, the coefficient times the second clock signal frequency to be inputted, first to control the first controlled delay circuit a comparator circuit for comparing the second control signal for controlling the control signal and the second control delay circuit, the operation of the phase comparator circuit included in the DLL circuit compares the result of the comparison circuit based on A DLL system comprising: a control circuit for stopping and transitioning an output voltage of a charge pump circuit included in the DLL circuit in a desired voltage direction based on the comparison result. According to claim 1, wherein the DLL system, to the comparison circuit, provided with a first and second comparator circuits each set value are different from each other, the phase comparison circuit with a comparison result of the first or second comparison circuit A DLL system comprising a control circuit for stopping operation and causing transition to different desired voltage directions based on a comparison result of the first and second comparison circuits.

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