JP2001257586A - Dll system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DLL system without the convergence of malfunction. SOLUTION: A DLL malfunction preventing circuit 1 inputs a control voltage VD1 from a DLL circuit and a control voltage VD2 from a PLL circuit 3. When the control current of the DLL circuit is changed to an abnormal value, the operation of a phase control circuit 4 is stopped, the output of a charge pump circuit 5 is controlled via the circuits of MP3 and MN3 and the control current is controlled to become a normal value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DLL capable of inputting a clock signal whose phase changes discontinuously by a trigger signal and outputting a multi-phase clock signal in which each clock phase is controlled. (Delay locked loop) circuit.

[0002]

2. Description of the Related Art A PLL (Phase Locked Loop) circuit is similar to a DLL circuit.
Before describing the DLL circuit, the PLL circuit will be described. FIG.
Reference numeral 2 denotes a configuration example of a PLL circuit. X'tal
Oscillation circuit 8 can easily generate only with a crystal oscillator 3
A reference clock signal of 0 MHz or less is output and input to the reference signal input R2 of the phase comparison circuit 9. Control voltage VD
The variable frequency oscillation circuit 13 controlled by 2 outputs a reference clock K used for the system. The reference clock K is input to the frequency dividing circuit 12, outputs a frequency-divided N clock signal, and is input to the comparison input V2 of the phase comparing circuit 9. When the comparison signal V2 is delayed in phase (advanced in phase) with respect to the reference signal R2, the phase comparison
2 (down pulse D2). If the phases of the comparison signal V2 and the reference signal R2 match, neither the up pulse U2 nor the down pulse D2 is output. These up pulse U2 and down pulse D2 are input to the charge pump circuit 10 to generate an error voltage VC2.

The error voltage VC2 is supplied to a control signal generation circuit 11
Is input to The control signal generation circuit 11 generates a control voltage VD2 for generating a control current for determining the output frequency of the variable frequency oscillation circuit 13. The control voltage VD2 is input to the variable frequency oscillation path 13. A resistor Rd and a capacitor Co are connected to the output of the charge pump circuit 10 to set the AC conversion gain to a predetermined finite value, and to control loop stability which is impeded by integration of the control phase error by the variable frequency oscillation circuit 13. Is secured.

At present, a digital phase comparator is generally employed as the phase comparator 9. Since the digital phase comparison circuit 9 has the frequency detection capability in addition to the phase difference detection capability, the PLL circuit can realize a stable configuration without any malfunction condition. As the output reference clock K,
It can generate a stable clock signal having a frequency N times higher than the clock signal generated by the X'taI oscillation circuit 8 and a high frequency which cannot be obtained by the X'taI oscillation circuit. The PLL circuit is generally used in a digital circuit (LSI) in which the precision is increasing.

Description of a conventional DLL circuit In a digital system, there is a case where signal processing with higher accuracy is performed using a clock signal whose phase changes discontinuously by a trigger signal. If the clock signal whose phase changes discontinuously is used as the reference signal R2, the PLL circuit loses the equilibrium state every time a phase change occurs, and the pull-in operation must be performed again, so that it cannot be used systematically. In this case, a DLL circuit is used.

FIG. 10 shows a configuration example of a conventional DLL circuit. The aforementioned clock signal SCK whose phase changes discontinuously is input to a delay chain circuit 7 in which a plurality of delay circuits whose delay time can be controlled are connected in cascade, and N multi-phase clock signal groups P0 whose phases are sequentially delayed are ~ PN. The clocks P0 and PN are input to the phase comparison circuit 4 as the reference signal R1 and the comparison signal V1. The output up pulse U1 and down pulse Dl are input to the charge pump circuit 5 and output an error voltage VCl. Error voltage VC1 is controlled by control signal generation circuit 6 to control voltage VD1.
And is input to the delay chain circuit 7 to control the delay time in the internal delay circuit. In the DLL circuit, unlike the PLL circuit, since the control phase error is not integrated by the delay chain circuit 7 and the loop stability is not hindered, the filter for suppressing the AC gain to the finite value at the output of the charge pump circuit 5 is used. No circuit is needed.

Therefore, as shown in FIG. 11A, the clock signal PN is controlled so as to be balanced in a state where the clock signal PN becomes a clock signal whose phase is delayed by the clock signal period with respect to P0. The clock signals P0 to P (N-1) are controlled timing signals within a clock cycle, and highly accurate digital signal processing can be performed using these clock signals.

As described above, digital signal processing is
PLL that can improve the accuracy of continuous clock (absolute time axis)
Attempts are being made to achieve high-precision signal processing by using both a circuit and a DLL circuit capable of increasing the precision of a clock (asynchronous time axis) whose phase varies discontinuously.

[0009]

However, the conventional DLL circuit has the following problem of malfunction.

(Problem 1) As shown in FIG.
When 1 (PN) is delayed by two cycles with respect to the reference signal Rl (P0), as can be seen from the figure, both the up pulse U1 and the down pulse D1 are not generated at all, as in the case of 1 cycle delay, and are balanced as they are. Would. In this state, this phenomenon occurs with an integer multiple period delay of twice or more. To avoid this malfunction, the control voltage generation range in the control signal generation circuit 6 may be limited.
In the case of using an OS circuit (general), it is impossible to cope with a large variation in element characteristics.

(Problem 2) The comparison signal V1 as shown in FIG.
When (PN) is advanced by a desired one cycle delay with respect to the reference signal R1 (P0), the down pulse D1 is output without outputting the up pulse U1, and the comparison signal V1 is output.
(PN) and balance it to the desired one-cycle delay. However, this operation is not guaranteed in the phase comparison circuit.

As shown in FIG. 11D, on the contrary, the up pulse U1 is generated without generating the down pulse D1, and the phase of the comparison signal V1 (PN) further advances to the control capability limit of the control signal generation circuit 6. You cannot escape from this state.

With respect to the malfunction of the DLL circuit described above, the frequency detection function of the digital phase comparator which is effective in the PLL circuit has no effect. The DLL circuit is a very effective circuit, but it cannot be widely used in a digital signal processing system unless this malfunction problem is fundamentally solved.

The present invention has been made under such circumstances, and an object of the present invention is to provide a DLL system in which there is no balance (convergence) of malfunctions.

[0015]

According to the present invention, a DLL system is configured as described in the following (1) and (2) to achieve the above object.

(1) In a DLL system which has a delay chain circuit in which first control delay circuits to which a first clock signal is input are connected in cascade, and controls the signal delay time of the delay chain circuit, For controlling the output signal of the variable frequency oscillation circuit including a plurality of control delay circuits to a coefficient multiple of the input second clock signal frequency
Circuit, a representative value of a first control signal for controlling the first control delay circuit, and a second value for controlling the second control delay circuit.
A comparison circuit for comparing the representative values of the control signals, and stopping the operation of the phase comparison circuit included in the DLL circuit based on the comparison result of the comparison circuit, and the output of the charge pump circuit included in the DLL circuit. A DLL system comprising a control circuit for changing a voltage in a desired voltage direction based on the comparison result.

(2) In the DLL system according to the above (1), the comparison circuit is provided with first and second comparison circuits having different representative value ratios, and the first and second comparison circuits are different from each other. A DLL system provided with a control circuit for stopping the operation of the phase comparison circuit based on the comparison result, and performing transition to different desired voltage directions based on the comparison result of the first and second comparison circuits.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be
This will be described in more detail with an embodiment of the system.

[0019]

FIG. 1 is a diagram showing the configuration of a DLL system according to an embodiment. In this embodiment, DLL circuits 2 and D
It comprises an LL malfunction prevention circuit 1, a PLL circuit 3, and a synchronous clock signal generation circuit 14.

Description of PLL Circuit 3 for Generating Multi-Phase Clock Group Since the PLL circuit 3 is basically the same as the configuration of FIG. 12, only the differences will be described. The variable frequency oscillating circuit 13 can generate multi-phase clock groups K0 to Km (m is an integer). FIG. 2 shows a configuration example of the variable frequency oscillation circuit 13 when m = 7. The positive output Po and the negative output No of the delay circuit 15a for delaying the differential signal are the positive input Pi and the negative input N of the delay circuit 15b having the same configuration.
Input to i. Similarly, the positive output Po and the negative output No of the delay circuit 15b are input to the delay circuit 15c having the same configuration. The same applies to the delay circuit 15d,
The positive output Po and the negative output No are input to the negative input Ni and the positive input Pi of the delay circuit 15a to form an oscillation circuit. The differential outputs Po and No of the delay circuits 15a to 15d
Output multi-phase clock groups K0 to K7 via differential buffers 16a to 16d. Also, delay circuits 15a to 15d
The control voltage VD2 is input to the control terminal Vd, and the oscillation frequency is controlled by controlling the delay time of each delay circuit.

Delay circuits 15a to 15 for delaying differential signals
Description of d FIG. 3 shows an example of the configuration of a CMOS circuit of the delay circuits 15a to 15d. The drive voltage Vd is MN1
/ G, MN3 / G. The drain current I1 of MN3 is connected to the sources of the source couples MN2 and MN4. MN2 / G and MN4 / G have positive signal Pi,
The negative signal Ni is input. MN1 / D is input to the gate-drain short circuits MP1 / D, MP2 / G and MP3 / G. MP2 / D and MP3 / D, both of which output current I2, are connected to MN2 / D and MN4 / D, respectively, and have a gate-drain short circuit MN5 / S and MN6.
/ S is connected to output a positive signal Po and a negative signal No. If I2 = I1 / 2, charging and discharging are performed by the current I2 in each of the Po and No transition periods. Since the current I2 is determined by the drive voltage VD, the input / output delay time can be controlled.

Description of Synchronous Clock Signal Generating Circuit 14 The multi-phase clock groups K0 to Km are output to a digital signal processing unit (not shown) that requires a high-precision absolute time axis, and are sent to the synchronous clock signal generating circuit 14. Is entered. FIG. 9 is a time chart for explaining the operation of the synchronous clock signal generation circuit 14. FIG. 7A shows the synchronization trigger signal SYNC, and FIG. 7B shows the synchronization clock signal SCK. When the valid timing of the synchronization trigger signal SYNC occurs at time ts, it is delayed (synchronized) by a certain period T1.
A clock signal having the same cycle as that of the clock groups K0 to Km is immediately generated. Since the clock groups K0 to Km and the synchronous trigger signal SYNC are completely asynchronous, the time t at which the valid timing of the synchronous trigger signal SYNC occurs.
The phase of the output clock signal jumps (discontinuous) at s. That is, the synchronous clock signal SCK controls an asynchronous time axis. Also, the synchronous clock signal SCK
Of the synchronization trigger signal SYNC is determined by the respective phase differences of the multiphase clock groups K0 to Km.

Description of DLL Circuit Generating Multi-Phase Clock The synchronous clock signal SCK is input to a delay chain circuit 7 in the DLL circuit 2. The difference between the DLL circuit 2 and the conventional example of FIG. 10 will be described. FIG. 4 shows a configuration example of the delay chain circuit 7. Here, the case where N = 8 will be described. The synchronous clock signal SCK is input to the differential buffer 17 and is converted into a differential signal. This differential signal is connected in cascade with nine delay circuit groups 15e to 15e each having the same configuration.
n. Control voltage V for controlling each delay time
D1 is input to the control terminal Vd, and the differential outputs Po and No of the delay circuits are respectively output to the single-phase buffers 18a to 18h.
To output the multi-phase clock groups P0 to P8. The delay circuit 15n in which the output differential signal is not used is for obtaining the same operation as in the other delay circuits 15e to 15m. Since the delay times of the delay circuits 15e to 15n in the delay chain circuit 7 and the delay circuits 15a to 15d in the variable frequency oscillation circuit 13 in the PLL circuit 3 can be made equal, the control current controlled by the control voltages VD1 and VD2 is It is only the difference due to variation. However, it cannot be driven by the control voltage VD2 of the PLL circuit 3 as the delay chain circuit 7. This relative variation is due to the large absolute variation of the element.
Even in the MOS process, it is possible to keep it to 10% or less.

Description of Charge Pump Circuit FIG. 5 shows a general configuration of a charge pump circuit used in the PLL circuit 3 and the DLL circuit 2. The negative up pulse NU and the positive down pulse PD are MP1 / G and M, respectively.
N1 / G, MP1 / D, MN1 / D and the capacitor Cl are connected to output an error voltage VC. In MN1 / S, a down current I1 is generated by MN2, and MP1 / S
, An up current I2 is generated by MP2, MP3 and MN3.

The same bias VB1 is input to MN2 / G and MN3 / G to ensure the correlation between the currents I1 and I2. Usually, the (W / L) ratio of the related transistors is set so that the down current I1 and the up current I2 are equal. However, this charge pump circuit has two problems. MN2 and MN3 and MP2 and MP3
It is impossible to design the drain-source voltage of each of them almost equal, and it fluctuates with respect to the absolute variation of the element (especially the current driving capability) and the environment (operating temperature, power supply voltage). I1 and up current I2 cannot be balanced. When this is considered regularly,
This means that an equilibrium state is established when the input up pulse width and down pulse width are shifted, and the comparison signal V converges in a state where the phase is shifted from the reference signal R. In addition, MP1 is generated by up pulse and down pulse.
And MN1 are off, MP1 / S and MN1
/ S moves toward the power supply and GND, respectively, and the current driving capability of MP2 and MN2 is lost. When MPl and MN1 change from this state to ON, first, MPl / S
(MN1 / S) is lowered (increased), and then MP2 (MN
The current drive capability of 2) is restored to generate an up current I2 (down current I1), thereby supplying a current to the charge pump terminal and changing the error voltage VC.

As described above, in the charge pump circuit of FIG. 2, the transient characteristics are not ideally performed, and not only the high-speed operation is performed, but also the comparison signal V in the equilibrium state converges with the phase shifted from the reference signal R. Have the factor to. The above operation is fatal in the DLL circuit 2.

The present inventor has proposed a charge pump circuit having the configuration shown in FIG.

The differential up pulse (N
U, PU) are input to MP1 / G and MP4 / G, respectively, and the differential down pulses (PD, ND), which have also been converted into differential signals, are input to MN1 / G and MN4 / G, respectively. MP1 / S and MP4S are connected and connected to MP2 / D that supplies up current I2, while MN1 / S and MN4 / S are connected and connected to MN2 / D that supplies down current. MP1 / D and MIN1 / D and MP4 / D and MN4 / D are connected respectively, and the connection point between MP1 / D and MN1 / D is a power supply and a GN.
The capacitors CI and C2 connected to D are connected and output as an error voltage VC. The error voltage VC is input to the voltage buffer 21, and its output is connected to a connection point between MP4 / D and MN4 / D. MN3 driven by the same bias VB1 as MN2 generates a coefficient current of down current I1 and
Connected to P3 / D. Since MP3 / G and MP2 / G are connected, a coefficient current of an up current is generated in MP3 / D. Then, MN5, MN6, MN7 and MP are set so that the current value of MP3 / D becomes equal to the current value of MN3 / D.
5, a control circuit composed of MP6 and resistors R1 and R2 controls the current balance between the up current I2 and the down current Il. The voltage in the current balance is determined by the resistors R1 and R2, and is usually set to half of the power supply voltage at which the operating voltage range of the error voltage VC is the widest (that is, R1 = R2).

The charge pump circuit of FIG. 6 not only dramatically improves the balance between the up current and the down current, but also
MP1 or MN1 related to the charge pump operation is O
During FF, MP4 or MN4 turns on and MP1 /
By maintaining the S and MNl / S voltages, the up current source MP2 and the down current source MN2 can always be in operation. Moreover, since the error voltage VC is input to the connection point between MP4 / D and MN4 / D via the voltage buffer 21, the voltage between the drain and the source when the transistors MP1 and MP4 and the transistors MN1 and MN4 are turned on and off. , The charge pump operation for the change of the up pulse and the down pulse is remarkably quick.

If the element values of the capacitors C1 and C2 connected to the error voltage VC terminal are set so as to satisfy the resistance ratio (R1 / R2) and the capacitance ratio (C2 / Cl), power supply noise is reduced. Become stronger. The charge pump circuit having the configuration shown in FIG. 6 can also be used in the PLL circuit 2.

Description of Configuration of DLL Malfunction Prevention Circuit The DLL malfunction prevention circuit 1 included in the DLL circuit 2 will be described. The control voltage VD1 is MN1 / G and MN
2 / G, and generates, at each drain terminal, a coefficient current of a control current that determines the delay time of each of the delay circuits 15e to 15n in the delay chain circuit 7. On the other hand, PLL
The control voltage VD2 generated by the circuit 3 is MP1 / G and MP
2 / G, and generates, at each drain terminal, a coefficient current of a control current that determines the delay time of each of the delay circuits 15a to 15d in the variable frequency oscillation circuit 13. Also MP1
/ D and MN1 / D and MP2 / D and MN2 / D are connected, and their connection points are named HERRB and LERR. Note that the control voltage VD1 for driving the N-type transistor and the control voltage VD2 for driving the P-type transistor may be changed even if the type of the transistors connected by changing the circuit configuration to drive the P-type transistor and the N-type transistor is changed. good. The ratio (W / L) of the gate width W and the gate length L of each transistor of MP1 and MN1 is set so that the current ratio [I (MP1 / D) / I (MN1 / D)]> 1. In the following description, the current ratio [I (MP1 / D) / I
(MN1 / D)] = 4/3. MP2 and MN
2, the ratio (W / L) of the gate width W and the gate length L of each transistor is set and the current ratio [I (MP2 / D) / I
(MN2 / D)]. In the following description, the electrical ratio [I (MP2 / D) / I (MN2 / D)] = 3/4.

Terminals HERRB and LERR are each INV
2 and DFF1 and DFF via INV1 and INV3
It is input to the second glue set terminal (asynchronous reset at L level). INV2 output and INV3 output are MN3 / G
And MP3 / G, MP3 / S and MN3 / S
Are connected to a power supply and GND, respectively. MP3 / D and MN3 / D are both connected to an error voltage VC1, which is an output of the charge pump circuit 5. DFF1 and DFF2
Are connected to a power supply, and each clock input is connected to a reference signal R1 (P0) and a comparison signal V1 (Pn). Each Q output of DFF1 and DFF2 is input to AND1, and the output of AND1 is input to the reset input (reset operation at L level) of the phase comparison circuit 4. When reset, the phase comparison circuit 4 stops outputting the up pulse and the down pulse. When the reset operation is released, first, the reference signal R (comparison signal V)
When the effective edge of (1) arrives, an up pulse (down pulse) is generated, and the normal operation of resetting the up pulse (down pulse) at the next effective edge of the comparison signal V (reference signal R).

Description of Operation of DLL Malfunction Prevention Circuit When the DLL circuit 2 and the PLL circuit 3 are in a desired operation state, it is considered that the control current in the DLL circuit 2 is excessive (the delay time of the delay circuits 15e to 15n is short). The HERRB point to be detected is at the H level. The LERR point that detects that the control current in the DLL circuit 2 is too small (the delay time of the delay circuits 15e to 15n is large) becomes L level. In this case, MP3 and MN3 are in the OFF state, and the Q outputs of DFF1 and DFF2 are both at the H level. Therefore, the output of AND1 becomes H level,
The phase comparison circuit 4 is in a normal operation state, and the DLL malfunction prevention circuit 1 has no influence on the main operation of the DLL circuit 2 in a desired operation state. If the control current of the DLL circuit 2 becomes abnormally smaller than the desired current by less than 3/4, LE
The RR point changes to the H level, and immediately resets the DFF 2 to set the ANDl output to the L level to cut off the input of the up pulse and the down pulse of the output of the phase comparison circuit 4 to the charge pump circuit 5. In addition, MP3 is turned on to forcibly raise the error voltage VCl, and the LERR point becomes L
Increase the control current until it changes to the level.

After the LERR point changes to L level, DLL
The operation of returning the circuit 2 to the normal control will be described with reference to a time chart shown in FIG. At this time, since the control current is still smaller than the desired control current value, the comparison signal V (Pn) is one cycle or more behind the reference signal R (P0) as shown in the figure. For example, when the LERR point changes to the L level at the time tx1, as shown in FIG. 7A, the first edge arrives at the effective edge of the reference signal R1, so that an up pulse Ul is generated and the effective edge of the comparison signal V1 arrives next. Terminates the generation of the up pulse Ul. With this up pulse, the error voltage VC1 output from the charge pump circuit 5 is increased to increase the control current, thereby reducing the delay time of the delay circuits 15e to 15n and converging to the desired delay time. However, if the LERR changes to the L level at time tx2, the operation of the phase comparison circuit 4 is immediately returned to FIG.
As shown in b, the down pulse D1 is generated because the effective edge of the comparison signal V1 first arrives, and the generation of the down pulse D1 ends at the next effective edge of the reference signal R1. In this case, conversely, the error voltage VC1 is decreased to decrease the control current, so that the delay time of the delay circuits 15e to 15n is increased, and the normal return operation cannot be performed. Therefore, the comparison signal V
There is a DFF 2 using 1 as a clock. The Q output of the DFF 2 can change to the H level after the arrival of the valid edge of the comparison signal Vl. As shown in FIG. 7C, the phase comparison circuit 4 always starts operating from the valid edge of the reference signal R1, and always rises. A pulse U1 is generated to return to the normal control operation. Next, the control current of the DLL circuit 2 becomes 4/3 of the desired current.
HERRB point changes to L level, DFFI is immediately reset, and AN
The output of Dl is set to L level, and the input of the up pulse and the down pulse output from the phase comparison circuit 4 to the charge pump circuit 5 is cut off. In addition, MN3 is turned on to forcibly lower the error voltage VCl, and the control current is reduced until the HERRB point changes to the H level. An operation of returning the DLL circuit 2 to the normal control after the HERRB point changes to the H level will be described with reference to a time chart shown in FIG. At this time, since the control current is still larger than the desired control current value, the comparison signal V (Pn) is ahead of the reference signal R (P0) by a desired one cycle delay as shown in the figure. For example, when the HERRb point changes to the H level at time tx1, the comparison signal V arrives first as shown in FIG. 8A.
1, the down pulse D1 is generated, and the down pulse D1 is generated at the next valid edge of the reference signal R1.
Terminate the occurrence. With this down pulse, the error voltage VC1 output from the charge pump circuit 5 is lowered to reduce the control current, thereby increasing the delay time of the delay circuits 15e to 15n and converging to the desired delay time. However, if time t
When HERRB changes to the H level at the time of x2, if the operation of the phase comparison circuit 4 is immediately resumed, as shown in FIG. 8B, the effective edge of the reference signal R1 arrives first, so that the up pulse U1 is generated and then arrives. The generation of the up pulse U1 ends at the valid edge of the comparison signal V1. In this case, conversely, the error voltage VC1 is increased to increase the control current, and the delay time of the delay circuits 15e to 15n is reduced, so that the normal return operation cannot be performed. For this purpose, there is a DFF1 clocked by the reference signal R1. The Q output of the DFF1 can change to the H level after the arrival of the valid edge of the reference signal R1. As shown in FIG. 8C, the phase comparison circuit 4 always starts operating from the valid edge of the comparison signal V1 and always goes down. A pulse D1 is generated to return to the normal control operation. Therefore, malfunction of the DLL circuit of this embodiment can be prevented.

In this embodiment, for simplicity of description, DL
Although the L circuit 2 and the delay circuit included in the PLL circuit are set to the same operation state (delay time = 1/8 cycle), the DL circuit according to the present invention can be controlled if the relative values of the control currents can be substantially managed.
It is clear that the L circuit can be implemented.

[0036]

As described above, the present invention has the following effects.

There is no equilibrium (convergence) state of malfunction in the conventional DLL circuit. This is always realized not only under limited conditions such as when power is turned on. That is, even if the state once falls into an abnormal state, the state can be automatically recovered, and the return operation can be performed in a short time.
Therefore, it can be widely applied to general digital signal processing systems as well as the PLL circuit. Therefore, PL
The accuracy of the absolute time axis can be improved by the L circuit, and the accuracy of the asynchronous time axis can be improved by the DLL circuit. Therefore, the digital signal processing can be performed with a variety of high precision, and can be easily realized by LSI technology using a CMOS process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a block diagram showing a configuration of a variable frequency oscillation circuit 13.

FIG. 3 is a block diagram showing a configuration of control delay circuits 15a to 15d.

FIG. 4 is a block diagram showing a configuration of a delay chain circuit 7;

FIG. 5 is a diagram showing a general charge pump circuit;

FIG. 6 is a diagram showing a charge pump circuit to be used;

FIG. 7 is a time chart of the return of the DLL circuit 2;

FIG. 8 is a time chart of the return of the DLL circuit 2;

FIG. 9 is a time chart of the synchronous clock generation circuit 14;

FIG. 10 is a diagram showing a conventional DLL circuit;

FIG. 11 is a time chart showing the operation of a conventional DLL circuit;

FIG. 12 is a diagram showing a general PLL circuit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DLL malfunction prevention circuit 2 DLL circuit 3 PLL circuit 4 Phase comparison circuit 5 Charge pump circuit 6 Control signal generation circuit 7 Delay chain circuit 8 Crystal oscillation circuit 12 Divider circuit 13 Variable frequency oscillation circuit 15a to 15n Control delay circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // G06F 1/06 H03L 7/08 J G06F 1/04 311Z F-term (Reference) 5B079 BA20 BB10 BC03 CC02 CC14 DD02 DD03 DD06 DD20 5J001 AA05 BB00 BB05 BB08 BB12 BB14 BB20 BB24 DD06 5J106 AA04 CC01 CC15 CC30 CC41 CC58 CC59 DD08 DD24 DD32 DD42 DD43 DD48 EE10 FF04 GG04 GG15 HH03 HH08 JJ09 KK30 LL07

Claims (2)

[Claims] A first clock signal input to the first clock signal;
In the DLL system for controlling the signal delay time of the delay chain circuit, the output signal of the variable frequency oscillation circuit including a plurality of second control delay circuits is input. And a second circuit for controlling the second control delay circuit and a representative value of a first control signal for controlling the first control delay circuit and a second control signal for controlling the second control delay circuit. A comparison circuit for comparing a representative value of the control signal, and stopping the operation of a phase comparison circuit included in the DLL circuit based on a comparison result of the comparison circuit, and an output voltage of a charge pump circuit included in the DLL circuit. And a control circuit for making a transition to a desired voltage direction based on the comparison result. 2. The DLL system according to claim 1, wherein said comparison circuit includes first and second different representative value ratios.
And a second comparison circuit, and the first or second
A control circuit for stopping the operation of the phase comparison circuit based on the comparison result of the comparison circuit, and performing a transition to a desired voltage direction different from each other based on the comparison result of the first and second comparison circuits. .