KR101480621B1 - Clock Generator of using Delay-Locked Loop - Google Patents

Abstract

A clock generator using a delay locked loop is disclosed. The delay locked loop of the clock generator is provided with a voltage controlled delay stage for performing phase delay and canceling the phase change due to the jitter component. The voltage controlled delay stage performs a delay operation on the input signal, and the delay operation is performed through the output signal of the loop filter and the variation of the phase change signal generated in each delay stage. The phase change signal is obtained by converting the phase of the input signal of the delay stage and the phase of the output signal into the form of a voltage having a certain level, thereby quickly eliminating jitter components generated in the delay.

Description

Clock Generator of Using Delay-Locked Loop [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator using a delay locked loop, and more particularly to a clock generator with a jitter component removed or reduced.

2. Description of the Related Art In recent years, as the operation speed of a system such as a computer has increased, a clock generator for maintaining stable operation has been demanded. Particularly, in a communication system, an electronic system such as a central processing unit, a memory, and the like, a clock generator is a very important factor. In the case of high-speed processing, a high frequency clock signal that matches the operating speed of the digital circuitry is required.

However, it is very difficult to generate a clock signal from which noises or jitter components have been removed through interfacing between chips formed through a silicon-based semiconductor manufacturing process, and a circuit for receiving the clock signal from the outside and processing the chip in the chip is required do. A phase-locked loop is often used as a generator of such an internal clock.

A typical phase locked loop has a closed loop feedback structure using a VCO (Voltage Controlled Oscillator). It is difficult to design because it is a higher order system and there is a problem that the bandwidth of the loop is changed by external variables such as temperature even in stable operation. In addition, there is a disadvantage that the fixed time (lock-in time) is slow and the jitter component is accumulated in the VCO or the like.

Accordingly, a clock generator in which a noise or a jitter component is removed by detecting a change in phase due to jitter or a noise component in the delay locked loop itself and securing a stable fixed state by eliminating the phase change will be required.

Disclosure of Invention Technical Problem [8] The present invention provides a clock generator using a delay locked loop for detecting and compensating for jitter components generated therein.

According to an aspect of the present invention, there is provided a phase error detector comprising: a phase detector for comparing an input signal and a delay output signal to detect a phase difference to form an up signal or a down signal; A charge pump for forming a charge / discharge current according to the up-signal or the down-signal of the phase detector; A loop filter for forming a delay control signal according to charge / discharge current of the charge pump; A voltage control delay stage for generating the delay output signal through a delay operation on the input signal in accordance with the delay control signal and correcting a phase change according to a jitter or a noise component generated in a delay operation through a phase change signal; And a frequency multiplier that receives signals delayed for each stage of the voltage controlled delay stage to form a pulse signal, and combines the signals to form an output signal.

According to the present invention, the clock generator has a voltage-controlled delay stage and corrects a phase change due to jitter and the like generated in the delay unit in the phase-change voltage converter. This compensates for the phase change due to jitter or noise during operation of the clock generator and reduces the jitter of the output signal. In addition, it is possible to smoothly remove the noise or jitter generated due to the motion of the input signal or the internal circuit, thereby performing a smooth frequency multiplication operation.

1 is a block diagram illustrating a clock generator according to a preferred embodiment of the present invention.
2 is a circuit diagram showing the phase detector of FIG. 1 according to a preferred embodiment of the present invention.
3 is a circuit diagram illustrating the operation of the charge pump and the loop filter of FIG. 1 according to an embodiment of the present invention.
4 is a block diagram illustrating the voltage controlled delay stage of FIG. 1 according to a preferred embodiment of the present invention.
5 is a circuit diagram illustrating the delay of FIG. 4 according to a preferred embodiment of the present invention.
6 is a circuit diagram showing the phase voltage converter of FIG. 4 according to an embodiment of the present invention.
7 is a timing chart for explaining the operation of the phase-to-voltage converter of FIG. 6 according to the embodiment of the present invention.
FIG. 8 is a block diagram of the frequency multiplier of FIG. 1 according to a preferred embodiment of the present invention.
9 is a circuit diagram and timing diagram showing the edge detector of FIG. 8 according to an embodiment of the present invention.
10 is a circuit diagram showing a pulse signal synthesizing unit according to an embodiment of the present invention.
11 is a timing chart for explaining the operation of the pulse signal combining unit of FIG. 10 according to the embodiment of the present invention.
12 is a block diagram illustrating another clock generator according to a preferred embodiment of the present invention.
13 is a block diagram illustrating the voltage controlled delay stage of FIG. 12 according to a preferred embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

1 is a block diagram illustrating a clock generator according to a preferred embodiment of the present invention.

Referring to FIG. 1, the clock generator of the present invention includes a phase detector 100, a charge pump 110, a loop filter 120, a voltage control delay stage 200, and a frequency multiplier 300.

The phase detector 100 compares the input two signals Fin and Fdl and simultaneously detects the phase and frequency difference of the two signals Fin and Fdl. For example, the periodic input signal Fin and the delayed output signal Fdl, which is the output signal of the voltage-controlled delay stage 200, are compared in the phase detector 100. The phase detector 100 outputs the up-signal UP and the down-signal DN through a comparison operation of two input signals Fin and Fdl. The up-signal UP and down-signal DN have a pulse width corresponding to the phase difference of the two input signals. In addition, the up-signal UP and down-signal DN can be selectively activated according to comparison of the phases of the two input signals.

For example, when the phase of the input signal Fin is faster than the delay output signal Fdl, the up-signal UP having a pulse width corresponding to the phase difference is activated. Further, when the phase of the input signal Fin is slower than the delay output signal Fdl, the down-signal DN having a pulse width corresponding to the phase difference is activated.

In addition, the operation of the phase detector may activate the up-signal UP when the phase of the input signal Fin is slower than the delayed output signal Fdl.

The up-signal UP and the down-signal DN, which are two output signals of the phase detector 100, are input to the charge pump 110. The charge pump 110 forms charge / discharge current Ich in accordance with the up-signal UP or down-signal DN. The charge / discharge current Ich formed charges or discharges the loop filter 120.

For example, the charge pump 110 charges the loop filter 120 by the activated up-signal UP, and the voltage of the delay control signal Vdl, which is the output signal of the loop filter 120, is raised by the charging operation. Also, the charge pump 110 discharges the loop filter 120 by the activated down-signal DN, and the level of the delay control signal Vdl, which is the output signal of the loop filter 120, is lowered by the discharging operation.

In addition, charge-discharge operations due to the activation of the up-signal UP and the down-signal DN may occur differently. That is, in the activation period of the up-signal UP, the charge pump 110 can perform the charging operation for the loop filter 120, and in the activation period of the down-signal DN, As shown in FIG.

The voltage controlled delay stage 200 generates a phase delay, delays the phase of the input signal Fin, and generates a delayed delayed output signal Fdl.

The voltage control delay stage 200 receives the delay control signal Vdl and the phase change signal Vpc and performs a delay operation according to the received delay control signal Vdl and the phase change signal Vpc. The voltage controlled delay stage 200 includes a delay unit 210 and a phase change voltage conversion unit 220.

The delay unit 210 receives the delay control signal Vdl, which is the output of the loop filter 120, and the phase change signal Vpc, which is the output of the phase change voltage conversion unit 220, as a control signal. The delay unit 210 includes a plurality of delay units 211, 212, and 213 and output signals of the delay units of the previous stages are input to the delay units 211, 212, and 213, respectively. In particular, the delay control signal Vdl, which is the output of the loop filter 120, is commonly applied to each of the delay units 211, 212, and 213 to determine the actual delay time of the delay unit 210.

The phase change voltage converting unit 220 detects a phase change that varies due to noise or an external factor after a phase lock is performed and forms a phase change signal Vpc proportional to the phase change. That is, when the fluctuating phase change increases, the level of the phase change signal Vpc increases, and when the phase change decreases, the level of the phase change signal Vpc decreases. The generated phase change signal Vpc is applied to the delay unit 210 to compensate for the phase change of the delay unit 210. To this end, the phase change voltage converting unit 220 has a plurality of phase voltage converters 221, 222, and 223. It is preferable that the phase voltage converters 221, 222, and 223 are disposed in a plurality corresponding to the delay units 211, 212, and 213, respectively. The phase voltage converters 221, 222, and 223 receive the inputs and outputs of the delay units of the current stage and generate respective phase change signals Vpc through charging and discharging operations in accordance with the phase change.

The frequency multiplier 300 receives an input signal or an output signal of each of the delay units 211, 212, and 213 constituting the delay unit 210, detects an edge of the received signal to generate a pulse signal, Performs a frequency multiplication operation through synthesis to form it as an output signal Fout.

2 is a circuit diagram showing the phase detector of FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 2, the phase detector includes a first flip-flop 101, a second flip-flop 102, and a reset unit 103.

The first flip-flop 101 and the second flip-flop 102 are composed of a D-type flip-flop. A high-level signal is input to the D terminal of the first flip-flop 101 and the second flip-flop 102, and an input signal Fin having a predetermined frequency and a delay The output signal Fdl is input. The delay output signal Fdl is a signal delayed by a predetermined timing as compared with the input signal Fin. For example, an input signal Fin is applied to the CP terminal of the first flip-flop 101 and a delayed output signal Fdl is input to the CP terminal of the second flip-flop 102. [

Since the first flip-flop 101 and the second flip-flop 102 have a D-type configuration, the input of the D terminal is reflected to the output terminal Q only when the input of the CP terminal is a logical "1 ".

The outputs of the first flip-flop 101 and the second flip-flop 102 are input to the reset unit 103. [ In FIG. 2, the reset unit 103 is described as an AND gate for performing a logical product operation. However, the reset unit 103 may be configured by various logic combinations such as a NOR gate. That is, the aspect of the logic combination of the reset unit 103 may be variously changed according to the designer's intention.

If the phase of the input signal Fin is faster than the phase of the delayed output signal Fd1, the first flip-flop 101 outputs logic "1" at a high level in a period in which the input signal Fin is at a high level and the delayed output signal Fdl is at a low level, And the second flip-flop 102 outputs a low level logic "0 ". In the section where the input signal Fin and the delay output signal Fdl are in common high level, the outputs of the two flip-flops 101 and 102 output a high logic level "1 ", and the reset unit 103 outputs two The flip-flops 101 and 102 are reset and a logic "0" is output to the Q terminal.

Accordingly, in the configuration of FIG. 2, when the phase of the input signal Fin is higher than the phase of the delay output signal Fd1, the high level corresponding to the phase difference is output as the up-signal UP. Further, when the phase of the input signal Fin is slower than the phase of the delayed output signal Fd1, the down-signal DN is activated to the high level and the up-signal UP is switched to the low level.

Also, according to the embodiment, the reset unit 103 may be configured as a NOR gate. Thus, the aspect of the up-signal UP and the aspect of the down-signal DN may vary depending on the type of gate constituting the reset section 103. [

3 is a circuit diagram illustrating the operation of the charge pump and the loop filter of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 3, the charge pump 110 has two current sources Ip, In and two switches S1, S2. The loop filter 120 also has a filter capacitor Clf.

The source current source Ip is connected between the positive power supply voltage VDD and the first switch S1, and the first switch S1 is connected between the source current source Ip and the delay control signal Vdl. Further, the sink current source In is connected between the ground and the second switch S2, and the second switch S2 is connected between the delay control signal Vdl and the sink current source In. The first switch S1 performs the on / off operation by the up-signal UP, and the second switch S2 performs the on / off operation according to the down-signal DN.

When the up-signal UP is activated, the first switch S1 is turned on. Therefore, a charging operation from the source current source Ip to the filter capacitor Clf of the loop filter 120 is performed, and the level of the delay control signal Vdl increases. Further, when the down-signal DN is activated, the second switch S2 is turned on, and the discharging operation to the filter capacitor Clf of the loop filter 120 is performed from the sink current source In. Thus, the level of the delay control signal Vdl decreases.

If the phase of the input signal Fin inputted to the phase detector is in phase with the phase of the delayed output signal Fdl, the reset unit of the phase detector can activate the reset signal. Therefore, the up-signal UP and the down-signal DN are simultaneously switched to the high level or the low level. When the up-signal UP and the down-signal DN have a common high level, the first switch S1 and the second switch S2 are turned on, and a current path is formed from the source current source Ip to the sink current source In. Assuming that the amount of current supplied by the source current source Ip and the amount of current generated by the sink current source In are the same, no charge / discharge operation occurs in the filter capacitor Clf. Therefore, the level of the delay control signal Vdl does not change. Further, when the up-signal UP and the down-signal DN have a common low level by the reset operation, the first switch S1 and the second switch S2 can be commonly turned off. So that the delay control signal Vdl can be fixed to a constant level.

That is, when the input signal Fin input to the phase detector and the delay output signal Fdl are in a locked-in stage within a certain range, the level of the delay control signal Vdl can be kept constant without changing .

4 is a block diagram illustrating the voltage controlled delay stage of FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 4, the voltage controlled delay stage has a delay unit 210 and a phase change voltage conversion unit 220.

The delay unit 210 includes a plurality of delay units 211, 212, and 213 connected in series with each other. A delay control signal Vdl and a phase change signal Vpc, which is an output of the phase change voltage converter 220, are applied to the delay units 211, 212, and 213, respectively. The delay time of each of the delay units 211, 212, and 213 is determined by the applied delay control signal Vdl and the phase change signal Vpc. That is, the delay control signal Vdl and the phase change signal Vpc are used as a control signal for determining the delay operation of the delay units 211, 212, and 213.

The phase change voltage conversion unit 220 has a plurality of phase voltage converters 221, 222, and 223 connected in series with each other. Each of the phase voltage converters 221, 222 and 223 is arranged corresponding to the delay units 211, 212 and 213. For example, one phase-to-voltage converter is provided in one delay. Each of the phase voltage converters is supplied with the input signal and the output signal of the corresponding delay unit. Also, the delay control signal Vdl, which is the output signal of the phase voltage converter, is used to control the delay time of the delay.

5 is a circuit diagram illustrating the delay of FIG. 4 according to a preferred embodiment of the present invention.

5, the delay unit has a first voltage control resistance unit 215, a second voltage control resistance unit 216, and a delay element 217. [

The first voltage control resistor unit 215 and the second voltage control resistor unit 216 have the same circuit configuration. The delay control signal Vdl is applied to the first voltage control resistor 215 and the phase change signal Vpc is applied to the second voltage control resistor 216. Further, the delay element 217 receives the output of the delay element of the previous stage or the input signal Fin in the form of differential signals IN and / IN.

The delay time of the delay element 217 can be determined by the delay control signal Vdl or the phase change signal Vpc applied to each of the voltage control resistors 215 and 216. [ The determination of the delay time can be achieved through adjustment of the amount of bias current flowing through the delay element 217. [

The first voltage control resistor 215 has NMOS transistors QN1, QN2 and QN3 and a PMOS transistor QP1. Transistor QP1 is diode connected, and transistor QN3 is diode connected. A delay control signal Vdl is applied to the gate terminals of the transistors QN1 and QN2. When the delay control signal Vdl has a low level, the amount of current flowing through the transistors QN1 and QN2 also has a low value. Therefore, the voltage at the gate terminal of the transistor QP1 has a high level. Further, the bias current flowing through the transfer gates QX1 and QX2 of the delay element 217 by the voltage of the gate terminal of the transistor QP1 having a high level has a low value, and the time for delaying the input signals IN and / IN increases . Further, when the delay control signal Vdl has a high value, the time delay of the input signals IN and / IN is reduced. The delayed signal is output in the form of differential signals Vm and / Vm, which is used as the input of the delay of the next stage.

This operation is also generated in the operation of the second voltage control resistance section 216 and the delay element 217 as well. That is, when the phase change signal Vpc increases, the delay time of the input signals IN and IN decreases. When the phase change signal Vpc decreases, the delay times of the input signals IN and / IN increase.

6 is a circuit diagram showing the phase voltage converter of FIG. 4 according to an embodiment of the present invention.

Referring to FIG. 6, the phase voltage converter has a voltage conversion unit 225 and a control signal generation unit 226.

7 is a timing chart for explaining the operation of the phase voltage converter of FIG. 6 according to the embodiment of the present invention.

Referring to FIGS. 6 and 7, the voltage converting unit 225 generates a phase change signal Vpc through a charge / discharge operation. In addition, the control signal generator 226 generates switching control signals SG1 and SG2 and a gate control signal SC1 through a logical operation on the input signals Vn-1 and Vn of the phase voltage converter.

First, it is assumed that the phase of the input signal Vn-1 is faster than the phase of Vn. For example, assume that the input signal Vn-1 is the output of the first delay unit 211 in FIG. 4, and the other input signal Vn is the output of the second delay unit 212. Accordingly, the phase voltage converter shown in FIG. 6 corresponds to the second phase voltage converter 222 in FIG. Thus, the phase of the signal Vn-1 is set faster than the signal Vn.

The signals Vn-1 and Vn are input to the first end gate (AND gate) 2261 of the control signal generation section 226. [ The first end gate 2261 generates a gate control signal SC1 through an AND operation. The gate control signal SC1 becomes a high level only when the signals Vn-1 and Vn are at a high level. Also, when any one of the two input signals is at the low level, the gate control signal SC1 becomes low level.

The gate control signal SC1 is input to one end of the second end gate 2262 and is input to the other end of the second end gate 2262 after being delayed for a predetermined time and then inverted. The signal Vx input to the other end of the second end gate 2262 is a signal delayed by the first delay circuit 2264 for a predetermined time. For example, it is delayed for a predetermined time by the delay caused by the configuration of the buffer and the inverter. Therefore, the degree of delay of the signal Vx applied to the second end gate 2262 can be variously changed depending on the configuration of the buffer or the inverter. The second end gate 2262 forms the first switching control signal SG1. If the first switching control signal SG1 ignores the delay time in the second end gate 2262, the gate control signal SC1 and its delayed and inverted signal Vx are activated to a high level in a high level period. As a result, the first switching control signal SG1, which is the output of the second end gate 2262, outputs a high level during the delayed period of the gate control signal SC1.

The input signal Vx is applied to the third end gate 2263. First, the signal Vx is inverted by the inverter and is delayed for a predetermined time to form the signal Vy, and is applied to one end of the third end gate 2263. [ The signal Vy is delayed and inverted for a predetermined time by the second delay circuit 2265 composed of a buffer, an inverter, and the like, and is input to the other end of the third end gate 2263. Thus, the third end gate 2263 forms a second switching signal SG2 through an AND operation on the signal Vy and its delayed and inverted signal.

The gate control signal SC1 and the switching control signals SG1 and SG2 formed through the above process are applied to the voltage converter 225. [

The gate control signal SC1 is input to the gate terminal of the PMOS transistor QP2 of the voltage conversion unit 225 and the second switching control signal SG2 is input to the gate terminal of the NMOS transistor QN4. The transistor QP2 is turned on in a period in which the gate control signal SC1 is at a low level and the transistor QN3 is turned off by the second switching control signal SG2. Thus, the current flows through the transistor QP2 turned on to the capacitor Cx and the voltage of the capacitor Cx rises.

The first switching control signal SG1 has a phase earlier than the second switching control signal SG2. Therefore, after the charging operation of the capacitor Cx, the charging switch SCH is turned on by the second switching control signal SG2. The charge voltage of the capacitor Cx is transferred to the capacitor Cy through the on-state charge switch SCH. That is, the charge charged in the capacitor Cx is transferred to the capacitor Cy through the turned-on charging switch SCH, and the phase change signal Vpc, which is the voltage of the capacitor Cy, is raised.

In addition, in the period in which the first switching control signal SG1 is at the low level and the second switching control signal SG2 is at the high level, the transistor QN4 is turned on and the charge charged in the capacitor Cx is discharged to the ground through the transistor QN4.

In the above-described operation of the phase voltage converter, the phase difference between the input signal and the output signal of the delay element causes a change in the level of the phase change signal Vpc. That is, when the phases of the input signal and the output signal of the delay device are changed and the phase difference is decreased in the timing diagram of FIG. 7, the interval in which the gate control signal SC1 is low level decreases. This means a decrease in the time to be charged in the capacitor Cx and causes a decrease in the phase change signal Vpc. In addition, when the phase difference between the input signal and the output signal of the delay device increases, the interval in which the gate control signal SC1 is low level increases. Thus, the time to charge the capacitor Cx increases and the phase change signal Vpc increases.

When the phase change signal Vpc increases, the delay of FIG. 5 reduces the delay time of the signal input as the differential signal. Thus, the delay time between the input signal and the output signal increased through the delay is reduced by the increase of the phase change signal Vpc, and is set to have a constant delay time by the phase change signal Vpc.

Further, when the phase change signal Vpc decreases, the delay of FIG. 5 increases the delay time of the input signal. Thus, the delay time between the input signal and the output signal reduced through the delay is increased by the decrease of the phase change signal Vpc, and is set to have a constant delay time by the phase change signal Vpc.

That is, each of the delay units determines the delay time according to the level of the delay control signal Vdl or the level of the phase change signal Vpc.

That is, the phase change voltage converter detects a phase change according to an unwanted jitter or a noise component generated in a delay unit of a delay unit, converts the phase change into a voltage, and allows the delay unit to operate with a normal delay time.

FIG. 8 is a block diagram of the frequency multiplier of FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 8, the frequency multiplier has an edge detector 310 and a pulse signal combiner 320. The edge detector 310 has a plurality of edge detectors 311, 312 and 313 and each of the edge detectors 311, 312 and 313 detects the edge of the input signal or output signal of the delay, Into signals P1, P2, ..., Pn.

The pulse signal synthesizer 320 generates an output signal Fout corresponding to the parallax of the pulse signal through on / off operations according to the pulse signals P1, P2, ..., Pn.

9 is a circuit diagram and timing diagram showing the edge detector of FIG. 8 according to an embodiment of the present invention.

Referring to FIG. 9, the signal Vm transitions to a high level and is applied to the end gate. Further, the signal Vm is inverted by the inverter, is delayed for a predetermined time in accordance with the inverting operation of the inverter, and is input to the end gate. Thus, the end gate outputs a high-level pulse Px in a period corresponding to the delay time of the inverter.

10 is a circuit diagram showing a pulse signal synthesizing unit according to an embodiment of the present invention.

11 is a timing chart for explaining the operation of the pulse signal combining unit of FIG. 10 according to the embodiment of the present invention.

Referring to FIGS. 10 and 11, the pulse signal synthesizer has a PMOS loading transistor MP1 and a plurality of synthesis transistors MN1, ..., MNn.

The gate terminal of the loading transistor MP1 is grounded. Thus, the loading transistor MP1 remains turned on.

Also, each of the synthesis transistors MN1, ..., MNn is connected in parallel with each other. The pulse signals P1, ..., Pn, which are output signals of the edge detector 310, are applied to the gate terminals of the composite transistor MP1.

First, in a period in which the pulse P1, which is the output signal of the first edge detector 311, is at a high level, the first synthesis transistor MN1 is turned on. The output stage forms a low level regardless of the operation of the other synthesis transistors according to the turn-on of the first synthesis transistor MN1.

In addition, in a period in which the output of the first edge detector 311 is at the low level and the output of the second edge detector 312 is not transitioned to the high level, all the synthesis transistors are kept in the off state. Thus, the output transitions to a high level.

Thereafter, when the output of the second edge detector 312 transitions to the high level, the second loading transistor MN2 is turned on, and the output transitions to the low level regardless of the state of the other loading transistors.

As a result, the pulse signal synthesizing unit is composed of the respective synthesis transistors MN1, MN2,. The output signals P1, P2, ..., Pn of the edge detectors 311, 312, and 313 input to the gate terminal of the MNn are transited to the low level in the high level interval and the output of the edge detector is low level Transition to a high level. Whereby the multiplication operation of the frequency according to the output signal of the edge detector is performed.

12 is a block diagram illustrating another clock generator according to a preferred embodiment of the present invention.

12, the configurations of the phase detector 100, the charge pump 110, the loop filter 120, and the frequency multiplier 300 are the same as those described in FIG. 1, and have the same configuration and operation.

12, the voltage control delay stage 200 further includes an average value detector 230. [ The mean value detection unit 230 has average value detectors 231, 232, and 233 arranged corresponding to the delay units 211, 212, and 213 or the phase voltage converters 221, 222, and 223, respectively.

The outputs of the corresponding phase voltage converters and the outputs of the adjacent phase voltage converters are input to the respective average value detectors 231, 232, and 233, and are calculated by the average value to be formed into the phase change signal Vpc.

For example, the output of the first phase voltage converter 221 and the output of the second phase voltage converter 222 are input to the second mean value detector 232, And is applied as the second phase change signal Vpc2.

The configuration and operation of the delay and phase voltage converter are the same as those described in FIGS. 5 to 7.

13 is a block diagram illustrating the voltage controlled delay stage of FIG. 12 according to a preferred embodiment of the present invention.

Referring to FIG. 13, the voltage controlled delay stage has a delay unit 210, a phase change voltage converting unit 220, and an average value detecting unit 230.

The delay unit 210 includes a plurality of delay units 211, 212, and 213 connected in series with each other. A delay control signal Vdl and a phase change signal Vpc, which is an output of the phase change voltage converter 220, are applied to the delay units 211, 212, and 213, respectively. The delay time of each of the delay units 211, 212, and 213 is determined by the applied delay control signal Vdl and the phase change signal Vpc. That is, the delay control signal Vdl and the phase change signal Vpc are used as a control signal for determining the delay operation of the delay units 211, 212, and 213.

The phase change voltage conversion unit 220 has a plurality of phase voltage converters 221, 222, and 223 connected in series with each other. Each of the phase voltage converters 221, 222 and 223 is arranged corresponding to the delay units 211, 212 and 213. For example, one phase-to-voltage converter is provided in one delay. Input signals and output signals of the corresponding delay units 211, 212, and 213 are input to the phase voltage converters 221, 222, and 223, respectively. The output signal of the phase voltage converter is formed into a phase change signal Vpc through an averaging operation with the output signal of the adjacent phase voltage converter in the average value detector 230. [

The mean value detector 230 receives the output signals from the adjacent phase voltage converters and performs an average operation on the output signals of the at least two phase voltage converters to form the phase change signal Vpc. To this end, the average value detector 230 has a plurality of average value detectors 231, 232, and 233 corresponding to the phase voltage converters 221, 222, and 223, respectively. Each of the mean value detectors 231, 232, and 233 forms a phase change signal Vpc according to an average operation on output signals of adjacent phase voltage converters. The formed phase change signal Vpc adjusts the delay time of each of the delay units 211, 212, and 213 as described above.

In the above-described present invention, the clock generator has a voltage-controlled delay stage and corrects a phase change due to jitter or the like generated in the delay unit in the phase change voltage converter. This compensates for the phase change due to jitter or noise during operation of the clock generator and reduces the jitter of the output signal. In addition, it is possible to smoothly remove the noise or jitter generated due to the motion of the input signal or the internal circuit, thereby performing a smooth frequency multiplication operation.

100: phase detector 110: charge pump
120: Loop filter 200: Voltage control delay stage
210: Delay unit 220: Phase change voltage converter
230: average value detector 300: frequency multiplier
310: edge detection unit 320: pulse signal synthesis unit

Claims (8)

A phase detector for detecting the phase difference by comparing the input signal and the delayed output signal to form an up-signal or a down-signal;
A charge pump for forming a charge / discharge current according to the up-signal or the down-signal of the phase detector;
A loop filter for forming a delay control signal according to charge / discharge current of the charge pump;
A voltage control delay stage for generating the delay output signal through a delay operation on the input signal in accordance with the delay control signal and correcting a phase change according to a jitter or a noise component generated in a delay operation through a phase change signal; And
And a frequency doubler for receiving signals delayed for each stage of the voltage controlled delay stage to form a pulse signal and combining the signals to form an output signal,
The voltage-
A delay unit having a plurality of delay units for receiving the delay control signal and the phase change signal and performing a delay operation on the input signal; And
And a phase voltage converting unit for receiving the input signal and the output signal of the delay unit and generating the phase change signal proportional to the phase difference between the input signal and the output signal of the delay unit. delete The phase-to-voltage converter of claim 1, wherein the phase-to-voltage converter has a plurality of phase-to-voltage converters, each of the phase-to-voltage converters receives an input signal and an output signal of the corresponding delay,
The level of the phase change signal is increased when the phase difference between the input signal and the output signal of the delay increases,
And decreases the level of the phase change signal when the phase difference between the input signal and the output signal of the delay device decreases. 4. The apparatus of claim 3, wherein the phase voltage converter comprises:
A voltage conversion unit for generating the phase change signal through charge / discharge operation; And
And a control signal generator for generating a first switching control signal, a second switching control signal, and a gate control signal through logic operation on the input signal and the output signal of the delay unit to control the charging / discharging operation of the voltage converting unit Clock generator. 5. The apparatus of claim 4, wherein the control signal generator comprises:
A first end gate for performing an AND operation on an input signal and an output signal of the delay unit to generate the gate control signal;
A second end gate receiving the gate control signal, performing a logical AND operation on the gate control signal inverted through the first delay circuit and a delayed signal to generate the first switching control signal; And
And a third end gate for performing an AND operation on a signal obtained by inverting the signal passed through the first delay circuit and a signal delayed and inverted through the second delay circuit to generate the second switching control signal Features a clock generator. 6. The apparatus of claim 5,
And a charging operation is performed when any one of the input signal and the output signal of the delay circuit is in a low level state, thereby raising the level of the phase change signal. The apparatus of claim 1, wherein the frequency doubler comprises:
An edge detector for detecting an edge of an input signal or an output signal of each of the delay units and converting the edge of the input signal or the output signal into a pulse signal; And
And a pulse signal synthesizer for receiving the pulse signal and generating an output signal corresponding to a parallax of the pulse signal according to an on / off operation. A phase detector for detecting the phase difference by comparing the input signal and the delayed output signal to form an up-signal or a down-signal;
A charge pump for forming a charge / discharge current according to the up-signal or the down-signal of the phase detector;
A loop filter for forming a delay control signal according to charge / discharge current of the charge pump;
A voltage control delay stage for generating the delay output signal through a delay operation on the input signal in accordance with the delay control signal and correcting a phase change according to a jitter or a noise component generated in a delay operation through a phase change signal; And
And a frequency doubler for receiving signals delayed for each stage of the voltage controlled delay stage to form a pulse signal and combining the signals to form an output signal,
The voltage-
A delay unit having a plurality of delay units for receiving the delay control signal and the phase change signal and performing a delay operation on the input signal;
A phase voltage converter having a plurality of phase voltage converters for receiving an input signal and an output signal of the delay unit and generating a signal proportional to the phase difference; And
And an average value detector having a plurality of average value detectors for performing an average operation on outputs of the phase voltage converters adjacent to each other to generate the phase change signal.

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