CN102394637A - Anti-differential power attack ternary counter based on sense amplification logic - Google Patents

Anti-differential power attack ternary counter based on sense amplification logic Download PDF

Info

Publication number
CN102394637A
CN102394637A CN2011103058180A CN201110305818A CN102394637A CN 102394637 A CN102394637 A CN 102394637A CN 2011103058180 A CN2011103058180 A CN 2011103058180A CN 201110305818 A CN201110305818 A CN 201110305818A CN 102394637 A CN102394637 A CN 102394637A
Authority
CN
China
Prior art keywords
gate
pmos transistor
nmos transistor
drain
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103058180A
Other languages
Chinese (zh)
Other versions
CN102394637B (en
Inventor
汪鹏君
张跃军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Maen Science & Technology Co ltd
Original Assignee
Ningbo University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo University filed Critical Ningbo University
Priority to CN201110305818.0A priority Critical patent/CN102394637B/en
Publication of CN102394637A publication Critical patent/CN102394637A/en
Application granted granted Critical
Publication of CN102394637B publication Critical patent/CN102394637B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Logic Circuits (AREA)

Abstract

本发明公开了一种基于灵敏放大逻辑的抗差分能量攻击的三值计数器,特点是它包括一个二值逻辑转换电路和一个灵敏放大逻辑转换电路,灵敏放大逻辑转换电路设置有电流补偿电路,所述的二值逻辑转换电路由第一D触发器、第二D触发器、与非门和异或非门组成,灵敏放大逻辑转换电路由第一PMOS管、第二PMOS管、第三PMOS管、第一NMOS管、第二NMOS管、第三NMOS管和第四NMOS管组成,灵敏放大逻辑转换电路的第一信号输出端和第二信号输出端并接于电流补偿电路,优点在于三值计数器的电路具有功耗恒定的特性,不仅具有良好的抗差分能量攻击效果,而且电路间接线连接的复杂度和成本均大大降低,电路的可靠性提高。

The invention discloses a three-value counter based on sensitive amplification logic and resisting differential energy attack, which is characterized in that it includes a binary logic conversion circuit and a sensitive amplification logic conversion circuit, and the sensitive amplification logic conversion circuit is provided with a current compensation circuit. The binary logic conversion circuit described above is composed of a first D flip-flop, a second D flip-flop, a NAND gate and an XNOR gate, and the sensitive amplification logic conversion circuit is composed of a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor. , the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube. The first signal output terminal and the second signal output terminal of the sensitive amplification logic conversion circuit are connected to the current compensation circuit in parallel. The advantage is that the three-value The circuit of the counter has the characteristic of constant power consumption, not only has a good anti-differential energy attack effect, but also greatly reduces the complexity and cost of wiring connections between circuits, and improves the reliability of the circuit.

Description

Amplify three value counters of the resisting differential energy attack of logic based on sensitivity
Technical field
The present invention relates to a kind of three value counters, especially relate to a kind of three value counters that amplify the resisting differential energy attack of logic based on sensitivity.
Background technology
Since the Kocher of U.S. cryptology institute in 1998 proposes the notion of lie attack [1],, in every field, caused widely and paid close attention to as a hot research direction.Conventional cipher is attacked and is used mathematical analysis method to disclose the weakness of AES.This just requires the assailant must quite high attainments arranged aspect cryptanalysis and the AES.Lie is attacked and only is to use information attack encryption chips such as some marginal information, output when for example power consumption, time of implementation, fault and input behavior, radiation, electric power spike situation, and it does not require that the assailant is proficient in cryptanalysis and AES.This just causes very big threat to chip safety.The lie attack method comprise differential power attack (Differential Power Analysis, DPA) [2], mistake attack (Fault Attacks, FA) [3]Attack with electromagnetic wave (Electromagnetic Attacks, EMA) [4]Or the like.Wherein, DPA attack be a kind of efficiently, lie attack method cheaply, the safety to crypto chip constitutes significant threat.The basic principle that DPA attacks is: when chip was being carried out different instructions and carried out various computing, corresponding power consumption is respective change also.Through using special electronic gauge and mathematical statistics technology, detect and analyze these and change, thereby obtain the specific key message in the chip.This is the method that a kind of change of power consumption of utilizing instruction is analyzed cryptographic algorithm and password [5]In the existing literature about the circuit structure of resisting differential energy attack; Amplify logic SABL (Sense Amplifier Based Logic) circuit, fluctuation attitude differential logic WDDL (Wave Dynamic Differential Logic) circuit etc. such as sensitivity, but the contained information density of its power hungry of these circuit and hardware circuit reduces by 50%.And MULTI-VALUED LOGIC CIRCUIT can not only increase the ability that single line carries information, improves the information density of digital circuit, and can reduce the VLSI pin count, reduces wiring connects between circuit complexity and cost, improves the reliability of circuit.Therefore, design many-valued anti-DPA attack circuit unit and become the new research direction of scholar.
Summary of the invention
Technical problem to be solved by this invention provides and a kind ofly can reduce complexity and the cost that wiring between circuit connects, improve circuit reliability amplify three value counters of the resisting differential energy attack of logic based on sensitivity.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of three value counters that amplify the resisting differential energy attack of logic based on sensitivity; It comprises a two-valued function change-over circuit and the sensitive logical transition circuit that amplifies; The described sensitive logical transition circuit that amplifies is provided with current compensation circuit; Described two-valued function change-over circuit is made up of first d type flip flop, second d type flip flop, NAND gate and biconditional gate; The first input end of the first input end of described first d type flip flop and described second d type flip flop is connected to clock signal input terminal; The positive output end of described first d type flip flop is connected with two inputs of described NAND gate respectively with the positive output end of described second d type flip flop; The reversed-phase output of described first d type flip flop is connected with two inputs of described biconditional gate respectively with the reversed-phase output of described second d type flip flop; Second input of described first d type flip flop is connected with the output of described NAND gate; Second input of described second d type flip flop is connected with the positive output end of described first d type flip flop; Described sensitive amplify the logical transition circuit by a PMOS manage, the 2nd PMOS pipe, the 3rd PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS manage and form; The source electrode of described PMOS pipe connects power supply; The source electrode of the source electrode of the drain electrode of described PMOS pipe and described the 2nd PMOS pipe and described the 3rd PMOS pipe also connects, and the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, and the drain electrode of described the 3rd PMOS pipe is connected with the drain electrode of described the 3rd NMOS pipe; The drain electrode of the source electrode of the source electrode of described the 2nd NMOS pipe and described the 3rd NMOS pipe and described NMOS pipe also connects; The source ground of described NMOS pipe, described the 4th NMOS pipe are connected across in the drain electrode of drain electrode and described the 3rd NMOS pipe of described the 2nd NMOS pipe, and the grid of the grid of described PMOS pipe, described NMOS pipe and the grid of described the 4th NMOS pipe are connected to the inversion clock signal input part; The drain electrode of the grid of described the 3rd PMOS pipe and described the 2nd PMOS pipe is connected to first signal output part; The drain electrode of the grid of described the 2nd PMOS pipe and described the 3rd PMOS pipe is connected to the secondary signal output, and the grid of described NMOS pipe is connected with clock signal input terminal, and the grid of described the 2nd NMOS pipe is connected with the output of described NAND gate; The grid of described the 3rd NMOS pipe is connected with the output of described biconditional gate, and described first signal output part and described secondary signal output are connected to described current compensation circuit.
Described current compensation circuit by the 4th PMOS manage, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe form; Described first signal output part and described secondary signal output are connected to the drain and gate of described the 4th PMOS pipe; Described the 4th PMOS pipe source electrode is connected with the drain electrode of described the 5th PMOS pipe; The source electrode of the source electrode of described the 5th PMOS pipe and described the 6th PMOS pipe is connected to power supply; The drain electrode of the grid of described the 6th PMOS pipe and drain electrode and described the 5th NMOS pipe is connected to the grid of described the 5th PMOS pipe, the grid and the source ground of described the 5th NMOS pipe.
Compared with prior art; The invention has the advantages that and utilize binary-coding and the sensitive logic pre-charging stage capacitive coupling characteristic of amplifying; Designed a kind of three value counters, this scheme only need use a sensitive two-valued function change-over circuit that amplifies logical transition circuit and corresponding conventional two-value components and parts formation just can realize the function of three value counters, and through a current compensation circuit is set; Make the circuit of three value counters of the present invention have the constant characteristic of power consumption; Not only have good resisting differential energy attack effect, and the complexity that wiring connects between circuit and all reductions greatly of cost, the reliability of raising circuit; Also can the cascade of multidigit counter unit be obtained three value counters of position arbitrarily simultaneously.
Description of drawings
Fig. 1 is the structural representation and the circuit symbol sketch map of the present invention's three value counters;
Fig. 2 is the sensitive structural representation that amplifies the logical transition circuit of the present invention;
Fig. 3 is the structural representation of two-valued function change-over circuit of the present invention;
Fig. 4 is the structural representation of current compensation circuit of the present invention;
Fig. 5 is the structural representation of three three value counters being made up of three value counters of the present invention;
Fig. 6 is the computer simulation waveform sketch map of three three value counters;
Fig. 7 is the sketch map of the current waveform of three three value counters in a count cycle;
Fig. 8 is the power consumption waveform sketch map of three three value counters.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
Like Fig. 1~shown in Figure 4; A kind of three value counters that amplify the resisting differential energy attack of logic based on sensitivity; It comprises a two-valued function change-over circuit 1 and the sensitive logical transition circuit 2 that amplifies; The sensitive logical transition circuit 2 that amplifies is provided with current compensation circuit 3; Two-valued function change-over circuit 1 is made up of the first d type flip flop D1, the second d type flip flop D2, NAND gate T1 and biconditional gate T2; The first input end 2D of the first input end 1D of the first d type flip flop D1 and the second d type flip flop D2 is connected to clock signal input terminal clk; The positive output end of the first d type flip flop D1 is connected with two inputs of NAND gate T1 respectively with the positive output end of the second d type flip flop D2; The reversed-phase output of the first d type flip flop D1 is connected with two inputs of biconditional gate T2 respectively with the reversed-phase output of the second d type flip flop D2, and the second input 1C of the first d type flip flop D1 is connected with the output of NAND gate T1, and the second input 2C of the second d type flip flop D2 is connected with the positive output end of the first d type flip flop D1; The sensitive logical transition circuit 2 that amplifies is made up of PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the 4th NMOS pipe N4; The source electrode of the one PMOS pipe P1 connects power supply, and the source electrode of the drain electrode of PMOS pipe P1 and the 2nd PMOS pipe P2 and the source electrode of the 3rd PMOS pipe P3 also connect, and the drain electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 2nd NMOS pipe N2; The drain electrode of the 3rd PMOS pipe P3 is connected with the drain electrode of the 3rd NMOS pipe N3; The drain electrode of source electrode that the source electrode of the 2nd NMOS pipe N2 and the 3rd NMOS manage N3 and NMOS pipe N1 also connects, and drain electrode and the 3rd NMOS that the source ground of NMOS pipe N1, the 4th NMOS pipe N4 are connected across the 2nd NMOS pipe N2 manage in the drain electrode of N3; The grid of the grid of the grid of the one PMOS pipe P1, NMOS pipe N1 and the 4th NMOS pipe N4 is connected to inversion clock signal input part clk; The drain electrode of the grid of the 3rd PMOS pipe P3 and the 2nd PMOS pipe P2 is connected to the first signal output part Vout, and the drain electrode of the grid of the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 is connected to secondary signal output CP, and the grid of NMOS pipe N1 is connected with clock signal input terminal clk; The grid of the 2nd NMOS pipe N2 is connected with the output of NAND gate T1; The grid of the 3rd NMOS pipe N3 is connected with the output of biconditional gate T2, and current compensation circuit 3 is made up of the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6 and the 5th NMOS pipe N5, and the 4th PMOS pipe P4 source electrode is connected with the drain electrode of the 5th PMOS pipe P5; The source electrode of the source electrode of the 5th PMOS pipe P5 and the 6th PMOS pipe P6 is connected to power supply; The drain electrode of the grid of the 6th PMOS pipe P6 and drain electrode and the 5th NMOS pipe N5 is connected to the grid of the 5th PMOS pipe P5, grid and the source ground of the 5th NMOS pipe N5, and the first signal output part Vout and secondary signal output CP are connected to the drain and gate of the 4th PMOS pipe P4.
Fig. 5 has provided the structural representation of three three value counters that utilize three value counters formation of the present invention.
Under the CANDANCE environment, adopt the 0.13 μ m CMOS technology of TSMC, three three value counters are carried out computer simulation.Fig. 6 has provided the analog waveform of three three value counters.Clk is a clock signal, V Out0, V Out1, V Out2Represent first in counter, second and tertiary output respectively, output logic 0, logical one and logic 2 successively under clock control.Analog result shows that output waveform is more satisfactory, and counter has correct logic functions.
Fig. 7 is the current waveforms of three three value counters in a count cycle, and main electric current occurs on the counting edge, and size of current is basic identical.
Fig. 8 is the power consumption waveform of three three value counters, and in each clock cycle, the power consumption curve is all the same, has the constant characteristic of power consumption.

Claims (2)

1.一种基于灵敏放大逻辑的抗差分能量攻击的三值计数器,其特征在于它包括一个二值逻辑转换电路和一个灵敏放大逻辑转换电路,所述的灵敏放大逻辑转换电路设置有电流补偿电路,所述的二值逻辑转换电路由第一D触发器、第二D触发器、与非门和异或非门组成,所述的第一D触发器的第一输入端与所述的第二D触发器的第一输入端并接于时钟信号输入端,所述的第一D触发器的正相输出端与所述的第二D触发器的正相输出端分别与所述的与非门的两个输入端连接,所述的第一D触发器的反相输出端与所述的第二D触发器的反相输出端分别与所述的异或非门的两个输入端连接,所述的第一D触发器的第二输入端与所述的与非门的输出端连接,所述的第二D触发器的第二输入端与所述的第一D触发器的正相输出端连接,所述的灵敏放大逻辑转换电路由第一PMOS管、第二PMOS管、第三PMOS管、第一NMOS管、第二NMOS管、第三NMOS管和第四NMOS管组成,所述的第一PMOS管的源极接电源,所述的第一PMOS管的漏极与所述的第二PMOS管的源极及所述的第三PMOS管的源极并接,所述的第二PMOS管的漏极与所述的第二NMOS管的漏极连接,所述的第三PMOS管的漏极与所述的第三NMOS管的漏极连接,所述的第二NMOS管的源极及所述的第三NMOS管的源极与所述的第一NMOS管的漏极并接,所述的第一NMOS管的源极接地,所述的第四NMOS管跨接在所述的第二NMOS管的漏极和所述的第三NMOS管的漏极上,所述的第一PMOS管的栅极、所述的第一NMOS管的栅极和所述的第四NMOS管的栅极并接于反相时钟信号输入端,所述的第三PMOS管的栅极与所述的第二PMOS管的漏极并接于第一信号输出端,所述的第二PMOS管的栅极与所述的第三PMOS管的漏极并接于第二信号输出端,所述的第一NMOS管的栅极与时钟信号输入端连接,所述的第二NMOS管的栅极与所述的与非门的输出端连接,所述的第三NMOS管的栅极与所述的异或非门的输出端连接,所述的第一信号输出端和所述的第二信号输出端并接于所述的电流补偿电路。1. A three-valued counter based on a sensitive amplification logic anti-differential energy attack, characterized in that it includes a binary logic conversion circuit and a sensitive amplification logic conversion circuit, and the sensitive amplification logic conversion circuit is provided with a current compensation circuit , the binary logic conversion circuit is composed of a first D flip-flop, a second D flip-flop, a NAND gate and an XNOR gate, the first input terminal of the first D flip-flop is connected to the first input terminal of the first D flip-flop The first input end of the two D flip-flops is connected to the clock signal input end in parallel, and the non-inverting output end of the first D flip-flop and the non-inverting output end of the second D flip-flop are respectively connected to the AND The two input terminals of the NOT gate are connected, and the inverting output terminal of the first D flip-flop and the inverting output terminal of the second D flip-flop are respectively connected with the two input terminals of the exclusive NOR gate connected, the second input end of the first D flip-flop is connected to the output end of the NAND gate, the second input end of the second D flip-flop is connected to the first D flip-flop The positive phase output terminal is connected, and the sensitive amplification logic conversion circuit is composed of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor , the source of the first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected in parallel with the source of the second PMOS transistor and the source of the third PMOS transistor, the The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, and the second The source of the NMOS transistor and the source of the third NMOS transistor are connected in parallel with the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, and the fourth NMOS transistor spans connected to the drain of the second NMOS transistor and the drain of the third NMOS transistor, the gate of the first PMOS transistor, the gate of the first NMOS transistor and the The gate of the fourth NMOS transistor is connected to the input terminal of the inverted clock signal in parallel, the gate of the third PMOS transistor and the drain of the second PMOS transistor are connected in parallel to the first signal output terminal, and the gate of the third PMOS transistor is connected to the first signal output terminal in parallel. The gate of the second PMOS transistor and the drain of the third PMOS transistor are connected to the second signal output end in parallel, the gate of the first NMOS transistor is connected to the clock signal input end, and the second NMOS transistor is connected to the clock signal input end. The gate of the transistor is connected to the output end of the NAND gate, the gate of the third NMOS transistor is connected to the output end of the XNOR gate, and the first signal output end and the The second signal output terminal is connected to the current compensation circuit in parallel. 2.如权利要求1所述的基于SABL逻辑的抗差分能量攻击的三值计数器,其特征在于所述的电流补偿电路由第四PMOS管、第五PMOS管、第六PMOS管和第五NMOS管组成,所述的第一信号输出端和所述的第二信号输出端并接于所述的第四PMOS管的漏极和栅极,所述的第四PMOS管源极与所述的第五PMOS管的漏极连接,所述的第五PMOS管的源极和所述的第六PMOS管的源极并接于电源,所述的第六PMOS管的栅极和漏极及所述的第五NMOS管的漏极并接于所述的第五PMOS管的栅极,所述的第五NMOS管的栅极和源极接地。2. The anti-differential energy attack ternary counter based on SABL logic as claimed in claim 1, characterized in that said current compensation circuit consists of a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a fifth NMOS transistor The first signal output terminal and the second signal output terminal are connected in parallel to the drain and gate of the fourth PMOS tube, and the source of the fourth PMOS tube is connected to the The drain of the fifth PMOS transistor is connected, the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to the power supply in parallel, the gate and drain of the sixth PMOS transistor and the The drain of the fifth NMOS transistor is connected to the gate of the fifth PMOS transistor in parallel, and the gate and source of the fifth NMOS transistor are grounded.
CN201110305818.0A 2011-10-11 2011-10-11 Anti-differential power attack ternary counter based on sense amplification logic Expired - Fee Related CN102394637B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110305818.0A CN102394637B (en) 2011-10-11 2011-10-11 Anti-differential power attack ternary counter based on sense amplification logic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110305818.0A CN102394637B (en) 2011-10-11 2011-10-11 Anti-differential power attack ternary counter based on sense amplification logic

Publications (2)

Publication Number Publication Date
CN102394637A true CN102394637A (en) 2012-03-28
CN102394637B CN102394637B (en) 2014-06-25

Family

ID=45861848

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110305818.0A Expired - Fee Related CN102394637B (en) 2011-10-11 2011-10-11 Anti-differential power attack ternary counter based on sense amplification logic

Country Status (1)

Country Link
CN (1) CN102394637B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103595371A (en) * 2013-10-25 2014-02-19 宁波大学 Double-edge D flip-flop based on N type SABL logic
CN107682006A (en) * 2017-09-28 2018-02-09 宁波大学 A kind of three value forward-backward counters using carbon nano field-effect transistor
CN108446556A (en) * 2018-03-01 2018-08-24 北京智芯微电子科技有限公司 The anti-power consumption analysis circuit and method of crypto chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000090668A (en) * 1998-09-07 2000-03-31 Texas Instr Inc <Ti> Semiconductor memory circuit
CN101777139A (en) * 2009-12-30 2010-07-14 宁波大学 Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000090668A (en) * 1998-09-07 2000-03-31 Texas Instr Inc <Ti> Semiconductor memory circuit
CN101777139A (en) * 2009-12-30 2010-07-14 宁波大学 Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MASSIMO ALIOTO 等: "A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION(VLSI)SYSTEMS》 *
高宁 等: "一种新型灵敏放大器的设计", 《电子与封装》 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103595371A (en) * 2013-10-25 2014-02-19 宁波大学 Double-edge D flip-flop based on N type SABL logic
CN103595371B (en) * 2013-10-25 2015-09-30 宁波大学 A kind of Double-edge D trigger based on N-type SABL logic
CN107682006A (en) * 2017-09-28 2018-02-09 宁波大学 A kind of three value forward-backward counters using carbon nano field-effect transistor
CN107682006B (en) * 2017-09-28 2020-11-10 宁波大学 A three-value reversible counter using carbon nano-field effect transistors
CN108446556A (en) * 2018-03-01 2018-08-24 北京智芯微电子科技有限公司 The anti-power consumption analysis circuit and method of crypto chip
CN108446556B (en) * 2018-03-01 2020-04-07 北京智芯微电子科技有限公司 Power consumption resisting analysis circuit and method for cryptographic chip

Also Published As

Publication number Publication date
CN102394637B (en) 2014-06-25

Similar Documents

Publication Publication Date Title
Zhao et al. Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
CN103595371B (en) A kind of Double-edge D trigger based on N-type SABL logic
CN101834595A (en) A three-valued adiabatic circuit and a T operation circuit of a single-power clock-controlled transmission gate
Monteiro et al. Low‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design
CN104320246A (en) Configurable multi-bit key output TVD-PUFs (Threshold Variation Delay-Physical Unclonable functions) circuit
CN109327206B (en) Power flattening standard integrated circuits
CN101527628A (en) Full-custom AES SubByte circuit resisting differential power analysis attack
Wu et al. FPGA-based measurement and evaluation of power analysis attack resistant asynchronous S-Box
CN102394637A (en) Anti-differential power attack ternary counter based on sense amplification logic
Monteiro et al. Low power secure AES S-box using adiabatic logic circuit
Japa et al. Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption
Kim et al. Three phase dynamic current mode logic: A more secure DyCML to achieve a more balanced power consumption
Kahleifeh et al. Low-energy and CPA-resistant adiabatic CMOS/MTJ logic for IoT devices
Vakil et al. Comparitive analysis of null convention logic and synchronous CMOS ripple carry adders
CN102386908A (en) Heat insulation domino circuit and heat insulation domino ternary AND gate circuit
Rengarajan et al. Challenges to adopting adiabatic circuits for systems‐on‐a‐chip
Levi et al. A survey of the sensitivities of security oriented flip-flop circuits
Hong et al. Design of Ultra Low-Voltage NCL Circuits in Nanoscale MOSFET Technology
CN102684679A (en) Delay-based dual-rail precharge logic output converter
CN102780485B (en) Configurable D latch for chaos computing
CN103594119B (en) A kind of three value Low-power-consumptiodomino domino shift registers
Metku et al. Novel area-efficient null convention logic based on cmos and gate diffusion input (Gdi) hybrid
CN101799747A (en) Arithmetic logic unit ALU based on reversible logic
Gope et al. Modelling of single electron ternary flip-flop using SIMON
Bhandari A novel design approach of low power consuming Decoder using Reversible Logic gates

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20210111

Address after: Room A507-1, Building 9, Jiuhuan Road, Jianggan District, Hangzhou City, Zhejiang 310000

Patentee after: HANGZHOU MAEN SCIENCE & TECHNOLOGY Co.,Ltd.

Address before: 315211, Fenghua Road, Jiangbei District, Zhejiang, Ningbo 818

Patentee before: Ningbo University

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140625

Termination date: 20211011