CN109474415B

CN109474415B - Three-phase single-rail pre-charging logic device

Info

Publication number: CN109474415B
Application number: CN201811219004.3A
Authority: CN
Inventors: 赵毅强; 蔡里昂; 叶茂; 马浩诚; 辛睿山
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2018-10-19
Filing date: 2018-10-19
Publication date: 2022-06-21
Anticipated expiration: 2038-10-19
Also published as: CN109474415A

Abstract

The invention relates to the field of information security and power consumption attack resistance, and aims to prevent an attacker from obtaining power consumption difference in a discharging stage by slowing down a clock so as to disable protection. Meanwhile, the logic unit can enable the power consumption of the unit to be the same in each evaluation period, and eliminate the power consumption difference under different input signals, so that an attacker cannot acquire the key through DPA attack. Therefore, the technical scheme adopted by the invention is that the three-phase single-rail pre-charging logic device comprises a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4 and an NMOS transistor C1 which plays a role in charge storage. The invention is mainly applied to the integrated circuit design and manufacture occasions.

Description

Three-phase single-rail pre-charging logic device

Technical Field

The invention relates to the field of information security and the field of power consumption attack resistance. And more particularly to a three-phase single rail precharge logic device.

Background

In the modern society, cryptographic devices represented by Smart cards (Smart cards), USB keys (USB keys), and the like are widely used in important fields such as telecommunications, finance, and pay television, and become Key components of these applications, and therefore, their security is important. Although the embeddability of the cryptographic device makes an attacker unable to directly obtain the key information in the cryptographic chip, most cryptographic chips are composed of CMOS circuits, in such circuits, certain Power consumption, electromagnetic side channel information and the like are leaked when the circuits work, and the attacker analyzes the correlation between the key data and the Power consumption information by using a Differential Power Analysis (DPA) technology and obtains the key by analyzing in a mathematical statistics manner.

The basic idea behind DPA attacks is to eliminate the correlation between the current and the internal data when the cryptographic chip is working. Among them, the circuit level protection is more general because it focuses more on the implementation of the underlying circuit structure of the cryptographic chip rather than the cryptographic algorithm itself. The circuit level protection is usually realized by designing a novel logic unit, and the main design concept is dual-rail precharge logic and a three-stage operation mode. The unit realized by the Dual-Rail precharge Logic mainly comprises sensitive Amplifier Logic (SABL), traveling Wave Dynamic Differential Logic (WDDL), Delay-Based Dual-Rail precharge Logic (DDPL) and look-up table-Based Differential Logic (LBDL); the Logic unit realized by the Three-stage working mode comprises Three-stage double-rail Pre-charge Logic TDPL (Three-phase double-rail Pre-charge Logic) and Three-stage Single-rail Pre-charge Logic TSPL (Three-phase Single-rail Pre-charge Logic). The TSPL adopts three-stage working modes of pre-charging, evaluation and discharging, so that the influence of output load mismatching on the unit protection performance is avoided, the power consumption of the logic unit in each evaluation period is not related to an input signal, and the logic unit has excellent capacity of resisting DPA attack. Although the internal nodes of the logic cells undergo a charge and discharge operation in each evaluation cycle, the internal nodes undergo two discharge operations in the evaluation phase and the discharge phase, respectively, due to the difference of the input signals, and thus when the clock is slowed down, the discharge difference at different inputs is detected, and thus the TSPL has a risk of protection failure.

Reference to the literature

1.Bucci M,Giancane L,Luzzi R,et al.Three-phase dual-rail pre-charge logic[C]//International Conference on Cryptographic Hardware and Embedded Systems.Springer-Verlag,2006:232-241.

2.Akkaya N E C,Erbagci B,Carley R,et al.A DPA-resistant self-timed three-phase dual-rail pre-charge logic family[C]//IEEE International Symposium on Hardware Oriented Security and Trust.IEEE,2015:112-117.

3.Hassoune I,Mace F,Flandre D,et al.Dynamic differential self-timed logic families for robust and low-power security ICs[J].Integration the Vlsi Journal,2007,40(3):355-364.

4.Menendez E,Mai K.Extended abstract:A high-performance,low-overhead,power-analysis-resistant,single-rail logic style[C]//IEEE International Workshop on Hardware-Oriented Security and Trust.IEEE,2008:33-36。

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide a novel standard cell CS-TSPL suitable for a security chip, the logic cell can store a discharge signal in an evaluation stage and uniformly release the discharge signal in a discharge stage, and an attacker is prevented from obtaining power consumption difference in the discharge stage through a slow clock, so that protection is invalid. Meanwhile, the logic unit can enable the power consumption of the unit to be the same in each evaluation period, and eliminate the power consumption difference under different input signals, so that an attacker cannot acquire the key through DPA attack. Therefore, the technical scheme adopted by the invention is that the three-phase single-rail pre-charging logic device comprises a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4 and an NMOS transistor C1 playing a role in charge storage; the source electrode of the PMOS transistor P1 is connected with a power supply, the grid electrode is connected with a clock signal CLK, and the drain electrode is connected with the drain electrodes of the NMOS transistor tubes N1 and N4 and the output signal O in a public way; the gate of the NMOS transistor N1 is connected with the input signal I, and the source is connected with the drain of the NMOS transistor N2; the grid electrode of the NMOS transistor N2 is connected with a clock signal CLK, and the source electrode is commonly connected with the drain electrode of the NMOS tube N3 and the grid electrode of the NMOS tube C1; the grid electrode of the NMOS transistor N3 is connected with a discharge signal DCH, and the source electrode is grounded; the grid electrode of the NMOS transistor N4 is connected with a discharge signal DCH, and the source electrode is grounded; the source and drain of NMOS transistor C1 are connected, both to ground.

Further:

a pre-charging stage: the CLK signal is low and the DCH signal is low, at which time the PMOS transistor P1 is turned on, so that the output signal O is precharged to high, and since the input signal of the cell is the output of the previous stage, the signal I is high when the CLK signal is low, at which time the NMOS transistor N1 is turned on, so that all the internal nodes in the pull-down network are precharged to high. The NMOS transistor N2 is turned off, so that nodes in the pull-down network cannot be discharged, and similarly, the NMOS transistors N3 and N4 are turned off to prevent the discharge of the output node O and other internal nodes;

an evaluation phase: the CLK signal is high potential, the DCH signal is still low potential, at this time, the PMOS tube P1 is turned off, the power supply is prevented from charging the internal node, the grid electrode of the NMOS tube N1 receives the input signal I, the on-off of the N1 is controlled, the function of the INV unit is realized, when the input signal I is '1', the pull-down network is turned on, and a '0' signal is output, and when the input signal is '0', the pull-down network is turned off, the output keeps high potential, the NMOS tube N2 is turned on, so that the charge in the pull-down network can be discharged onto the capacitor C1, and because the NMOS tube N3 is turned off, the charge on the capacitor C1 can be stored and cannot be directly discharged onto the ground, and meanwhile, the NMOS tube N4 is turned off, so that the charge on the output node O cannot be discharged;

and (3) a discharging stage: the CLK signal is high potential, the DCH signal is high potential, at this time, the PMOS transistor P1 is turned off, the power supply is prevented from charging the internal nodes, the NMOS transistor N4 is turned on, so that the output node O is pulled down to low potential, and the input signal I receives the output signal of the previous stage, therefore, when the DCH signal is high potential, the NMOS transistor N1 is turned off, and simultaneously the NMOS transistors N2 and N3 are turned on, so that the nodes stored on the capacitor C1 are discharged to the ground, thereby realizing the discharging operation of all the internal nodes.

The invention has the characteristics and beneficial effects that:

by designing a novel standard unit, the power consumption difference of the logic unit under different signal inputs during operation is eliminated, so that nodes inside the unit have one-time evaluation and discharge operation in each period, and the DPA attack resistance of the unit is ensured. Meanwhile, the discharge charge in the evaluation stage is stored by using a capacitor formed by an NMOS tube and is discharged together with the discharge charge in the discharge stage, so that the operation of secondary discharge is avoided, and an attacker cannot acquire the current information in the evaluation stage by a slow clock.

Description of the drawings:

FIG. 1CS-TSPL logic INV cell circuit diagram.

FIG. 2 is a timing diagram of the operation of the CS-TSPL logic INV cell.

Detailed Description

The invention provides a three-stage single-rail pre-charging structure (CS-TSPL) with a charge storage function based on three-stage single-rail pre-charging logic.

In order to improve the DPA attack resistance of the cell, a three-stage single-rail pre-charge logic structure (CS-TSPL) with a charge storage function is provided. The unit structure and the operation principle of the standard cell will be described with reference to fig. 1 and 2. The basic structure of the logic unit is single-rail dynamic logic, and fig. 1 is a circuit diagram of an INV unit of ST-TDPL structure, where I is an input signal of the unit, CLK is a clock control signal of the unit, O is an output signal of the unit, indicating an inverted output result of the signal I, and DCH signal is a discharge signal.

The logic unit includes a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, and an NMOS transistor C1 functioning as a charge storage. The source electrode of the PMOS transistor P1 is connected with a power supply, the grid electrode is connected with a clock signal CLK, and the drain electrode is connected with the drain electrodes of the NMOS transistor tubes N1 and N4 and the output signal O in a public way; the gate of the NMOS transistor N1 is connected with the input signal I, and the source is connected with the drain of the NMOS transistor N2; the grid electrode of the NMOS transistor N2 is connected with a clock signal CLK, and the source electrode is connected with the drain electrode of the NMOS tube N3 and the grid electrode of the NMOS tube C1 in a public way; the grid electrode of the NMOS transistor N3 is connected with a discharge signal DCH, and the source electrode is grounded; the grid electrode of the NMOS transistor N4 is connected with a discharge signal DCH, and the source electrode is grounded; the source and drain of the NMOS transistor C1 are connected, both to ground.

The working mode of the standard cell is divided into three working phases of pre-charging, evaluation and discharging. The operation of the unit in the three stages is specifically analyzed below.

A pre-charging stage: the CLK signal is low and the DCH signal is low, such that the PMOS transistor P1 is turned on and the output signal O is precharged to high. Meanwhile, because the input signal of the cell is the output of the previous stage, the signal I is at a high level when CLK is at a low level, and at this time, the NMOS transistor N1 is turned on, so that all internal nodes in the pull-down network are precharged to a high level. The NMOS transistor N2 is turned off, so that nodes in the pull-down network cannot be drained, and similarly, the NMOS transistors N3 and N4 are turned off, and the output node O and other internal nodes are prevented from discharging.

An evaluation phase: the CLK signal is high and the DCH signal is still low, at which time the PMOS transistor P1 is turned off, preventing the power supply from charging the internal nodes. The grid electrode of the NMOS tube N1 receives an input signal I, the on-off of the N1 is controlled, the function of the INV unit is achieved, when the input signal I is '1', the pull-down network is conducted, a '0' signal is output, and when the input signal is '0', the pull-down network is turned off, and the output keeps high potential. The NMOS transistor N2 is turned on, so that the charge in the pull-down network can be discharged to the capacitor C1, and since the NMOS transistor N3 is turned off, the charge on the capacitor C1 is stored and is not directly discharged to the ground. Meanwhile, the NMOS transistor N4 is turned off, so that the charge on the output node O is not discharged.

And (3) a discharging stage: the CLK signal is high and the DCH signal is high. At this time, the PMOS transistor P1 is turned off, preventing the power supply from charging the internal node. The NMOS transistor N4 is turned on, so that the output node O is pulled down to a low potential. Meanwhile, the input signal I receives the output signal of the previous stage, so that the NMOS transistor N1 is turned off when the DCH signal is high. Meanwhile, the NMOS transistors N2 and N3 are conducted, so that the node stored on the capacitor C1 is discharged to the ground, and the discharging operation of all internal nodes is realized.

In a conventional TSPL cell, during an evaluation phase, a pull-down network is turned on according to a value of an input signal, so that a part of charges are discharged to the ground during the evaluation phase, and during a discharge phase, the rest of charges are discharged through a discharge network, so that two discharge operations are performed, and under different input signals, discharge currents during the evaluation phase are different and are vulnerable. In the unit, the NMOS tube C1 plays a role of virtual ground, the charges discharged in the evaluation stage are stored in the C1 instead of directly discharged to the ground, the part of the stored charges are discharged together with the residual charges in the discharge stage, so that the unit only has a current spike in the discharge stage during operation, and the discharge current has no correlation with the input signal, thereby eliminating the power consumption difference under different input signals and improving the protection capability of the unit.

When designing a CS-TDPL logic unit, attention is paid to the size of a capacitor formed by an NMOS tube C1. When the pull-down network is on, capacitor C1 and the internal node capacitance together distribute the charge drawn from the power supply during the precharge phase, i.e.: VDD × CL ═ VL (C)_L+ C1), wherein V_DDIs a power supply voltage, and also outputs a high level potential, C_LIs internal node capacitance, V_LThe output is a low level potential, and C1 is a capacitance formed by NMOS transistors. When C is present_LWhen it is sufficiently large, V_LWill be pulled to a sufficiently low potential to ensure proper output of the cell.

Claims

1. A three-phase single-rail pre-charge logic device is characterized by comprising a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4 and an NMOS transistor C1 which plays a role in charge storage; the source electrode of the PMOS transistor P1 is connected with a power supply, the grid electrode is connected with a clock signal CLK, and the drain electrode is commonly connected with the drain electrodes of the NMOS transistors N1 and N4 and an output node O; the gate of the NMOS transistor N1 is connected with the input signal I, and the source is connected with the drain of the NMOS transistor N2; the grid electrode of the NMOS transistor N2 is connected with a clock signal CLK, and the source electrode is connected with the drain electrode of the NMOS transistor N3 and the grid electrode of the NMOS transistor C1 in a common way; the grid electrode of the NMOS transistor N3 is connected with a discharge signal DCH, and the source electrode is grounded; the grid electrode of the NMOS transistor N4 is connected with a discharge signal DCH, and the source electrode is grounded; the source electrode and the drain electrode of the NMOS transistor C1 are connected and are commonly grounded;

a pre-charging stage: the CLK signal is low potential, the DCH signal is low potential, the PMOS transistor P1 is conducted at the moment, the output node O is precharged to high potential, the input signal I is high level when the CLK is low level, the NMOS transistor N1 is conducted at the moment, all internal nodes in the pull-down network are precharged to high potential, the NMOS transistor N2 is turned off, the charges on the internal nodes in the pull-down network are not discharged, and the NMOS transistors N3 and N4 are turned off in a similar manner, so that the output node O and the rest internal nodes are prevented from being discharged;

an evaluation phase: the CLK signal is high potential, the DCH signal is still low potential, at this time, the PMOS tube P1 is turned off, the power supply is prevented from charging the internal node, the grid of the NMOS transistor N1 receives the input signal I, the on-off of the N1 is controlled, the function of the INV unit is realized, when the input signal I is 1, the pull-down network is turned on, 0 signal is output, when the input signal is 0, the pull-down network is turned off, the output keeps high potential, the NMOS transistor N2 is turned on, so that the charge in the pull-down network is discharged to the capacitor C1, and because the NMOS transistor N3 is turned off, the charge on the capacitor C1 is stored and is not directly discharged to the ground, and meanwhile, the NMOS transistor N4 is turned off, so that the charge on the output node O is not discharged;

and (3) a discharging stage: the CLK signal is high and the DCH signal is high, at which time the PMOS transistor P1 is turned off to prevent the power from charging the internal nodes, the NMOS transistor N4 is turned on, so that the output node O is pulled down to low, and at the same time the input signal I enters the gate of the NMOS transistor N1, when the DCH signal is high, the NMOS transistor N1 is turned off, and at the same time the NMOS transistors N2 and N3 are turned on, so that the charge stored on the capacitor C1 is drained to the ground, thereby achieving the discharging operation of all the internal nodes.