CN104571249A - Power-consumption self-adaptive linear voltage regulator - Google Patents
Power-consumption self-adaptive linear voltage regulator Download PDFInfo
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- CN104571249A CN104571249A CN201510037935.1A CN201510037935A CN104571249A CN 104571249 A CN104571249 A CN 104571249A CN 201510037935 A CN201510037935 A CN 201510037935A CN 104571249 A CN104571249 A CN 104571249A
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Abstract
The invention discloses a power-consumption self-adaptive linear voltage regulator. The power-consumption self-adaptive linear voltage regulator comprises an error amplifier, a buffer with an automatic bias current adjusting function, an output driving pipe and a feedback circuit. The buffer can adjust its bias current in real time according to load conditions. Meanwhile, the optimum effect is realized, and circuit stability is guaranteed. Compared with the structure of the prior art, the power-consumption self-adaptive linear voltage regulator has lower no-load current and wider output driving range.
Description
Technical field
The present invention relates to a kind of linear voltage regulator, particularly a kind of power consumption adaptive line voltage stabilizer.
Background technology
Low pressure difference linear voltage regulator is usually integrated in the chips for circuit provides accurate, stable supply voltage.Linear voltage regulator requires equal energy reliably working under different power voltage usually, and therefore its circuit structure itself must adapt to very wide voltage range.In addition as power supply, its output current has very wide variation range (a unloaded hundreds of milliampere).Corresponding equivalent output load changes to tens Europe from a few megaohm always, and from the feedback control loop of low pressure difference linear voltage regulator, its position exporting limit can change four or five orders of magnitude, brings very large challenge to loop stability design.In order to ensure stability, common way is at an output terminal very large electric capacity in parallel, moves output limit to enough low position, until in minimum load situation the unit gain frequency of feedback control loop still lower than the position of loop second limit.But consequence is bulky capacitor (normally tens of to hundreds of μ F) in parallel seriously limits loop bandwidth, also declines to some extent to the rejection ability of interference and power-supply fluctuation.Another kind method uses impact damper (normally source follower) to isolate error amplifier and driving tube, to improve second, the position of the 3rd limit, even if the position of dominant pole (output limit) changes a lot, the position of secondary limit is still greater than unit gain frequency.But the major defect done like this to realize higher secondary pole location, need very large electric current to drive these impact dampers, directly results in the high power consumption of low pressure difference linear voltage regulator.In order to improve efficiency, needing to design the impact damper with more high current efficiency, very low output resistance can be realized under lower bias current.
Another kind more efficiently mode adopts adaptive frequency compensation technology, namely time pole location makes corresponding change according to the change of dominant pole, when dominant pole position is lower, only need lower electric current just can realize ensureing that time limit is greater than unit gain frequency.And when exporting big current and load is lower, extra current is injected to impact damper, time limit is increased with identical speed with dominant pole, continues the stability ensureing loop.Adaptive frequency compensation technology due to its high current utilization rate and flexibly bandwidth control mode obtain a wide range of applications in academia and industry member.For realizing adaptive frequency compensation, to follow the trail of with automatic current and the design of current buffer of regulatory function seems very crucial.Traditional buffer circuits is usually structurally comparatively complicated, often stacked more transistor size between VDD-to-VSS.But constantly reduce along with integrated circuit kernel supply voltage, under linear voltage regulator also needs to be operated in lower supply voltage, now conventional buffer structure cannot continue to use.
Summary of the invention
Goal of the invention: for above-mentioned prior art, proposes a kind of application scenario being applicable to low suppling voltage, wide driving scope, and has the linear voltage regulator of self-adaptive current regulatory function, can ensure the frequency stability in any drive current situation.
Technical scheme: a kind of power consumption adaptive line voltage stabilizer, comprises the first to the 9th PMOS, the first to the 3rd NMOS tube, first to fourth resistance, the first electric capacity, the second electric capacity and reference current source; Wherein, the grid of described first PMOS and drain electrode connect the positive pole of reference current source, and its source electrode connects external power source, the minus earth of reference current source; The source electrode of the second PMOS connects external power source, and its grid connects the grid of the first PMOS, and its drain electrode connects the source electrode of the 3rd PMOS and the 4th PMOS; The grid of the 3rd PMOS connects external reference voltage, and its drain electrode connects grid and the drain electrode of the first NMOS tube; The drain electrode of the 4th PMOS connects the drain electrode of the second NMOS tube; The grid of the second NMOS tube connects the grid of the first NMOS tube, the source ground of the first NMOS tube and the second NMOS tube; The grid of the 3rd NMOS tube connects the drain electrode of the second NMOS tube, its source ground, and its drain electrode connects the drain electrode of the 5th PMOS; The source electrode of the 5th PMOS connects one end of the first resistance, another termination external power source of the first resistance; The grid of the 7th PMOS connects the drain electrode of the 3rd NMOS tube and one end of the second resistance, one end of another termination second electric capacity of the second resistance, the other end ground connection of the second electric capacity; The grounded drain of the 7th PMOS, its source electrode connects the grid of the 5th PMOS and the drain electrode of the 6th PMOS; The grid of the 6th PMOS connects the grid of the first PMOS, and its source electrode connects external power source; The source electrode of the 8th PMOS connects external power source, and its drain and gate connects the source electrode of the 7th PMOS; The source electrode of the 9th PMOS connects power supply, and its grid connects the source electrode of the 7th PMOS, and the drain electrode of the 9th PMOS connects one end of the 3rd resistance, one end of another termination the 4th resistance of the 3rd resistance and the grid of the 4th PMOS, the other end ground connection of the 4th resistance; The drain electrode of the 9th PMOS is output voltage node, a termination VOUT of the first electric capacity, the other end ground connection of the first electric capacity.
Beneficial effect: a kind of power consumption adaptive line voltage stabilizer of the present invention, by arranging adaptive buffer between error amplifier and power drive pipe, change the bias current of this impact damper when different driving electric current in good time, while realizing more high energy efficiency, meet the frequency stability under all loading conditions.This buffer structure is simple, has very low quiescent dissipation and wider impedance variation scope, can meet the output current of maximum 200mA.
Accompanying drawing explanation
Fig. 1 is power consumption adaptive line voltage regulator circuit structural drawing of the present invention;
Fig. 2 is loop gain amplitude versus frequency characte Bode diagram under linear voltage regulator maximum current drive of the present invention and no-load condition;
Fig. 3 is the relation curve of loop phase nargin with drive current variations.
Embodiment
Below in conjunction with accompanying drawing the present invention done and further explain.
As shown in Figure 1, a kind of power consumption adaptive line voltage stabilizer is made up of error amplifier, current automatic adaptation impact damper and driving circuit and feedback resistance.When this linear voltage regulator is in unloaded or low current mode output, buffers bias at lower current, ensure that lower quiescent dissipation while meeting enough phase margins.And when linear voltage regulator drive current is larger, a part of drive current to be copied by current mirror and is injected in the bias current of impact damper by impact damper, reduce the high frequency output impedance of impact damper and the secondary limit of loop is raised, ensure that the unit gain frequency of loop is all the time lower than 1/2nd of secondary limit.Physical circuit topological relation is:
Power consumption adaptive line voltage stabilizer comprises first to the 9th PMOS PM1 ~ PM9, first to the 3rd NMOS tube NM1 ~ NM3, first to fourth resistance R1 ~ R4, the first electric capacity C1, the second electric capacity C2 and reference current source IDC1.Wherein, the grid of the first PMOS PM1 and drain electrode connect the positive pole of reference current source IDC1, the minus earth of reference current source IDC1.The source electrode of the second PMOS PM2 connects external power source, and its grid connects the grid of the first PMOS PM1, and its drain electrode connects the source electrode of the 3rd PMOS PM3 and the 4th PMOS PM4.The grid of the 3rd PMOS PM3 meets external reference voltage VREF, and its drain electrode connects grid and the drain electrode of the first NMOS tube NM1.The drain electrode of the 4th PMOS PM4 connects the drain electrode of the second NMOS tube NM2.The grid of the second NMOS tube NM2 connects the grid of the first NMOS tube NM1, the source ground of the first NMOS tube NM1 and the second NMOS tube NM2.The grid of the 3rd NMOS tube NM3 connects the drain electrode of the second NMOS tube NM2, its source ground, and its drain electrode connects the drain electrode of the 5th PMOS PM5.The source electrode of the 5th PMOS PM5 connects one end of the first resistance R1, another termination external power source of the first resistance R1.The grid of the 7th PMOS PM7 connects the drain electrode of the 3rd NMOS tube NM3 and one end of the second resistance R2, one end of another termination second electric capacity C2 of the second resistance R2, the other end ground connection of the second electric capacity C2.The grounded drain of the 7th PMOS PM7, its source electrode connects the grid of the 5th PMOS PM5 and the drain electrode of the 6th PMOS PM6.The grid of the 6th PMOS PM6 connects the grid of the first PMOS PM1, and its source electrode connects external power source.The source electrode of the 8th PMOS PM8 connects external power source, and its drain and gate connects the source electrode of the 7th PMOS PM7.The source electrode of the 9th PMOS PM9 connects power supply, its grid connects the source electrode of the 7th PMOS PM7, the drain electrode of the 9th PMOS PM9 connects one end of the 3rd resistance R3, one end of another termination the 4th resistance R4 of the 3rd resistance R3 and the grid of the 4th PMOS PM4, the other end ground connection of the 4th resistance R4.The drain electrode of the 9th PMOS PM9 is output voltage node VOUT, a termination VOUT of the first electric capacity C1, the other end ground connection of the first electric capacity C1.Wherein, the input V of external power source and linear voltage regulator
in.
Error amplifier is wherein the typical structure of traditional Differential Input, Single-end output; NM3, PM5, PM6, PM7, R1 constitute current automatic adaptation impact damper.Traditional to follow based on source or the impact damper of structure is followed in super source, usually have the side-play amount of a gate source voltage between its input and output voltage, this has the output current that can limit this circuit in limited time at supply voltage.Current automatic adaptation impact damper of the present invention under operating conditions, the drain voltage of NM3 can about a threshold voltage lower than its grid voltage, compensate for the pressure reduction between the source electrode of PM7 and grid to a certain extent, therefore there is side-play amount hardly between this voltage buffer input and output voltage, improve the performance of the linear voltage regulator under low-voltage.This current automatic adaptation buffer output end creates mutual conductance by negative-feedback technology and strengthens effect, namely the change in voltage of PM5 grid is exaggerated at the drain terminal of PM5, extra electric current is injected by PM7, its equivalent is that the input impedance of PM7 source electrode is greatly reduced, and unnecessary follower bandwidth is transformed into output impedance lower in be concerned about bandwidth by this negative feedback structure.PM8 monitors the situation of output current, and is copied by a part of output current and be injected in buffer circuits, and then reduces the output impedance of impact damper, ensure that the phase margin of whole feedback loop under any driving loading condition.
Figure 2 shows that the loop gain amplitude-frequency response Bode diagram of this power consumption adaptive line voltage stabilizer under maximum output current and no-load condition.As can be seen from the figure this power consumption adaptive line voltage stabilizer can adjust time pole location in real time according to the change of unity gain bandwidth: when being in light condition, unit gain frequency is lower, and now its impact damper is in Low-bias Current pattern and is dragged down by secondary pole location; When being in maximum drive current pattern, along with dominant pole position is improved, unit gain frequency also improves thereupon, and now impact damper is in high bias currents pattern, and secondary pole location also synchronously raises, and ensure that enough phase margins.
Figure 3 shows that the variation relation of loop phase nargin with drive current, as can be seen from the figure, when drive current is enough low, dominant pole and unit gain frequency are all in very low position, and now phase margin is close to 90 degree.Along with drive current constantly increases, unit gain frequency progressively improves and constantly near time limit, phase margin also constantly declines thereupon.When unit gain frequency is fallen near time limit 1/2nd frequency, phase margin is close to 60 degree, the extra current effect being now injected into impact damper starts to manifest, subsequently when drive current constantly raises, the speed of secondary limit movement has caught up with the pace of change of unit gain frequency, and phase margin also slightly rises thereupon.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (1)
1. a power consumption adaptive line voltage stabilizer, it is characterized in that: comprise the first to the 9th PMOS (PM1 ~ PM9), the first to the 3rd NMOS tube (NM1 ~ NM3), first to fourth resistance (R1 ~ R4), the first electric capacity (C1), the second electric capacity (C2) and reference current source (IDC1); Wherein, the grid of described first PMOS (PM1) and drain electrode connect the positive pole of reference current source (IDC1), and its source electrode connects external power source, the minus earth of reference current source (IDC1); The source electrode of the second PMOS (PM2) connects external power source, and its grid connects the grid of the first PMOS (PM1), and its drain electrode connects the source electrode of the 3rd PMOS (PM3) and the 4th PMOS (PM4); The grid of the 3rd PMOS (PM3) connects external reference voltage (VREF), and its drain electrode connects grid and the drain electrode of the first NMOS tube (NM1); The drain electrode of the 4th PMOS (PM4) connects the drain electrode of the second NMOS tube (NM2); The grid of the second NMOS tube (NM2) connects the grid of the first NMOS tube (NM1), the source ground of the first NMOS tube (NM1) and the second NMOS tube (NM2); The grid of the 3rd NMOS tube (NM3) connects the drain electrode of the second NMOS tube (NM2), its source ground, and its drain electrode connects the drain electrode of the 5th PMOS (PM5); The source electrode of the 5th PMOS (PM5) connects one end of the first resistance (R1), another termination external power source of the first resistance (R1); The grid of the 7th PMOS (PM7) connects the drain electrode of the 3rd NMOS tube (NM3) and one end of the second resistance (R2), one end of another termination second electric capacity (C2) of the second resistance (R2), the other end ground connection of the second electric capacity (C2); The grounded drain of the 7th PMOS (PM7), its source electrode connects the grid of the 5th PMOS (PM5) and the drain electrode of the 6th PMOS (PM6); The grid of the 6th PMOS (PM6) connects the grid of the first PMOS (PM1), and its source electrode connects external power source; The source electrode of the 8th PMOS (PM8) connects external power source, and its drain and gate connects the source electrode of the 7th PMOS (PM7); The source electrode of the 9th PMOS (PM9) connects power supply, its grid connects the source electrode of the 7th PMOS (PM7), the drain electrode of the 9th PMOS (PM9) connects one end of the 3rd resistance (R3), one end of another termination the 4th resistance (R4) of the 3rd resistance (R3) and the grid of the 4th PMOS (PM4), the other end ground connection of the 4th resistance (R4); The drain electrode of the 9th PMOS (PM9) is a termination VOUT of output voltage node (VOUT), the first electric capacity (C1), the other end ground connection of the first electric capacity (C1).
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| CN201510037935.1A CN104571249B (en) | 2015-01-26 | 2015-01-26 | A kind of power consumption adaptive line manostat |
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| CN201510037935.1A CN104571249B (en) | 2015-01-26 | 2015-01-26 | A kind of power consumption adaptive line manostat |
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| CN106292824A (en) * | 2015-06-29 | 2017-01-04 | 展讯通信（上海）有限公司 | low-dropout regulator circuit |
| CN109710022A (en) * | 2019-01-07 | 2019-05-03 | 上海奥令科电子科技有限公司 | A kind of voltage regulator circuit |
| KR20200007667A (en) * | 2018-07-13 | 2020-01-22 | 에이블릭 가부시키가이샤 | Voltage regulator and method of controlling voltage regulator |
| CN111176358A (en) * | 2019-12-27 | 2020-05-19 | 成都锐成芯微科技股份有限公司 | Low-power-consumption low-dropout linear voltage regulator |
| CN111221374A (en) * | 2020-01-16 | 2020-06-02 | 东南大学 | Full-integrated load pole compensation linear voltage regulator |
| CN111414040A (en) * | 2020-04-10 | 2020-07-14 | 上海兆芯集成电路有限公司 | Low dropout linear regulator |
| CN112558668A (en) * | 2020-12-08 | 2021-03-26 | 大连民族大学 | LDO circuit based on chopping technology |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106292824A (en) * | 2015-06-29 | 2017-01-04 | 展讯通信（上海）有限公司 | low-dropout regulator circuit |
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| KR20200007667A (en) * | 2018-07-13 | 2020-01-22 | 에이블릭 가부시키가이샤 | Voltage regulator and method of controlling voltage regulator |
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| TWI793339B (en) * | 2018-07-13 | 2023-02-21 | 日商艾普凌科有限公司 | Voltage regulator and method for controlling the voltage regulator |
| JP7063753B2 (en) | 2018-07-13 | 2022-05-09 | エイブリック株式会社 | Voltage regulator and voltage regulator control method |
| CN109710022A (en) * | 2019-01-07 | 2019-05-03 | 上海奥令科电子科技有限公司 | A kind of voltage regulator circuit |
| CN111176358B (en) * | 2019-12-27 | 2021-11-02 | 成都锐成芯微科技股份有限公司 | Low-power-consumption low-dropout linear voltage regulator |
| CN111176358A (en) * | 2019-12-27 | 2020-05-19 | 成都锐成芯微科技股份有限公司 | Low-power-consumption low-dropout linear voltage regulator |
| CN111221374A (en) * | 2020-01-16 | 2020-06-02 | 东南大学 | Full-integrated load pole compensation linear voltage regulator |
| CN111414040A (en) * | 2020-04-10 | 2020-07-14 | 上海兆芯集成电路有限公司 | Low dropout linear regulator |
| CN112558668A (en) * | 2020-12-08 | 2021-03-26 | 大连民族大学 | LDO circuit based on chopping technology |
| CN112558668B (en) * | 2020-12-08 | 2022-05-20 | 大连民族大学 | LDO circuit based on chopping technology |
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