JP2014140269A - Switching regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching regulator that improves power consumption efficiency in a light load condition by controlling a change in a ripple voltage of an output voltage.SOLUTION: An inductor current IL flowing through an inductor L1 is controllingly switched in response to control voltages of a PWM control circuit section 10. A first voltage comparison circuit 15 outputs a state detection signal LVLX when the inductor current IL becomes zero or decreases. A second voltage comparison circuit 11, 12 compares a first constant voltage Vref1 and a second constant voltage Vref2 as a reference voltage Vref with a feedback voltage FB. A state transition control circuit 14 stops the switching operation when the first voltage comparison circuit 15 detects that excitation energy of the inductor has become zero or decreased, and selects the second constant voltage Vref2 to serve as the reference voltage Vref for the feedback voltage FB when the second voltage comparison circuit 11, 12 detects that the feedback voltage VB has fallen below the first constant voltage Vref1 as the reference voltage Vref.

Description

The present invention relates to a switching regulator capable of reducing a self-current consumption at a light load by making it possible to control output voltage ripple over a wide range, and a control method thereof.

In recent years, power saving of electronic devices has been demanded in consideration of environmental problems, and the demand for power saving is particularly remarkable in battery-driven electronic devices.
In general, in order to save power, it is important to reduce power consumed in an electronic device, improve power use efficiency of the power supply circuit itself, and suppress wasteful power consumption.
Non-insulated switching regulators using inductors are widely used as high-efficiency power supply circuits used in small electronic devices.

There are roughly two known control methods for switching regulators. One of them is a method of changing the duty cycle of a clock signal having a constant frequency. In other words, this is a PWM (pulse width modulation) control mode method in which the on-time of the switching transistor is changed to control the output voltage to be constant.

The other is a method of changing the cycle of the clock signal with a constant pulse width. That is, this is a VFM (Variable Frequency Modulation) control mode method in which the output voltage is controlled to be constant by changing the switching frequency while keeping the ON time of the switching transistor constant.

As a method of the VFM control mode, there are a method of changing the frequency steplessly and a method of changing the frequency in a pseudo manner by thinning out a clock signal having a frequency used in PWM control. VFM may be expressed as PFM (Pulse Frequency Modulation).

The power consumption of the switching regulator itself increases in proportion to the switching frequency. In the PWM control mode, the ON / OFF control of the switching transistor is performed at a constant cycle even at light load, so that the power consumption efficiency at light load deteriorates.

On the other hand, in the VFM control mode, the switching frequency of the switching transistor changes according to the load current (current flowing through the load). For this reason, the influence of noise and ripple on the device is increased, but the number of switching times at light load is reduced, so that the power use efficiency is improved as compared with the PWM control mode.

Accordingly, switching regulators have been developed that increase power consumption efficiency from light loads to heavy loads by switching control between the PWM control mode and the VFM control mode according to the load conditions.

However, since the noise generated from the switching regulator has a great influence on surrounding electronic devices, it is necessary to consider this noise.
Among them, the noise component due to the switching regulator is the largest due to the switching frequency of the switching transistor.

In the VFM control mode, the frequency varies according to the load current (also referred to as output current), so that the noise component generated from the switching regulator also varies according to the load current. Therefore, it is necessary to consider the influence on the surrounding electronic equipment regarding the fluctuation of the noise component.

In general, when the control is performed in the VFM control mode, the ripple of the output voltage is larger than when the control is performed in the PWM control mode. In the VFM control mode, since the maximum switching frequency in the VFM control mode is not fixed, the switching transistor is turned on and energy is supplied to the inductor before the inductor current (current flowing through the inductor) becomes zero. Has a problem that the ripple of the output voltage further increases.
Hereinafter, the reason will be described with reference to the switching regulator shown in FIG.

FIG. 10 is a circuit diagram of a voltage mode control type switching regulator capable of switching between PWM control mode and VFM control mode.
In FIG. 10, R1 and R2 are feedback resistors, 111 is an error amplifier (AMP), 112 and 113 are comparators (CMP), 130 is an oscillation circuit, 131 is an oscillation control circuit, 140 is an RS flip-flop circuit, and 150 is a control Circuit, M101 is a switching transistor, M102 is a synchronous rectification transistor, L1 is an inductor, Co is an output capacitor, 120 is a load, 180 is a voltage generation circuit, IN is an input terminal, OUT is an output terminal, Vref is a first reference voltage (see Voltage), Vrefm is a second reference voltage (), and LX is a connection point. The voltage generation circuit 180 has a function of generating a ramp voltage Vc including a triangular wave voltage.

First, it is assumed that charges are accumulated in the output capacitor Co, and the charges accumulated in the output capacitor Co are discharged from the output terminal OUT toward the load 120.
When the charge stored in the output capacitor Co is discharged from the output terminal OUT to the load 120 and the load current Iout flows, the output voltage Vout gradually decreases.
The error amplifier 111 amplifies a voltage corresponding to the difference between the first reference voltage Vref and the decrease in the output voltage Vout, and outputs an error voltage opout. The error voltage opout rises contrary to the decrease of the output voltage Vout.

When the error voltage opout exceeds the second reference voltage Vrefm, the comparator 112 inverts the state detection signal CMPOUT and outputs the inverted signal to the transmission control circuit 131. As a result, the signal level of the enable signal OSCEN of the transmission control circuit 131 is inverted and changes from the low level to the high level.

When the signal level of the enable signal OSCEN becomes a high level, the oscillation circuit 130 generates a high-level pulse and outputs it as a clock signal CLK to the RS flip-flop circuit 140.

By this clock signal CLK, the RS flip-flop circuit 140 is set, and its output terminal Q becomes high level. As a result, the control circuit 150 sets the control voltages PHS and NLS to low level, turning on the switching transistor M101 and turning off the synchronous rectification transistor M102.

When the switching transistor M101 is turned on, the input voltage Vin is applied to the inductor L1, and the inductor current IL flows through the inductor L1. The inductor current IL increases with a slope proportional to the voltage difference between the input voltage Vin and the output voltage Vout.

When the inductor current IL exceeds the output current Iout, the output capacitor Co is charged, so that the output voltage Vout increases, and as a result, the error voltage opout decreases.
When the error voltage opout falls below the second reference voltage Vrefm, the state output signal CMPOUT of the comparator 112 is inverted, and as a result, the signal level of the enable signal OSCEN is inverted and becomes low level again.

When the signal level of the enable signal OSCEN becomes low level, the oscillation circuit 130 generates one pulse at low level and outputs it as a clock signal CLK to the RS flip-flop 140 to stop the oscillation operation.

The voltage generation circuit 180 outputs the ramp voltage Vc and is input to the non-inverting input terminal of the comparator 113. The ramp voltage Vc rises with time, and when the ramp voltage Vc exceeds the error voltage opout, the signal level of the comparison output voltage PWMOUT of the comparator 113 is inverted and changes from the low level to the high level.

When the comparison output voltage PWMOUT becomes high level, the RS flip-flop circuit 140 is reset, the output terminal Q becomes low level, and the control circuit 150 sets the control voltages PHS and NLS to high level, respectively.

For this reason, the switching transistor M101 is turned off, and the synchronous rectification transistor M102 is turned on. As a result, the inductor current IL decreases with a slope proportional to the output voltage Vout. When the current value of the inductor current IL falls below the output current Iout, the output voltage Vout starts to fall, and when the output voltage Vout falls, the error voltage opout rises.
When the error voltage opout exceeds the second reference voltage Vrefm, the state detection signal CMPOUT is inverted, the enable signal OSCEN changes from low level to high level, and the operation as described above is repeated.

In the VFM control mode, the smaller the output current Iout, the longer it takes to lower the output voltage Vout, so that it takes time to increase the error voltage opout, and as a result, the interval at which the enable signal OSCEN is at a low level becomes longer. The switching frequency is lowered. On the other hand, when the output current Iout increases, the switching frequency increases, and when the error voltage opout is always equal to or higher than the second reference voltage Vrefm, the mode automatically switches to the PWM control mode.

In the PWM control mode, since the error voltage opout is always equal to or higher than the second reference voltage Vrefm, the state detection signal CMPOUT of the comparator 112 is maintained at a low level, and the enable signal OSCEN is at a high level. Then, the oscillation circuit 130 oscillates at a predetermined frequency, and generates and outputs a clock signal CLK having a predetermined frequency. That is, it is controlled in the PWM control mode.

However, in the conventional switching regulator shown in FIG. 10, the peak of the inductor current IL in the VFM control mode is determined substantially depending on the voltage value of the second reference voltage Vrefm and the slope of the ramp voltage Vc.

In the case of such a control method, the ripple voltage of the output voltage Vout varies due to various factors. When the ripple voltage of the output voltage Vout decreases, the switching frequency in the VFM control mode increases and the power consumption efficiency does not improve. Further, if the ripple voltage of the output voltage Vout becomes excessive, it will greatly exceed the set output voltage range, which may seriously damage the load-side electronic device.

FIG. 11 is a graph showing the relationship between the ripple voltage waveform RP of the output voltage Vout and the waveform ILP of the inductor current IL corresponding to the output voltage Vout at a certain setting value of the switching regulator shown in FIG.

FIG. 12 shows a ripple voltage waveform RP ′ of the output voltage Vout ′ smaller than the output voltage Vout shown in FIG. 11 and a waveform ILP ′ of the inductor current IL ′ corresponding to the output voltage Vout ′.
In FIG. 12, each waveform indicated by a dotted line indicates the same waveform as each waveform shown in FIG.

In FIG. 12, since the output voltage Vout ′ is low, the decreasing slope of the inductor current IL ′ becomes small as shown by the solid line, and the amount of charge supplied to the output capacitor Co is greatly increased.
That is, in the switching regulator shown in FIG. 10, when the output voltage Vout decreases, the ripple voltage increases. In general, a load-side electronic device that requires a low voltage has a narrow voltage tolerance range, and thus is unlikely to be used with the same control method.

FIG. 13 shows a ripple voltage waveform RP ′ of the output voltage Vout and a waveform ILP ″ of the inductor current IL ″ when the inductor L1 having an inductance smaller than the inductance of the inductor L1 shown in FIG. 10 is used. In FIG. 13, the waveform indicated by the dotted line shows the same waveform as that shown in FIG.

In FIG. 13, since the inductance of the inductor L1 is small, the slope of the inductor current IL ″ increases as shown by the solid line, and the amount of charge supplied to the output capacitor Co is greatly reduced.
Thus, in the switching regulator shown in FIG. 10, when the inductance of the inductor L1 is reduced, the ripple voltage of the output voltage Vout is reduced. That is, in the switching regulator shown in FIG. 10, when the ripple voltage of the output voltage Vout decreases, the oscillation frequency increases and the power consumption efficiency at the time of light load, which is the purpose of the VFM control mode, is deteriorated.
Thus, fluctuations in the output voltage Vout cause power consumption efficiency at light loads, noise, damage to electronic devices on the load side, and the like.

The present invention has been made in view of the above circumstances, and a switching regulator capable of further improving the power consumption efficiency at light loads by controlling fluctuations in the ripple voltage of the output voltage and its control It aims to provide a method.

A switching regulator according to the present invention includes a switching transistor that performs switching according to a control voltage, a rectifying element that performs rectification when the switching transistor is off, an inductor that is charged by an input voltage when the switching transistor is on, A voltage comparison is made between the voltage at the connection point between the switching transistor and the inductor and a reference voltage which means that the excitation energy of the inductor is zero or small, and a state detection signal is output as a binary signal as the comparison result A first voltage comparison circuit; a first constant voltage circuit that generates a first constant voltage; a second constant voltage circuit that generates a second constant voltage higher than the first constant voltage; A feedback circuit unit comprising a feedback resistor unit for converting the output voltage of the output terminal into a feedback voltage; A second voltage comparison circuit that performs voltage comparison with a reference voltage and generates and outputs a binary signal indicating the comparison result; and controls the switching transistor so that the feedback voltage and the reference voltage coincide with each other And when the first voltage comparison circuit detects a signal indicating that the excitation energy of the inductor has become zero or small, the first constant voltage operates as a reference voltage for the feedback voltage. When the second voltage comparison circuit detects that the feedback voltage is lower than the reference voltage, the second constant voltage is changed from the second state to the second state where the switching operation is stopped from the first state. When a transition is made to a third state that operates as a reference voltage for the feedback voltage, and the second voltage comparison circuit detects that the feedback voltage is higher than the reference voltage, A state transition control circuit for shifting to the first state from the third state, characterized by having a.

According to the present invention, by switching the reference voltage for the feedback voltage from the first constant voltage to the second constant voltage, the feedback voltage is made to follow the reference voltage, and the ripple of the output voltage is controlled. The power consumption efficiency at light load can be further improved.
Further, since it is possible to prevent the ripple of the output voltage from becoming excessive, it is possible to reduce noise caused by the ripple, and thus suppress damage to the circuit.

1 is a circuit diagram of a switching regulator according to Embodiment 1 of the present invention. FIG. 2 is a flowchart showing the operation timing of the switching regulator shown in FIG. FIG. 3 is a circuit diagram of a switching regulator according to Embodiment 2 of the present invention. FIG. 4 is a frequency characteristic diagram of a feedback circuit unit including a feedback resistor. FIG. 5 is a circuit diagram showing a detailed circuit configuration of the comparator and the error amplifier circuit shown in FIG. FIG. 6 is a timing chart for explaining a problem when the voltage at the inverting input terminal of the comparator 11 is higher than the second constant voltage. FIG. 7 is an explanatory diagram showing a state in which the voltage at the inverting input terminal of the comparator 11 is set lower than the second constant voltage in order to ensure the state transition. FIG. 8 is a circuit diagram of a switching regulator according to the third embodiment of the present invention. FIG. 9 is a circuit diagram of a switching regulator according to Embodiment 4 of the present invention. FIG. 10 is a circuit diagram showing an example of a conventional switching regulator. FIG. 11 is a waveform diagram schematically showing the relationship between the ripple of the output voltage and the inductor current. FIG. 12 is a waveform diagram schematically showing the relationship between the ripple of the output voltage smaller than the output voltage shown in FIG. 11 and the inductor current. FIG. 13 is a waveform diagram schematically showing the relationship between the ripple of the output voltage of the inductor smaller than the inductor shown in FIG. 10 and the inductor current.

Example 1
FIG. 1 shows a circuit diagram of a step-down current mode switching regulator according to a first embodiment of the present invention.
The switching regulator includes a switching transistor M1, a rectifying element M2, an inductor L1, an output capacitor (smoothing capacitor) Co, a PWM control circuit 10, a feedback circuit unit including feedback resistors R1 and R2, and a comparator 11. And an error amplifier 12.

The switching regulator monitors the drain voltage LXV of the phase compensation circuit 13 including the series circuit of the resistor R3 and the capacitor C3, the state transition circuit 14, and the rectifier element M2, and the current IL of the inductor L1 becomes positive. A comparison circuit 15 for detecting this, a switch SW2 opened by the state 2, and a switch SW3 switched by the state 3.

  Furthermore, this switching regulator outputs the load current Iout toward the load 120 according to the output voltage Vout, the current source Iref1, the resistor R4, the constant voltage circuit E1, the input terminal IN to which the input voltage Vin is applied, and the output voltage Vout. It also has a terminal OUT.

The feedback circuit section divides the output voltage Vout by the feedback resistors R1 and R2 and converts it to the feedback voltage FB. The feedback voltage FB is obtained by the following equation, where the output voltage is Vout and the resistance values are R1 and R.
Feedback voltage FB = Vout × R2 / (R1 + R2)
The gate of the switching transistor M1 is connected to the P terminal of the PWM control circuit 10, and is turned on / off by the control voltage PHS to perform a switching operation.

The rectifying element M2 is constituted by a synchronous rectification transistor (MOSFET) for preventing reverse current, and the gate of the synchronous rectification transistor is connected to the N terminal of the PWM control circuit 10, and is switched on / off by a control voltage NLS to perform a switching operation. .

The comparator circuit 15 is composed of a comparator 15 ′ and an AND circuit 15 ″, and the drain voltage LXV at the connection point LX of the switching transistor M1 and the rectifier M2 is input to the non-inverting input terminal + of the comparator 15 ′. The reference voltage Vref3 of the constant voltage circuit E2 is input to the inverting input terminal − of the device 15 ′.

When the drain voltage LXV is higher than the reference voltage Vref3, the comparator 15 ′ outputs a high level signal to one input terminal of the AND circuit 15 ″. The control voltage PHS is applied to the other input terminal of the AND circuit 15 ″. And the AND circuit 15 ″ outputs a high level state detection signal LVLX as a binary signal to the state transition circuit 14 when a high level signal is input to both of its input terminals.

The AND circuit 15 ″ outputs a low level state detection signal LVLX to the state transition circuit 14 when the control voltage PHS is low level.
The inductor current IL of the inductor L1 when the state detection signal LVLX is at the high level becomes the inductor current IL = Vref3 / Ronm2 when the on-resistance of the rectifying element M2 is Ronm2.

Normally, the comparator 15 has a delay time, and the reference voltage Vref3 is set to a voltage slightly lower than 0V so that the inductor current IL does not become 0 or less (so as not to flow in the reverse direction). Usually, since the on-resistance Ronm2 is very small, the reference voltage Vref3 is required to have high accuracy. The reference voltage Vref3 means that the excitation energy of the inductor L1 is zero or small. The constant voltage circuit E2 is composed of a constant voltage source inside the IC.

The comparison circuit 15 compares the drain voltage LXV at the connection point LX between the switching transistor M1 and the inductor L1 with the reference voltage Vref3 and outputs a state detection signal LVLX as a comparison result toward the state transition circuit 14. 1 functions as a voltage comparison circuit.

The feedback voltage FB is input to the non-inverting input terminal + of the comparator 11, and the reference voltage Vref used to control the fluctuation of the ripple voltage is input to the inverting input terminal of the comparator 11. As the reference voltage Vref, a first constant voltage Vref1 and a second constant voltage Vref2 are used. The first constant voltage Vref1 is generated by a constant voltage circuit E1, and the constant voltage circuit E1 is also composed of a constant voltage source inside the IC.

The second constant voltage Vref2 is generated by a constant current source Iref1, a resistor R4, and a constant voltage circuit E1. The second constant voltage Vref2 is higher than the first constant voltage Vref1 by a voltage generated by the constant current source Iref1 and the resistor R4.

The reference voltage Vref is input to the non-inverting input terminal + of the error amplifier 12, and the feedback voltage FB is input to the inverting input terminal of the error amplifier 12. The reference voltage Vref is switched between the first constant voltage Vref1 and the second constant voltage Vref2 by the switch SW3.

The switch SW3 is switched by a state transition circuit 14 having a function described later. That is, when the switch SW3 is in the state 1, the first constant voltage Vref1 is applied to the inverting input terminal − of the comparator 11 and the non-inverting input terminal + of the error amplifier 12; Switching is performed by a state 3 transition signal output from the state transition circuit 14 so that the voltage Vref2 is applied.

The comparator 11 outputs the comparison output voltage cmpout toward the state transition circuit 14, and the error amplifier 12 outputs the error voltage opout toward the phase compensation circuit 13 and the PWM control circuit 10 via the switch SW2. The comparator 11 cooperates with the error amplifier 12 to function as a second voltage comparison circuit that performs voltage comparison between the feedback voltage FB and the reference voltage Vref to generate and output a binary signal indicating the comparison result. .

The switch SW2 is closed by the state 1 transition signal and the state 3 transition signal output from the state transition circuit 14 in the state 1 and state 3, and the state 2 output from the state transition circuit 14 in the state 2 Opened by a transition signal.

The P terminal of the PWM control circuit 10 is connected to the gate of the switching transistor M1. The N terminal of the PWM control circuit 10 is connected to the gate of the rectifying element M2. The control voltage PHS is input to the gate of the switching transistor M1, and the control voltage NLS is input to the gate of the rectifying element M2.

The switching transistor M1 is a P-channel transistor, which is turned off when the control voltage PHS is at a high level and turned on when the control voltage PHS is at a low level.
The rectifying element M2 is an N-channel transistor, and is turned on when the control voltage NLS is at a high level and turned off when the control voltage NLS is at a low level.

The state transition circuit 14 outputs a state 1 transition signal when the comparison output voltage cmpout is at a low level, and outputs a state 2 transition signal when the state detection signal LVLX of the comparison circuit 15 is at a high level, so that the comparison output voltage cmpout is When the level is high, a state 3 transition signal is output.

The comparator 11 compares the feedback voltage FB with the first constant voltage Vref1 as the reference voltage Vref, and when the feedback voltage FB is higher than the first constant voltage Vref1, the low-level comparison output voltage cmpout is used as a state transition circuit. 14 and outputs a high-level comparison output voltage cmpout to the state transition circuit 14 when the feedback voltage FB is lower than the reference voltage Vref.

The phase compensation circuit 13 controls the PWM control circuit 10 following the first constant voltage Vref1 as the reference voltage Vref in the state 1, and becomes a high impedance in the state 2 and holds a constant voltage.
The operation of the switching regulator shown in FIG. 1 will be described with reference to the timing chart shown in FIG.

FIG. 2 shows the operation of the switching regulator in a light load state where the load 120 is small (light) and the inductor current IL is in the intermittent mode.
When the control voltage PHS is low level and the drain voltage LXV at the connection point LX is lower than the reference voltage, or when the control voltage PHS is high level and the drain voltage LXV at the connection point LX is lower than the reference voltage Vref3, the state detection signal LVLX is Low level.

Further, when the control voltage PHS is at a high level and the drain voltage LXV at the connection point LX is equal to or higher than the reference voltage Vref3, the state detection signal LVLX is assumed that the excitation energy stored in the inductor L1 is zero or small. Becomes high level.

Since the error amplifier 12 integrates the difference between the feedback voltage FB and the reference voltage Vref and controls the PWM control circuit 10 with the error voltage opout, the feedback voltage FB is converged to the reference voltage Vref. Therefore, Vout = {(R1 + R2) / R2} × Vref.
The state transition circuit 14 performs state transition control according to the conditions described below.

(State 1)
In the state 1, the switch SW2 is closed, and the switch SW3 applies the first constant voltage Vref1 as the reference voltage Vref to the inverting input terminal − of the comparator 11 and to the non-inverting input terminal + of the error amplifier 12. Connected to the side.

In this state 1, the PWM control circuit 10 controls the control voltages PHS, NLS (FIG. 2 (FIG. 2)) according to the error voltage opout (see FIG. 2 (i)) so that the feedback voltage FB converges to the first constant voltage Vref1. a) and (b) are controlled.

As a result, the switching transistor M1 and the commutator M2 are turned on / off, the output voltage Vout (see FIG. 2 (f)) changes according to the error voltage opout, and a normal PWM operation is performed with a heavy load.

In this state 1, when the inductor current IL becomes small (see time t1 in FIG. 2 (e)) and the drain voltage LXV becomes larger than the reference voltage Vref3 (see FIG. 2 (c)), the state detection signal LVLX becomes high level. It becomes. Thereby, the state transition circuit 14 outputs a high-level state 2 transition signal (see FIG. 2 (k)).

Since the state detection signal LVLX becomes high level only when the inductor current IL becomes sufficiently small, the state 1 is continuously maintained in a heavy load state. In state 2, the switch SW2 is opened, the control voltage PHS is at a high level, the control voltage NLS is at a low level, and the switching operation is stopped. That is, the switching regulator is in a shutdown mode (sleep mode).

At this time, since the circuits other than those constituting the comparator 11 and the error amplifier 12 can be shut down, the current consumption of the switching regulator can be greatly reduced.

In the state 2, when the feedback voltage FB becomes equal to or lower than the reference voltage Vref which is the first constant voltage Vref1 (see time point t2 in FIG. 2G), the comparison output voltage compout becomes high level (FIG. 2H). reference). As a result, the state transition circuit 14 outputs a high-level state 3 transition signal (see FIG. 2 (l)).

Thereby, the switch SW3 is connected to the side of applying the second constant voltage Vref2 as the reference voltage Vref to the inverting input terminal − of the comparator 11 and applying it to the non-inverting input terminal + of the error amplifier 12. Further, the switch SW2 is closed.

Since the second constant voltage Vref2 is set higher than the first constant voltage Vref1, the feedback voltage FB is lower than the reference voltage Vref, but the voltage difference between the feedback voltage FB and the reference voltage Vref is eliminated. The error amplifier 12 controls the PWM control circuit 10.

As a result, the output voltage Vout rises and a ripple voltage is generated. When the feedback voltage Vout becomes higher than the reference voltage Vref, which is the second constant voltage Vref2 (see time t3 in FIG. 2G), the comparison output voltage mpout of the comparator 11 is inverted and becomes a low level (FIG. 2 (l)).

When the comparison output voltage mpout voltage becomes low level, the state transition circuit 14 outputs a state 1 transition signal, and the switching regulator executes a sequence operation of state 1 → state 2 → state 3 when the load is light.

As a result, the feedback voltage FB is caused to follow the change of the reference voltage Vref, and a stable ripple voltage of the output voltage Vout is generated. At this time, the ripple voltage of the output voltage Vout depends on the resistance value of the feedback circuit section.
ΔVout = (R1 + R2) / R2 × (Vref2−Vref1)
It is expressed by the following formula. That is, a ripple voltage obtained by multiplying the ripple voltage of the reference voltage Vref by {(R1 + R2) / R2}.

In the state 1, the phase compensation circuit 13 controls the PWM control circuit 10 so as to follow the reference voltage Vref as the reference constant voltage Vref1. In state 2, since it is disconnected from the error amplifier 12 and becomes a high impedance state, the voltage is held. In the state 3, the PWM control circuit 10 is controlled so as to follow the reference voltage Vref as the standard constant voltage Vref2.

Thus, in the first embodiment, the ripple voltage of the output voltage Vout can be controlled according to the reference voltage Vref, and the current consumption can be greatly reduced.

(Example 2)
FIG. 3 shows a circuit diagram of the step-down switching regulator of the second embodiment.
In FIG. 3, a speed-up capacitor Cspd is connected in parallel to the resistor R1 of the feedback circuit section of the switching regulator shown in FIG.

Further, instead of the rectifying element M2 made of a transistor, a rectifying element M2 made of a diode D2 is used. Further, the comparison output voltage cmpout of the comparator 11 is generated from the output of the error amplifier 12. The circuit configuration of the error amplifier 12 will be described later.

The speed-up capacitor Cspd is used to pass through the high frequency component of the feedback circuit unit. FIG. 4 shows the frequency characteristics of the feedback circuit section using the speed-up capacitor Cspd. A curved line Q1 indicated by a broken line indicates a phase characteristic, and a curved line Q2 indicated by a solid line indicates a gain characteristic.

This frequency characteristic is when the resistance R1 = 5.25 kΩ, the resistance R2 = 1.0 kΩ, and the speed-up capacitor Cspd = 6.8 nF, with a zero point in the low band and a peak in the high band. The gain after the peak frequency is 0DB. Note that ((1.00E + 0i); sign i is a positive integer) means a natural constant E raised to the power of i.

That is, this frequency characteristic indicates that the input signal is passed through by a factor of 1. Therefore, the ripple voltage ΔVout of the output voltage Vout is changed to the change voltage of the reference voltage Vref by arranging the peak of the high frequency in the frequency characteristic where the ripple of the output voltage Vout is generated, that is, the frequency characteristic of the switching regulator. ΔVref, that is, ΔVout = ΔVref = Vref2−Vref1.

Since the rectifying element M2 is constituted by the diode D2, when the inductor current IL becomes 0 in the current discontinuous mode, the drain voltage (cathode voltage) LXV at the connection point LX follows the output voltage Vout.

Therefore, if the reference voltage Vref3 is set to a voltage lower than the output voltage Vout and higher than the ground voltage GND, it can be detected that the load current Iout becomes 0, and a transistor is used as the rectifying element M2. Compared to this, the reference voltage Vref3 can be generated relatively easily.

As shown in FIG. 5, the error amplifier 12 includes P-channel transistors P1, P2, and P3, differential pair P-channel transistors, and N-channel transistors N1, N2, N3, N4, N5, and N7. The P-channel transistors P1, P2, and P3 have the same gate length and gate width, and the differential pair P4 and P5 have the same gate length and gate width.

N-channel transistors N1, N2, N3, N4, N5 and N7 have the same gate length. The gate widths of the N-channel transistors N1, N2, N3, and N4 are the same. The gate widths of the N-channel transistors N5 and N7 are set so that the gate width of the N-channel transistor N5 and the gate width of the N-channel transistor N7 is equal to the gate width of the N-channel transistor N1. It is configured.

The N-channel transistor N6 is configured with a minimum gate length allowed in manufacturing, and can be regarded as a switch that is turned on / off by a threshold voltage. In general, since the threshold voltage of a transistor has a manufacturing error, the output of the error amplifier 12 has a differential offset voltage. The largest cause is the offset of the threshold voltage of the differential pair P-channel transistors P4 and P5, and a differential offset voltage is generated at the inverting voltage terminal by the offset of the threshold voltage.

The offsets of the P-channel transistors P1, P2, N-channel transistors N1, N2, N3, N4 also affect the differential offset voltage of the output of the error amplifier 12, but compared to the differential pair P-channel transistors P4, P5. small.

As a result, there is a difference between the feedback voltage FB and the reference voltage Vref, but the reference voltage Vref is generally trimmed in anticipation of the differential offset voltage so that the feedback voltage FB becomes a desired value. Therefore, it is rarely a problem.

Further, in the error amplifier 12 shown in FIG. 5, since the output of the error amplifier 12 and the output of the comparator 11 are generated by the same differential pair P-channel transistors P4 and P5, a differential offset voltage is generated. Since it is only affected by the offset of the channel transistors P2, P3, N channel transistors N4, N5, N7, the error can be minimized.

On the other hand, when the error amplifier 12 and the comparator 11 are made separately, the reference voltage Vref is trimmed in anticipation of the differential offset so that the feedback voltage FB becomes a desired value. Only the differential offset of the amplifier 12 is included, and the inverted voltage of the comparator 11 is shifted by the difference of the differential offset.

For example, if the operating offset error voltage of the error amplifier 12 is ± 30 mV and the error voltage of the comparator 11 is ± 50 mV, the error voltage will deviate by a maximum of ± 80 mV from the desired value of the feedback voltage FB. In that case, the ripple of the output voltage Vout by the state transition circuit 14 has a very large variation.

With reference to FIG. 6, it will be described that a problem may occur even when the differential offset voltage is minimized when the state transition circuit 14 is in a state of outputting a state 3 transition signal. FIG. 6 is drawn assuming that the voltage applied to the inverting input terminal − for inverting the comparison output voltage cmpout of the comparator 11 is slightly higher than the voltage at the inverting input terminal − of the error amplifier 12.

In FIG. 6, the voltage 1 applied to the inverting input terminal of the comparator 11 with respect to the first constant voltage Vref1 is higher than the first constant voltage Vref1, and with respect to the second constant voltage Vref2. Thus, the voltage 2 applied to the inverting input terminal of the comparator 11 is higher than the second constant voltage Vref2.

In the state 1, when the feedback voltage FB becomes smaller than the voltage 1, the comparison output voltage cmpout of the comparator 11 is inverted. However, in the state 3, the feedback voltage FB converges to the second constant voltage Vref2 as the reference voltage Vref due to the error voltage opout of the error amplifier 12, but the voltage 2 at the inverting input terminal of the comparator 11 is the second voltage. 2 is higher than the reference voltage Vref which is a constant voltage Vref2.

Therefore, in the state 3, the feedback voltage FB cannot be higher than the voltage 2, the comparison output voltage cmpout is not inverted, and as a result, the state 1 transition signal is not output, and the feedback voltage FB is the second voltage. The constant voltage Vref2 remains converged.

In the comparator 11 and the error amplifying circuit 12 shown in FIG. 5, when the output of the comparator 11 is at a high level, the switching N-channel transistor N6 is in an on state, so that the output of the comparator 11 changes from a high level to a low level. The output of the comparator 11 when reaching the level and the output of the error amplifier 12 substantially coincide.

When the output of the comparator 11 is at a low level, the switching N-channel transistor N6 is in an OFF state, so that the comparison output voltage cmpout of the comparator 11 is output from the N-channel transistor N5 smaller than the N-channel transistor N4. The feedback voltage FB that is inverted from the level to the high level is designed to be lower than the reference voltage Vref.

As a result, in the state 1 and the state 2, the voltage 1 applied to the inverting input terminal of the comparator 11 with respect to the first constant voltage Vref1 is higher than the first constant voltage Vref1. In the state 3, as shown in FIG. 7, the voltage 2 applied to the inverting input terminal of the comparator 11 with respect to the second constant voltage Vref2 is lower than the second constant voltage Vref2.

Therefore, as shown in FIG. 7, the feedback voltage FB becomes higher than the voltage 2, the comparison output voltage cmpout is inverted, and the state 1 transition signal is always output.
As described above, in the second embodiment, similarly to the first embodiment, light load detection can be easily performed. Further, the fluctuation of the ripple voltage of the output voltage Vout can be changed according to the reference voltage Vref. Further, it is possible to avoid problems caused by the differential offset between the comparator 11 and the error amplifier 12.

(Example 3)
FIG. 8 is a diagram illustrating a circuit of the step-up switching regulator according to the third embodiment of the present invention. The switching regulator shown in FIG. 8 can perform the same circuit operation as that of the step-down switching regulator shown in FIG. 3 using the step-up switching regulator.

Since the configuration of the switching transistor M1, the inductor L1, and the diode D3 is only different from that of the step-down switching regulator shown in FIG. 3, only the connection relationship is shown and a detailed description is omitted.

(Example 4)
FIG. 9 is a diagram illustrating a circuit of a polarity inversion switching regulator according to the fourth embodiment of the present invention. The switching regulator shown in FIG. 9 is configured such that a circuit operation similar to that of the step-down switching regulator shown in FIG. 3 can be performed using a polarity inversion switching regulator.

Since only the connection relationship between the rectifier element (diode D2) and the inductor L1 is different from that of the step-down switching regulator shown in FIG. 3, only the connection relationship is shown and detailed description is omitted.

(Effect of Example)
According to these embodiments, the reference voltage Vref of the feedback voltage FB is switched from the first constant voltage Vref1 to the second constant voltage Vref2. As a result, the feedback voltage FB follows the reference voltage Vref, and the ripple voltage of the output voltage Vout is controlled by the voltage difference between the first constant voltage Vref1 and the second constant voltage Vref2. For this reason, the ripple fluctuation of the output voltage Vout can be suppressed without impairing the power consumption efficiency at the time of light load, and it is effective for noise countermeasures and the like.

In addition, according to the second to fourth embodiments, since the speed-up capacitor Cspd is used, the output voltage Vout can follow the reference voltage Vref regardless of the circuit constant of the feedback circuit section.
Further, by keeping the voltage of the capacitor C3 of the phase compensation circuit 13 connected to the output terminal of the error amplifier 12 constant in the second state, the operating point in the first state is preserved. As a result, it is possible to converge to the result of connecting the operation of the first state and the operation of the third state of the switching regulator.

By disconnecting the capacitor C3 of the phase compensation circuit 13 from the circuit, the voltage of the phase compensation capacitor of the error amplifier 12 can be kept constant in the second state.
In the second state, by setting an unnecessary circuit to the sleep mode, the self-consumption of the switching regulator can be further reduced, and the power consumption efficiency can be improved.

By using the error voltage opout of the error amplifier 12 as the second comparison circuit, the ripple voltage due to the difference in the reference voltage Vref can be accurately generated.
The second voltage comparison circuit has an offset, and from the third state to the first state by detecting that the feedback voltage FB is higher than the reference voltage Vref in the third state by a voltage lower by the offset. You can always make a transition.

By using the rectifier element M2 as a MOSFET that performs control for preventing a reverse current, the efficiency at a heavy load can be improved while the efficiency at a heavy load is improved.
When the rectifying element M2 is the diode D2, the excitation energy is zero or light by detecting that the cathode voltage of the diode D2 becomes a positive voltage following the output voltage Vout of the output terminal OUT in the current discontinuous mode. It can be detected.

Since the control method is the current mode, the feedback voltage FB can follow the second constant voltage Vref2 without overshoot.

The present invention is applicable to an electronic circuit that is driven by PWM control.

10 ... PWM control circuit (control circuit part)
11: Comparator (second voltage comparison circuit)
12: Error amplification circuit (second voltage comparison circuit)
14: State transition circuit 15: First voltage comparison circuit
L1… Inductor
IL: Inductor current
Vref3 ... reference voltage
LVLX ... Status detection signal
Vref1 ... First constant voltage
Vref2 ... Second constant voltage
Vref… Reference voltage
FB: Feedback voltage

JP 2010-259257 A

Claims (10)

In the switching regulator that converts the input voltage input to the input terminal into a predetermined output voltage and outputs the load current from the output terminal.
A switching transistor that performs switching according to a control voltage, a rectifier that performs rectification when the switching transistor is turned off, an inductor that is charged by the input voltage when the switching transistor is turned on, and the switching transistor and the inductor A first voltage comparison circuit that compares the voltage at the connection point with a reference voltage that means that the excitation energy of the inductor is zero or small, and outputs a state detection signal as a binary signal as the comparison result; A first constant voltage circuit that generates a first constant voltage, a second constant voltage circuit that generates a second constant voltage higher than the first constant voltage, and an output voltage of the output terminal is fed back The comparison result obtained by performing a voltage comparison between the feedback circuit and the reference voltage, and a feedback circuit unit composed of a feedback resistor that converts the voltage into a voltage A second voltage comparison circuit that generates and outputs a binary signal, a control circuit unit that controls the switching transistor so that the feedback voltage and the reference voltage match, and the first voltage comparison circuit When a signal indicating that the excitation energy of the inductor is zero or small is detected, a transition is made from a first state in which the first constant voltage is used as a reference voltage for the feedback voltage to a second state in which the switching operation is stopped. And when the second voltage comparison circuit detects that the feedback voltage is lower than the reference voltage, the second state operates from the second state using the second constant voltage as the reference voltage of the feedback voltage. And when the second voltage comparison circuit detects that the feedback voltage is higher than the reference voltage, the state transitions from the third state to the first state. Switching regulator comprising: the state transition control circuit, the causing. 2. The feedback circuit unit according to claim 1, wherein the feedback circuit unit includes a feedback resistor that converts the output voltage into the feedback voltage, and a speed-up capacitor that passes a high frequency component of the output voltage as the feedback voltage. Switching regulator. The second voltage comparison circuit includes an error amplifier that operates to converge a difference between the feedback voltage and the reference voltage, and maintains an error signal of the error amplifier constant in the second state. The switching regulator according to claim 1 or 2. The output terminal of the error amplifier is connected to a phase compensation circuit, the phase compensation circuit including a capacitor, and in the state 2, the capacitor is disconnected from the error amplifier in order to keep the voltage of the capacitor constant. The switching regulator according to claim 3. 5. The switching regulator according to claim 1, wherein at least the control circuit unit is set in a sleep mode in the second state. 6. The second voltage comparison circuit has an offset voltage, and detects that the feedback voltage is higher than the reference voltage in the third state with a voltage lower by the offset voltage. The switching regulator according to any one of claims 1 to 5. The switching regulator according to claim 1, wherein the rectifying element is a MOSFET that performs control for preventing a backflow current. The rectifying element is a diode, and the first voltage comparison circuit detects a signal indicating that the excitation energy is zero or light by detecting that the cathode voltage of the diode becomes a positive voltage. The switching regulator according to any one of claims 1 to 6, wherein the switching regulator is characterized in that: The switching regulator according to claim 1, wherein the switching regulator is controlled in a current mode. The reference voltage to be compared with the feedback voltage of the output voltage is switched between the first constant voltage and the second constant voltage higher than the first constant voltage, and the feedback voltage is compared with the first constant voltage. A first step of setting the control circuit unit that performs switching control of the inductor current flowing through the inductor to the first state;
A second step of detecting that an inductor current flowing through the inductor is zero or small when the control circuit unit is in the first state and setting the control circuit unit to a second state which is a sleep state;
When the control circuit unit is in the second state, the feedback voltage is compared with the first constant voltage, and when the feedback voltage is lower than the first constant voltage, the reference voltage is set to the first constant voltage. The reference voltage is set when the control circuit unit for switching the inductor current by switching from the constant voltage to the second constant voltage is set to the third state and the feedback voltage becomes higher than the second constant voltage. And switching the second constant voltage to the first constant voltage to repeat the third step of setting the control circuit unit to the first state.