CN204480101U - A kind of low pressure difference linear voltage regulator of quick response - Google Patents
A kind of low pressure difference linear voltage regulator of quick response Download PDFInfo
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- CN204480101U CN204480101U CN201520182059.7U CN201520182059U CN204480101U CN 204480101 U CN204480101 U CN 204480101U CN 201520182059 U CN201520182059 U CN 201520182059U CN 204480101 U CN204480101 U CN 204480101U
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- pmos
- reference voltage
- operational amplifier
- vbn
- resistance string
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Abstract
The utility model relates to a kind of low pressure difference linear voltage regulator of quick response, comprise band-gap reference, operational amplifier, feedback resistance string and power tube, band-gap reference is for generation of reference voltage V ref and input to the negative input of operational amplifier, feedback resistance series winding is connected to the positive input of operational amplifier, the drain terminal of one termination power tube of feedback resistance string, the other end ground connection of feedback resistance string, the source of power tube meets V
dDpower supply, the output terminal of the grid termination operational amplifier of power tube, also comprise reference voltage generating circuit, NMOS tube M1 and PMOS M2, the input end of reference voltage generating circuit connects band-gap reference, reference voltage generating circuit generating reference voltage vbn and reference voltage vbp.The utility model solves the high technical matters of existing low pressure difference linear voltage regulator LDO power consumption, and the utility model, by increasing part auxiliary circuit, avoids excessive pressure drop and overshoot.
Description
Technical field
The utility model relates to a kind of low pressure difference linear voltage regulator LDO of quick response.
Background technology
General LDO is made up of band-gap reference, operational amplifier, feedback resistance string and Modulating Power pipe 14 pipe.Band-gap reference produces the reference voltage V ref for comparing; Feedback resistance string determines feedback factor; The grid voltage of operational amplifier Modulating Power pipe 14 pipe,
Make feedback voltage Vfb=Vref=Vout*R2/ (R1+R2).
So output voltage Vout=Vref* (the R1+R2)/R2 of LDO.Improved the response speed of LDO by the quiescent current Iq increasing operational amplifier, thus reduce pressure drop and the overshoot of LDO output, and accelerate the resume speed of LDO output voltage.Although this way can avoid the output of LDO to have large pressure drop and large overshoot; And accelerate LDO exports pressure drop and large overshoot response speed to it; But but increase the power consumption of LDO.
Summary of the invention
In order to solve the high technical matters of existing low pressure difference linear voltage regulator LDO power consumption, the utility model provides a kind of low pressure difference linear voltage regulator LDO of quick response.
Technical solution of the present utility model:
A kind of low pressure difference linear voltage regulator of quick response, comprise band-gap reference 16, operational amplifier 13, feedback resistance string 15 and power tube 14, described band-gap reference is for generation of reference voltage V ref and input to the negative input of operational amplifier 13, described feedback resistance string 15 is connected to the positive input of operational amplifier, the drain terminal of one termination power tube 14 of described feedback resistance string 15, the other end ground connection of described feedback resistance string 15, the source of described power tube 14 meets V
dDpower supply, the output terminal of the grid termination operational amplifier of described power tube 14, it is characterized in that: also comprise reference voltage generating circuit 10, NMOS tube M1 and PMOS M2, the input end of described reference voltage generating circuit 10 connects band-gap reference, described reference voltage generating circuit 10 generating reference voltage vbn and reference voltage vbp, reference voltage vbn is connected to the grid end of NMOS tube M1, and reference voltage vbp is connected to the grid end of PMOS M2, and the drain terminal of described NMOS tube M1 meets V
dDpower supply, the source of described NMOS tube M1 is connected with the source of PMOS M2, the drain terminal ground connection of described PMOS M2.
Vbn=Vout+Vthn+ △ V, vbp=Vout-Vthp-△ V, Vthn is the threshold voltage of NMOS tube M1, and Vthp is the threshold voltage of PMOS M2;
The condition that wherein △ V will meet is:
As Vout-Vout2> △ V, then NMOS tube M1 opens;
As Vout3-Vout> △ V, then PMOS M2 opens,
Vout2 is the voltage drop value of output voltage Vout, and Vout3 is the overshoot value of output voltage Vout.
Above-mentioned reference voltage generating circuit 10 comprises vbn generative circuit and vbp generative circuit, described vbn generative circuit comprises the first operational amplifier 22, PMOS M3 and the first divider resistance string 21, the negative input of described first operational amplifier 22 connects band-gap reference, the positive input of described first operational amplifier 22 connects the feedback voltage Vfb 2 of divider resistance string 21 output, the grid end of the output termination PMOS M3 of described first operational amplifier 22, the source of described PMOS M3 meets V
dDpower supply, the drain terminal of described PMOS M3 connects one end of the first divider resistance string 21, described first divider resistance string 21 other end ground connection, the drain terminal output reference voltage vbn of described PMOS M3,
Described vbp generative circuit structure is identical with vbn generative circuit structure, and vbp generative circuit comprises the second operational amplifier 32, PMOS M4 and the second divider resistance string 31.
Divider resistance string 21 in above-mentioned vbn generative circuit comprises the resistance R4 and variable resistor R3 that connect successively, and the resistance of described variable resistor R3 meets: Vref=vbn*R4/ (R3+R4);
Identical with vbn generative circuit, the second divider resistance string 31 in vbp generative circuit comprises the resistance R5 and variable resistor R6 that connect successively, and the resistance of described variable resistor R6 meets: Vref=vbp*R5/ (R6+R5).
The advantage that the utility model has:
1, the utility model is by increasing part auxiliary circuit (reference voltage generating circuit 10, NMOS tube M1 and PMOS M2), avoids excessive pressure drop and overshoot.
2, the utility model does not increase the power consumption of operational amplifier.When the lower Iq of operational amplifier, obtain response speed faster.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of existing low pressure difference linear voltage regulator;
Fig. 2 is the circuit structure diagram of the utility model low pressure difference linear voltage regulator;
Fig. 3 is the vbn generative circuit structural drawing of reference voltage generating circuit;
Fig. 4 is the vbp generative circuit structural drawing of reference voltage generating circuit.
Embodiment
The utility model adds reference voltage generating circuit on original basis, a NMOS tube M1, and a PMOS, M2.The threshold voltage of NMOS tube M1 is the threshold voltage of Vthn, PMOS M2 is Vthp.Reference voltage generating circuit 10 produces reference voltage vbn and vbp.Wherein vbn=Vout+Vthn+ △ V, vbp=Vout-Vthp-△ V; △ V is can the value of trim, can need adjustment according to application.
During normal work, operational amplifier, by the grid voltage of Modulating Power pipe 14, ensures Vref=Vfb=vout*R2/ (R1+R2), thus ensures Vout=Vref* (R1+R2)/R2; The value stabilization of Vout is adjusted by the loop of operational amplifier 13, divider resistance string 15 and power tube 14 composition.
If the output voltage Vout of LDO has a pressure drop to become Vout2, as voltage drop value Vout-Vout2> △ V, NMOS tube M1 will open, V
dDcan be charged to Vout by NMOS tube M1, accelerate the resume speed of Vout and reduce the voltage drop value of Vout.
If the output voltage Vout of LDO has an overshoot to become Vout3, as overshoot value Vout3-Vout> △ V, PMOS M2 will open, and Vout can discharge into ground gnd by PMOS 12, accelerates the resume speed of Vout and reduces the overshoot value of Vout.
Fig. 3, Fig. 4 are a kind of ways of realization of reference voltage generating circuit.Amplifier ensures feedback voltage Vfb 2=Vref=vbn*R4/ (R3+R4) by the grid voltage adjusting PMOS M3; By the loop of the first operational amplifier 22, PMOS M3 and the first divider resistance string 21 composition, be finally export vbn=Vref* (R3+R4)/R4.R3 in feedback resistance string be can trim adjustment resistance, suitable vbn magnitude of voltage can be obtained by trim R3.Vbp with the circuit the same with generating vbn, can obtain suitable vbp magnitude of voltage by the value arranging different R5 and R6.
Identical with vbn generative circuit, the second divider resistance string 31 in vbp generative circuit comprises the resistance R5 and variable resistor R6 that connect successively, and the second operational amplifier 32 adjusts the grid voltage of PMOS M4 to ensure feedback voltage Vfb 3=Vref=vbp*R5/ (R6+R5); By the loop of the second operational amplifier 22, PMOS M4 and the second divider resistance string 21 composition, be finally export vbp=Vref* (R6+R5)/R5.
Claims (4)
1. the low pressure difference linear voltage regulator responded fast, comprise band-gap reference (16), operational amplifier (13), feedback resistance string (15) and power tube (14), described band-gap reference is for generation of reference voltage V ref and input to the negative input of operational amplifier (13), described feedback resistance string (15) is connected to the positive input of operational amplifier, the drain terminal of one termination power tube (14) of described feedback resistance string (15), the other end ground connection of described feedback resistance string (15), the source of described power tube (14) meets V
dDpower supply, the output terminal of the grid termination operational amplifier of described power tube (14), it is characterized in that: also comprise reference voltage generating circuit (10), NMOS tube M1 and PMOS M2, the input end of described reference voltage generating circuit (10) connects band-gap reference, described reference voltage generating circuit (10) generating reference voltage vbn and reference voltage vbp, reference voltage vbn is connected to the grid end of NMOS tube M1, reference voltage vbp is connected to the grid end of PMOS M2, and the drain terminal of described NMOS tube M1 meets V
dDpower supply, the source of described NMOS tube M1 is connected with the source of PMOS M2, the drain terminal ground connection of described PMOS M2.
2. the low pressure difference linear voltage regulator of quick response according to claim 1, is characterized in that:
Vbn=Vout+Vthn+ △ V, vbp=Vout-Vthp-△ V, Vthn is the threshold voltage of NMOS tube M1, and Vthp is the threshold voltage of PMOS M2;
The condition that wherein △ V will meet is:
As Vout-Vout2> △ V, then NMOS tube M1 opens;
As Vout3-Vout> △ V, then PMOS M2 opens,
Vout2 is the voltage drop value of output voltage Vout, and Vout3 is the overshoot value of output voltage Vout.
3. the low pressure difference linear voltage regulator of quick response according to claim 1 and 2, it is characterized in that: described reference voltage generating circuit (10) comprises vbn generative circuit and vbp generative circuit, described vbn generative circuit comprises the first operational amplifier (22), PMOS M3 and the first divider resistance string (21), the negative input of described first operational amplifier (22) connects band-gap reference, the positive input of described first operational amplifier (22) connects the feedback voltage Vfb 2 that the first divider resistance string (21) exports, the grid end of the output termination PMOS M3 of described first operational amplifier (22), the source of described PMOS M3 meets V
dDpower supply, the drain terminal of described PMOS M3 connects one end of the first divider resistance string (21), described first divider resistance string (21) other end ground connection, the drain terminal output reference voltage vbn of described PMOS M3,
Described vbp generative circuit structure is identical with vbn generative circuit structure, and vbp generative circuit comprises the second operational amplifier (32), PMOS M4 and the second divider resistance string (31).
4. the low pressure difference linear voltage regulator of quick response according to claim 3, it is characterized in that: the first divider resistance string (21) in described vbn generative circuit comprises the resistance R4 and variable resistor R3 that connect successively, the resistance of described variable resistor R3 meets: Vref=vbn*R4/ (R3+R4);
Identical with vbn generative circuit, the second divider resistance string (31) in vbp generative circuit comprises the resistance R5 and variable resistor R6 that connect successively, and the resistance of described variable resistor R6 meets: Vref=vbp*R5/ (R6+R5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520182059.7U CN204480101U (en) | 2015-03-27 | 2015-03-27 | A kind of low pressure difference linear voltage regulator of quick response |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520182059.7U CN204480101U (en) | 2015-03-27 | 2015-03-27 | A kind of low pressure difference linear voltage regulator of quick response |
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| Publication Number | Publication Date |
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| CN204480101U true CN204480101U (en) | 2015-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520182059.7U Withdrawn - After Issue CN204480101U (en) | 2015-03-27 | 2015-03-27 | A kind of low pressure difference linear voltage regulator of quick response |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104699162A (en) * | 2015-03-27 | 2015-06-10 | 西安华芯半导体有限公司 | Quick-response low-dropout regulator |
| CN109358691A (en) * | 2018-10-17 | 2019-02-19 | 江门市新会区炎泰电子有限公司 | A kind of serial Feedback formula voltage regulator circuit |
| CN109814650A (en) * | 2019-01-23 | 2019-05-28 | 西安交通大学 | A kind of low pressure difference linear voltage regulator clamping transistor structure |
| CN110297515A (en) * | 2018-03-22 | 2019-10-01 | 艾普凌科有限公司 | Voltage regulator |
-
2015
- 2015-03-27 CN CN201520182059.7U patent/CN204480101U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104699162A (en) * | 2015-03-27 | 2015-06-10 | 西安华芯半导体有限公司 | Quick-response low-dropout regulator |
| CN104699162B (en) * | 2015-03-27 | 2016-04-20 | 西安紫光国芯半导体有限公司 | A kind of low pressure difference linear voltage regulator of quick response |
| CN110297515A (en) * | 2018-03-22 | 2019-10-01 | 艾普凌科有限公司 | Voltage regulator |
| CN109358691A (en) * | 2018-10-17 | 2019-02-19 | 江门市新会区炎泰电子有限公司 | A kind of serial Feedback formula voltage regulator circuit |
| CN109814650A (en) * | 2019-01-23 | 2019-05-28 | 西安交通大学 | A kind of low pressure difference linear voltage regulator clamping transistor structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150715 Effective date of abandoning: 20160420 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |