CN204740520U - Stabiliser according to load frequency and output voltage dynamic adjustment bias current - Google Patents
Stabiliser according to load frequency and output voltage dynamic adjustment bias current Download PDFInfo
- Publication number
- CN204740520U CN204740520U CN201520181260.3U CN201520181260U CN204740520U CN 204740520 U CN204740520 U CN 204740520U CN 201520181260 U CN201520181260 U CN 201520181260U CN 204740520 U CN204740520 U CN 204740520U
- Authority
- CN
- China
- Prior art keywords
- circuit
- output voltage
- semiconductor
- oxide
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Amplifiers (AREA)
Abstract
The utility model relates to a stabiliser according to load frequency and output voltage dynamic adjustment bias current, including the band gap benchmark, operational amplifier, feedback resistance cluster and power tube, the band gap benchmark is used for producing reference voltage vref and the negative sense input of input for operational amplifier, the feedback resistance cluster is connected to operational amplifier's positive going input end, the feedback resistance cluster is including the resistance R1 and the resistance R2 that once establish ties, the drain terminal of resistance R1's a termination power tube, resistance R2's other end ground connection, the source termination VDD power of power tube, the bars termination operational amplifier's of power tube output, still include frequency detection circuitry, bias current generating circuit and output voltage detection circuitry, the utility model discloses a solve the present technical problem that the low dropout regulator LDO consumption is high, adopt the utility model discloses a circuit when load digital circuit's frequency is higher, can avoid LDO to have too big pressure drop.
Description
Technical field
The utility model relates to a kind of voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current.
Background technology
General low pressure difference linear voltage regulator (LDO) is made up of band-gap reference, operational amplifier, feedback resistance string and power tube.Band-gap reference produces the reference voltage V ref for comparing; Feedback resistance string determines feedback factor; The grid voltage of operational amplifier power tube,
Make feedback voltage Vfb=Vref=Vout*R2/ (R1+R2).
So output voltage Vout=Vref* (the R1+R2)/R2 of LDO.Improved the response speed of LDO by the quiescent current Iq increasing operational amplifier, thus reduce pressure drop and the overshoot of LDO output, and accelerate the resume speed of LDO output voltage.Although this way can avoid the output of LDO to have large pressure drop and large overshoot; And accelerate LDO exports pressure drop and large overshoot response speed to it; But but increase the power consumption of LDO.
Summary of the invention
In order to solve the high technical matters of existing low pressure difference linear voltage regulator LDO power consumption, the utility model provides a kind of low pressure difference linear voltage regulator LDO of quick response.
Technical solution of the present utility model:
A kind of voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current, comprise band-gap reference 13, operational amplifier 14, feedback resistance string 15 and power tube 16, described band-gap reference is for generation of reference voltage V ref and input to the negative input of operational amplifier 14, described feedback resistance string 15 is connected to the positive input of operational amplifier 14, described feedback resistance string 15 comprises the resistance R1 and resistance R2 that connect successively, the drain terminal of the one termination power tube 16 of described resistance R1, the other end ground connection of described resistance R2, the source of described power tube 16 meets V
dDpower supply, the output terminal of the grid termination operational amplifier of described power tube 16, is characterized in that: also comprise frequency detection circuit 10, bias current generative circuit 11 and output voltage detecting circuit 12,
Described frequency detection circuit 10 for detecting the frequency of carry digital circuit output signal clk, and generates the first electric current I 1 according to the height of the frequency detected and inputs to bias current generative circuit;
Described output voltage detecting circuit 12 for detecting output voltage Vout, and generates the second electric current I 2 according to the height of output voltage Vout and inputs to bias current generative circuit;
Described bias current generative circuit generates a bias current I3 according to the first electric current I 1 of input and the size of the second electric current I 2; Wherein I3=I1*k1+I2*k2; K1 and k2 is the scale-up factor according to setting the requirement of the response speed of voltage stabilizer;
The bias current I3 of the output of described bias current generative circuit, as the input of operational amplifier 14, provides bias current to operational amplifier 14.
The principle that said frequencies testing circuit 10 is followed when generation the first electric current I 1 is; The frequency of carry digital circuit output signal clk is higher, and the first electric current I 1 of generation is larger; The frequency of carry digital circuit output signal clk is lower, and the first electric current I 1 of generation is less.
The principle that above-mentioned output voltage detecting circuit 12 is followed when generation the second electric current I 2 is: the value of output voltage Vout is less, and the second electric current I 2 of generation is larger; The value of output voltage Vout is larger, and the second electric current I 2 of generation is less.
Frequency detection circuit 10 comprises the first operational amplifier 101, phase inverter string 30, Correctional tube M1 and Correctional tube M2, the negative input of the first operational amplifier 101 meets the supply voltage vcore of carry digital circuit, the positive input of the first operational amplifier 101 receives the supply voltage of phase inverter string, the grid end of the output termination Correctional tube M1 of the first operational amplifier 101, the drain terminal of described Correctional tube M1 connects phase inverter string, and the source of described Correctional tube M1 and Correctional tube M2 all meets power supply V
dD, the grid end of the grid termination Correctional tube M1 of described Correctional tube M2, the drain terminal of described Correctional tube M2 exports the first electric current I 1.
Above-mentioned output voltage detecting circuit comprises the switch of the drain terminal series connection of analog to digital converter ADC, metal-oxide-semiconductor m1, metal-oxide-semiconductor m2, metal-oxide-semiconductor m3, metal-oxide-semiconductor m4 and each metal-oxide-semiconductor, the grid end of each metal-oxide-semiconductor all meets the bias voltage vcmp that band-gap reference provides, bias voltage vcmp is for generation of bias current, and the source of each metal-oxide-semiconductor all meets power supply V
dD,
The input termination output voltage Vout of described analog to digital converter ADC and reference voltage Vref, analog to digital converter ADC exports thinking enable signal (en1-en4) according to the difference size of output voltage Vout and reference voltage Vref, and every road enable signal controls a switch.
The breadth length ratio of metal-oxide-semiconductor m1, metal-oxide-semiconductor m2, metal-oxide-semiconductor m3, metal-oxide-semiconductor is 1:2:4:8.
Above-mentioned bias current generative circuit comprises the first mirror image circuit U1, the second mirror image circuit U2, the 3rd mirror image circuit U3, the 4th mirror image circuit U4 and the 5th mirror image circuit U5, first electric current I 1 exports the first image current I1 ' through the first mirror image circuit U1 and the second mirror image circuit U2 successively, second electric current I 2 exports the second image current I2 ' through the 3rd mirror image circuit U3 and the 4th mirror image circuit U4 successively, and the first image current I1 ' and the second image current I2 ' all exports the 3rd electric current I 3 through the 5th mirror image circuit U5.
The breadth length ratio of metal-oxide-semiconductor m11 in first mirror image electricity U1 road and the ratio of the breadth length ratio of metal-oxide-semiconductor m12 are 1:1, and the ratio of the breadth length ratio of the metal-oxide-semiconductor m23 in the second mirror image circuit U2 and the breadth length ratio of metal-oxide-semiconductor m24 is 1:k1;
In 3rd mirror image circuit U3, the ratio of the breadth length ratio of metal-oxide-semiconductor m5 and the breadth length ratio of metal-oxide-semiconductor m6 is 1:1, and the ratio of the breadth length ratio of the metal-oxide-semiconductor m7 in the 4th mirror image circuit U4 and the breadth length ratio of metal-oxide-semiconductor m8 is 1:k2.
The advantage that the utility model has:
1, adopt circuit of the present utility model, when the frequency of carry digital circuit is higher, LDO can be avoided to have excessive pressure drop.
2, according to the size of load current, the reaction velocity of LDO is dynamically accelerated.
3, when load frequency is lower, the power consumption of LDO can be saved.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of typical voltage stabilizer;
Fig. 2 is the circuit structure diagram of voltage stabilizer LDO of the present utility model;
Fig. 3 is the structural representation of the utility model frequency detection circuit;
Fig. 4 is the structural representation of the utility model output voltage detecting circuit;
Fig. 5 is the structural representation of the utility model bias current generative circuit.
Embodiment
The utility model adds partial circuit 20 partial circuit 20 and comprises a frequency detection circuit, an output voltage detecting circuit and a bias current generative circuit on original basis.
Frequency detection circuit detects the frequency of carry digital circuit, and generates an electric current according to the height of frequency.The frequency of operation of digital circuit is higher, and the electric current of generation is larger; The frequency of operation of carry digital circuit is lower, and the electric current of generation is less.
Output voltage detecting circuit detects the output voltage of LDO, and generates an electric current according to the height of output voltage.The value of output voltage is less, and the electric current of generation is larger; The value of output voltage is larger, and the electric current of generation is less.
Bias current generative circuit generates a bias current according to the size of current of input.The electric current I 2 that the electric current I 1 of frequency detection circuit output and output voltage detecting circuit export is as the input of bias current generative circuit.Bias current generative circuit output current I3, wherein I3=I1*k1+I2*k2; K1 and k2 is (namely to the requirement of voltage stabilizer response speed) scale-up factor of setting according to actual needs.The output I3 of bias current generative circuit, as the input of amplifier, provides bias current to amplifier.
Frequency detection circuit can realize as shown in Figure 3.One end of amplifier connects the supply voltage vcore of digital circuit, and the other end is connected to the supply voltage of phase inverter string, and amplifier guarantees that the supply voltage of phase inverter string is equal with the supply voltage of digital circuit.The electric current flowing through Correctional tube M1 equals to flow through the electric current of powering to phase inverter string 30.Phase inverter string 30 be input as clock signal, the electric current flowing through phase inverter power supply is directly proportional to the frequency of clock signal.So the electric current flowing through Correctional tube M1 is also directly proportional to the frequency of clock signal.The electric current of M2 mirror image M1, and output current I1 is provided.So the output current I1 that M2 provides is directly proportional to the frequency of input signal clk, namely the frequency of clk is higher, and the electric current I 1 of output is larger.
Output voltage detecting circuit can realize as shown in Figure 4.The output vout of LDO and reference voltage vref is as the input of analog to digital converter ADC, analog to digital converter ADC exports 4 code:en1 ~ en4m1 according to the difference size of vout and vref, the breadth length ratio of m2, m3, m4 is that the code value that the size of 1:2:4:8.I2 is exported by ADC determines.The value of the minimum value of I2 to be the maximal value of ib1, I2 be ib1+ib2+ib3+ib4=15*ib1. output voltage vout is less, and output current I2 is larger.
Bias current generative circuit can realize as shown in Figure 5.Input the first electric current I 1 and generate the first image current I1 ' by the first mirror image circuit U1, the second mirror image circuit U2, I1 '=I1*k1, wherein k1 is the regulation coefficient according to designing the requirement of output voltage response speed, the ratio of the breadth length ratio of m11 and the breadth length ratio of m12 is the ratio of the breadth length ratio of 1:1, m23 and the breadth length ratio of m24 is 1:k1.Input the second electric current I 2 and generate the second image current I2 ' by the 3rd mirror image circuit U3, the 4th mirror image circuit U4, I2 '=I2*k2, wherein k2 is the regulation coefficient according to designing the requirement of output voltage response speed, the ratio of the breadth length ratio of m5 and the breadth length ratio of m6 is the ratio of the breadth length ratio of 1:1, m7 and the breadth length ratio of m8 is 1:k2.
Claims (8)
1. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current, comprise band-gap reference (13), operational amplifier (14), feedback resistance string (15) and power tube (16), described band-gap reference is for generation of reference voltage V ref and input to the negative input of operational amplifier (14), described feedback resistance string (15) is connected to the positive input of operational amplifier (14), described feedback resistance string (15) comprises the resistance R1 and resistance R2 that connect successively, the drain terminal of the one termination power tube (16) of described resistance R1, the other end ground connection of described resistance R2, the source of described power tube (16) meets V
dDpower supply, the output terminal of the grid termination operational amplifier of described power tube (16), it is characterized in that: also comprise frequency detection circuit (10), bias current generative circuit (11) and output voltage detecting circuit (12)
Described frequency detection circuit (10) for detecting the frequency of carry digital circuit output signal clk, and generates the first electric current I 1 according to the height of the frequency detected and inputs to bias current generative circuit;
Described output voltage detecting circuit (12) for detecting output voltage Vout, and generates the second electric current I 2 according to the height of output voltage Vout and inputs to bias current generative circuit;
Described bias current generative circuit generates a bias current I3 according to the first electric current I 1 of input and the size of the second electric current I 2; Wherein I3=I1*k1+I2*k2; K1 and k2 is the scale-up factor according to setting the requirement of the response speed of voltage stabilizer;
The bias current I3 of the output of described bias current generative circuit, as the input of operational amplifier (14), provides bias current to operational amplifier (14).
2. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current according to claim 1, is characterized in that: the principle that described frequency detection circuit (10) is followed when generation first electric current (1) is; The frequency of carry digital circuit output signal clk is higher, and the first electric current I 1 of generation is larger; The frequency of carry digital circuit output signal clk is lower, and the first electric current I 1 of generation is less.
3. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current according to claim 2, it is characterized in that: the principle that described output voltage detecting circuit (12) is followed when generation the second electric current I 2 is: the value of output voltage Vout is less, the second electric current I 2 of generation is larger; The value of output voltage Vout is larger, and the second electric current I 2 of generation is less.
4. according to the arbitrary described voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current of claim 1-3, it is characterized in that: described frequency detection circuit comprises the first operational amplifier (101), phase inverter string (30), Correctional tube M1 and Correctional tube M2, the negative input of the first operational amplifier (101) meets the supply voltage vcore of carry digital circuit, the positive input of the first operational amplifier (101) receives the supply voltage of phase inverter string, the grid end of the output termination Correctional tube M1 of the first operational amplifier (101), the drain terminal of described Correctional tube M1 connects phase inverter string, the source of described Correctional tube M1 and Correctional tube M2 all meets power supply V
dD, the grid end of the grid termination Correctional tube M1 of described Correctional tube M2, the drain terminal of described Correctional tube M2 exports the first electric current I 1.
5. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current according to claim 4, is characterized in that:
Described output voltage detecting circuit comprises the switch of the drain terminal series connection of analog to digital converter ADC, metal-oxide-semiconductor m1, metal-oxide-semiconductor m2, metal-oxide-semiconductor m3, metal-oxide-semiconductor m4 and each metal-oxide-semiconductor, the grid end of each metal-oxide-semiconductor all meets the bias voltage vcmp that band-gap reference provides, bias voltage vcmp is for generation of bias current, and the source of each metal-oxide-semiconductor all meets power supply V
dD,
The input termination output voltage Vout of described analog to digital converter ADC and reference voltage Vref, analog to digital converter ADC exports thinking enable signal (en1-en4) according to the difference size of output voltage Vout and reference voltage Vref, and every road enable signal controls a switch.
6. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current according to claim 5, is characterized in that: the breadth length ratio of metal-oxide-semiconductor m1, metal-oxide-semiconductor m2, metal-oxide-semiconductor m3, metal-oxide-semiconductor is 1:2:4:8.
7. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current according to claim 5, it is characterized in that: described bias current generative circuit comprises the first mirror image circuit U1, second mirror image circuit U2, 3rd mirror image circuit U3, 4th mirror image circuit U4 and the 5th mirror image circuit U5, first electric current I 1 exports the first image current I1 ' through the first mirror image circuit U1 and the second mirror image circuit U2 successively, second electric current I 2 exports the second image current I2 ' through the 3rd mirror image circuit U3 and the 4th mirror image circuit U4 successively, first image current I1 ' and the second image current I2 ' all exports the 3rd electric current I 3 through the 5th mirror image circuit U5.
8. the voltage stabilizer according to load frequency and output voltage dynamic conditioning bias current according to claim 7, it is characterized in that: the breadth length ratio of metal-oxide-semiconductor m11 in the first mirror image electricity U1 road and the ratio of the breadth length ratio of metal-oxide-semiconductor m12 are 1:1, and the ratio of the breadth length ratio of the metal-oxide-semiconductor m23 in the second mirror image circuit U2 and the breadth length ratio of metal-oxide-semiconductor m24 is 1:k1;
In 3rd mirror image circuit U3, the ratio of the breadth length ratio of metal-oxide-semiconductor m5 and the breadth length ratio of metal-oxide-semiconductor m6 is 1:1, and the ratio of the breadth length ratio of the metal-oxide-semiconductor m7 in the 4th mirror image circuit U4 and the breadth length ratio of metal-oxide-semiconductor m8 is 1:k2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520181260.3U CN204740520U (en) | 2015-03-27 | 2015-03-27 | Stabiliser according to load frequency and output voltage dynamic adjustment bias current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520181260.3U CN204740520U (en) | 2015-03-27 | 2015-03-27 | Stabiliser according to load frequency and output voltage dynamic adjustment bias current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204740520U true CN204740520U (en) | 2015-11-04 |
Family
ID=54422247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520181260.3U Active CN204740520U (en) | 2015-03-27 | 2015-03-27 | Stabiliser according to load frequency and output voltage dynamic adjustment bias current |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204740520U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106774602A (en) * | 2016-12-05 | 2017-05-31 | 清华大学 | A kind of low pressure difference linear voltage regulator with big output current scope |
| CN106774600A (en) * | 2016-12-23 | 2017-05-31 | 长沙景嘉微电子股份有限公司 | A kind of low power consumption power supply circuit |
| CN106774587A (en) * | 2016-12-05 | 2017-05-31 | 清华大学 | A kind of low pressure difference linear voltage regulator |
| CN108008757A (en) * | 2016-10-27 | 2018-05-08 | 意法设计与应用股份有限公司 | Voltage regulator with bias current boosting |
| CN109725673A (en) * | 2019-02-13 | 2019-05-07 | 西安交通大学 | A kind of fully integrated multi output stack low pressure difference linear voltage regulator |
| CN110231847A (en) * | 2019-07-17 | 2019-09-13 | 江苏润石科技有限公司 | Rapid response type low pressure difference linear voltage regulator |
| CN113568466A (en) * | 2021-09-26 | 2021-10-29 | 芯灵通(天津)科技有限公司 | High-voltage-resistant low dropout regulator (LDO) and power-on circuit thereof |
-
2015
- 2015-03-27 CN CN201520181260.3U patent/CN204740520U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108008757A (en) * | 2016-10-27 | 2018-05-08 | 意法设计与应用股份有限公司 | Voltage regulator with bias current boosting |
| CN108008757B (en) * | 2016-10-27 | 2020-07-31 | 意法设计与应用股份有限公司 | Voltage regulator with bias current boost |
| CN106774602A (en) * | 2016-12-05 | 2017-05-31 | 清华大学 | A kind of low pressure difference linear voltage regulator with big output current scope |
| CN106774587A (en) * | 2016-12-05 | 2017-05-31 | 清华大学 | A kind of low pressure difference linear voltage regulator |
| CN106774600A (en) * | 2016-12-23 | 2017-05-31 | 长沙景嘉微电子股份有限公司 | A kind of low power consumption power supply circuit |
| CN109725673A (en) * | 2019-02-13 | 2019-05-07 | 西安交通大学 | A kind of fully integrated multi output stack low pressure difference linear voltage regulator |
| CN110231847A (en) * | 2019-07-17 | 2019-09-13 | 江苏润石科技有限公司 | Rapid response type low pressure difference linear voltage regulator |
| CN113568466A (en) * | 2021-09-26 | 2021-10-29 | 芯灵通(天津)科技有限公司 | High-voltage-resistant low dropout regulator (LDO) and power-on circuit thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104699161B (en) | A kind of voltage-stablizer that bias current is dynamically adjusted according to load frequency and output voltage | |
| CN204740520U (en) | Stabiliser according to load frequency and output voltage dynamic adjustment bias current | |
| CN104699162B (en) | A kind of low pressure difference linear voltage regulator of quick response | |
| CN105138062B (en) | Improve the system of low pressure difference linear voltage regulator load regulation | |
| CN104777869B (en) | A kind of low pressure difference linear voltage regulator of the quickly response of dynamic adjustment reference voltage | |
| CN106774580B (en) | A kind of LDO circuit of fast transient response high PSRR | |
| CN203872056U (en) | Direct-current power supply controlled by constant power | |
| CN103268134B (en) | The low difference voltage regulator of transient response can be improved | |
| CN114200994B (en) | Low dropout linear regulator and laser ranging circuit | |
| CN202067171U (en) | Low dropout linear regulator | |
| CN204480101U (en) | A kind of low pressure difference linear voltage regulator of quick response | |
| CN103775366A (en) | Power supply temperature sampling and fan control circuit and power supply device | |
| CN105048773A (en) | Output voltage control circuit | |
| CN104679084A (en) | Voltage correction circuit and low-dropout linear regulator system | |
| CN105337497B (en) | Improve the system of DC voltage booster circuit transient response | |
| CN104331112A (en) | Low dropout linear regulator and soft starting circuit thereof | |
| CN103631299A (en) | Constant-differential-pressure and variable-output-voltage low dropout regulator | |
| CN109445503A (en) | A kind of LDO circuit applied to integrated chip | |
| CN106774602A (en) | A kind of low pressure difference linear voltage regulator with big output current scope | |
| CN106940580B (en) | A kind of low-power consumption band gap reference and supply unit | |
| CN203422692U (en) | Low dropout regulator and soft start circuit of low dropout regulator | |
| Zhou et al. | Valley V 2 control technique for switching converters with fast transient response | |
| CN103631310A (en) | Band-gap reference voltage source | |
| CN202926683U (en) | Power supply temperature sampling and fan controlling circuit and power supply device | |
| CN103257665A (en) | Non-capacitive low-dropout linear voltage stabilizing system and bias current regulating circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |