CN102298408A - Voltage-stabilizing circuit - Google Patents
Voltage-stabilizing circuit Download PDFInfo
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- CN102298408A CN102298408A CN2011101031183A CN201110103118A CN102298408A CN 102298408 A CN102298408 A CN 102298408A CN 2011101031183 A CN2011101031183 A CN 2011101031183A CN 201110103118 A CN201110103118 A CN 201110103118A CN 102298408 A CN102298408 A CN 102298408A
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Abstract
The invention provides a voltage-stabilizing circuit. The circuit comprises a power supply, a first positive channel metal oxide semiconductor (PMOS) transistor, a feedback resistor, an operational amplifier and loads, wherein the source electrode of the first PMOS transistor is connected with the power supply; the feedback resistor is connected with the drain electrode of the first PMOS transistor; the input end of the operational amplifier is connected with the feedback resistor and the output end of the operational amplifier is connected with the grid electrode of the first PMOS transistor; the loads are connected with the source electrode and grid electrode of the first PMOS transistor; and in the initial power-supplying stage, the voltage on the loads is more than or equal to the threshold voltage of the first PMOS transistor and is less than or equal to the rated operational voltage of the first PMOS transistor. The voltage-stabilizing circuit has higher reliability.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the mu balanced circuit of a kind of CMOS of being used for.
Background technology
(Complementary Metal Oxide Semiconductor CMOS) has advantage low in energy consumption, that antijamming capability is strong etc. to complementary metal oxide semiconductor (CMOS), and it is widely used in the large scale integrated chip manufacturing.
Show the mu balanced circuit that is applied to CMOS with reference to figure 1, described mu balanced circuit comprises: operational amplifier 12, be connected in operational amplifier 12 output terminal OP
OutPMOS pipe 10, particularly, the grid of described PMOS pipe is connected in the output terminal OP of operational amplifier 12
Out, the source electrode of described PMOS pipe is connected in power supply 13, and the drain electrode of described PMOS pipe is connected in resistance 11, and described resistance 11 is connected in the input end of operational amplifier 12.
With reference to figure 2, show the voltage synoptic diagram of mu balanced circuit shown in Figure 1, the voltage of PMOS pipe source electrode in the figure dotted line presentation graphs 1, operational amplifier 12 output terminal OP in the solid line presentation graphs 1
OutVoltage, particularly, supply voltage is 5V to PMOS pipe 10 voltages that provide, therefore, the source voltage of described PMOS pipe 10 rises to 5V very soon, can reach 5V/ μ s the soonest, meanwhile, because the operational amplifier output signal is slow Time Created, therefore at power supply to the 12 power supply initial stages of operational amplifier, operational amplifier 12 output terminal OP
OutVoltage lower because operational amplifier 12 output terminal OP
OutBe connected in the grid of PMOS pipe 10, correspondingly, the grid of PMOS pipe 10 is also lower at the voltage at power supply initial stage, this makes between the grid of PMOS pipe 10 and source electrode bigger voltage, A, B point with same time point in scheming is an example, the voltage that A is ordered is 5V, and the voltage that B is ordered is 0.537V, voltage between the AB point is 4.463V, the grid and the voltage between the source electrode that is to say PMOS pipe 10 are 4.463V, but in this enforcement, the rated operational voltage of PMOS pipe 10 is 3.3V, and the voltage between grid, the source electrode can make the reliability decrease of PMOS pipe 10 greater than rated operational voltage.
Summary of the invention
The problem that the present invention solves provides the higher mu balanced circuit of a kind of reliability.
For addressing the above problem, the invention provides a kind of mu balanced circuit, comprise power supply successively, the PMOS pipe that source electrode links to each other with described power supply, be connected in the feedback resistance of PMOS pipe drain electrode, one input end is connected in the operational amplifier that described feedback resistance, output terminal are connected in the first gate pmos utmost point, also comprise the load that is connected in described PMOS pipe source electrode and grid, at the power supply power supply initial stage, voltage in the described load is more than or equal to the threshold voltage of a PMOS pipe, and is less than or equal to the rated operational voltage of a PMOS pipe.
Described load is the metal-oxide-semiconductor or the diode of one or more series connection.
Described load comprises the load PMOS pipe of a plurality of series connection, link to each other between the grid of each load PMOS pipe and the drain electrode, a plurality of load PMOS pipes source electrode successively link to each other with drain electrode, what link to each other with described PMOS pipe source electrode be the source electrode of first load PMOS pipe, and what link to each other with the drain electrode of described PMOS pipe is the drain electrode of last individual load PMOS pipe.
Described load comprises the load NMOS pipe of a plurality of series connection, link to each other between the grid of each load NMOS pipe and the drain electrode, a plurality of load NMOS manage successively, and source electrode links to each other with drain electrode, what link to each other with described PMOS pipe source electrode be the drain electrode of first load NMOS pipe, the source electrode of the last individual load NMOS pipe that links to each other with the drain electrode of described PMOS pipe.
The difference of described power source voltage and operational amplifier output terminal high level is less than the threshold voltage sum of described a plurality of metal-oxide-semiconductors or diode.
The difference of described supply voltage and operational amplifier output terminal high level is more than or equal to the threshold voltage of a described PMOS pipe.
Described supply voltage is 5V, and the rated operational voltage of a PMOS pipe is 3.3V, and threshold voltage is 0.6～0.8V.
Described load is the load PMOS pipe of 3 series connection, and the threshold voltage of each load PMOS pipe is 0.6～0.8V.
Described load is the load PMOS pipe of 4 series connection, and the threshold voltage of each load PMOS pipe is 0.6～0.8V.
The threshold voltage of each load PMOS pipe equates.
Compared with prior art, the present invention has the following advantages: be connected in the load between PMOS pipe source electrode and the drain electrode, can clamp down on the voltage of operational amplifier output terminal, avoid the bigger problem of voltage between the grid of a PMOS pipe and the source electrode, improve the reliability of mu balanced circuit.
Description of drawings
Fig. 1 is the synoptic diagram of prior art mu balanced circuit one embodiment;
Fig. 2 is the voltage synoptic diagram of mu balanced circuit shown in Figure 1;
Fig. 3 is the synoptic diagram of mu balanced circuit one embodiment of the present invention;
Fig. 4 is the voltage synoptic diagram of mu balanced circuit shown in Figure 3.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
In order to solve the described problem of background technology, the invention provides a kind of mu balanced circuit, described mu balanced circuit comprises power supply successively, the PMOS pipe that source electrode links to each other with described power supply, be connected in the feedback resistance of PMOS pipe drain electrode, one input end is connected in described feedback resistance, output terminal is connected in the operational amplifier of the first gate pmos utmost point, also comprise the load that is connected in described PMOS pipe source electrode and grid, at the power supply power supply initial stage, voltage in the described load is more than or equal to the first threshold voltage of a PMOS pipe, and is less than or equal to the rated operational voltage of a PMOS pipe.
Be provided with the load that is connected in PMOS pipe source electrode and grid among the present invention, describedly load on the power supply power supply and the initial stage can clamp down on the voltage of operational amplifier output terminal, avoid the voltage of operational amplifier output terminal when power supply is powered, to be in lower state, thereby avoided the bigger problem of voltage between the grid of a PMOS pipe and the source electrode, improved the reliability of mu balanced circuit.
Below in conjunction with specific embodiment, further describe technical scheme of the present invention, with reference to figure 3, show the synoptic diagram of mu balanced circuit one embodiment of the present invention.Present embodiment is an example with the mu balanced circuit that the 3.3V output voltage is provided, but the present invention is not restricted to this.
Described mu balanced circuit comprises: power supply 100, PMOS pipe 101, feedback resistance 104, operational amplifier 102, load 103, resistance 105, wherein,
The one PMOS pipe 101 is used to provide the output terminal of mu balanced circuit, also is used to control the output voltage of mu balanced circuit, and it is stable that it is kept.
Particularly, the source electrode of described PMOS pipe 101 is connected in described power supply 100, and grid is connected in the output terminal of described operational amplifier 102, and drain electrode is connected with feedback resistance 104, resistance 105, ground connection afterwards in turn.
Wherein, described PMOS pipe 101 drain electrodes are the voltage output end of mu balanced circuit.
In the present embodiment, the threshold voltage of described PMOS pipe 101 is positioned at the scope of 0.6V～0.8V, and the rated operational voltage VDD of described PMOS pipe 101 is 3.3V.
Particularly, described operational amplifier 102 comprises normal phase input end, negative-phase input, output terminal, described negative-phase input is loaded with reference voltage Vref, described positive input is connected in the end that feedback resistance 104 does not connect PMOS pipe 101, that is to say, feedback resistance 104 is connected between described operational amplifier 102 normal phase input ends and 101 drain electrodes of PMOS pipe, and described output terminal is connected in the grid of described PMOS pipe 101.
Because the output voltage of operational amplifier 102 links to each other with the grid of PMOS pipe 101, in order to guarantee that a PMOS manages conducting between 101 source electrodes and the drain electrode, produce output voltage V out, the high level of operational amplifier 102 need satisfy following relation: the difference of supply voltage and operational amplifier output terminal high level is more than or equal to the threshold voltage of a described PMOS pipe.
In the present embodiment, the high level that described operational amplifier 102 output terminals are exported is positioned at the scope of 4.2V～4.4V.
In order to improve the reliability of PMOS pipe 101, the one PMOS manages the rated operational voltage that voltage between 101 source electrodes and the grid need be less than or equal to PMOS pipe 101, because load 103 is connected in described PMOS pipe source electrode and grid, therefore, preferably, at the 101 power supply initial stages of power supply, the voltage in the described load 103 need be less than or equal to the rated operational voltage of PMOS pipe 101.
Simultaneously, in order to make a PMOS manage conducting between 101 source electrodes and the drain electrode, produce output voltage V out, the voltage that the one PMOS manages between 101 source electrodes and the grid need be more than or equal to the threshold voltage of PMOS pipe 101, preferably, at the power supply power supply initial stage, the voltage in the load 103 needs the threshold voltage more than or equal to PMOS pipe 101.
In the present embodiment, described load 103 is the load PMOS pipe of 3 series connection, the grid of described load PMOS pipe links to each other with drain electrode, 3 load PMOS pipes source electrode successively link to each other with drain electrode, the source electrode of first load PMOS pipe links to each other with the source electrode of described PMOS pipe 101, and the drain electrode of the 3rd load links to each other with the drain electrode of described PMOS pipe 101.
In the present embodiment, the threshold voltage of described load PMOS pipe is identical, and identical with the threshold voltage of PMOS pipe 101, all in the scope of 0.6V～0.8V.But the present invention is not restricted to this.
In order to understand the present invention better, the principle of work of mu balanced circuit of the present invention is described further below in conjunction with change in voltage figure.
In conjunction with reference to figure 4, show the voltage synoptic diagram of mu balanced circuit shown in Figure 3, what Fig. 4 middle polyline 201 was represented is the voltage of power supply 100, the voltage of the output terminal of the operational amplifier of first curve, 202 expressions, and that second curve 203 is represented is the output voltage V out of circuit output end of pressure-stabilizing.
As shown in Figure 4, the 100 power supply initial stages of power supply, voltage on the power supply 100 rises to 5V from 0V apace, at this moment, the source voltage of the one PMOS pipe 101 rises to 5V, load 103 rises to 5V with the terminal voltage that PMOS pipe source electrode links to each other, because the threshold voltage of 3 load PMOS pipes is all in the scope of 0.6V～0.8V in the load 103, described 3 equal conductings of load PMOS pipe, therefore, to manage the link to each other voltage of an end of 101 grids be that power supply 100 voltages deduct load 103 voltages (the threshold voltage sums of 3 load PMOS pipes) for described load 103 and a PMOS.In the present embodiment, the voltage that a described PMOS manages 101 grids is about 3.2V, and the source electrode and the voltage between the grid of PMOS pipe 101 are 1.8V, less than rated operational voltage 3.3V, can not cause a PMOS to manage the problem of 101 reliability decrease.
The source electrode and the voltage between the grid of the one PMOS pipe 101 are 1.8V, also greater than the threshold voltage 0.6～0.8V of PMOS pipe 101, therefore conducting between the source electrode of PMOS pipe 101 and the drain electrode, form conducting channel, electric current is led ground end through source electrode, drain electrode, feedback resistance 104 and the resistance 105 of PMOS pipe 101 successively, make the circuit output end of pressure-stabilizing output voltage V out that is connected in the drain electrode of PMOS pipe, by second curve 203 as can be known, output voltage V out increases gradually.
Because the voltage of operational amplifier 102 normal phase input ends is the difference of the output voltage V out and feedback resistance 104 voltages of mu balanced circuit, that is to say that normal phase input end voltage is directly proportional with output voltage V out, increase gradually along with Vout, correspondingly, normal phase input end voltage increases, shown in first curve 202, when normal phase input end voltage during greater than reference voltage Vref, operational amplifier 102 output voltages increase gradually, this voltage that PMOS is managed between 101 source electrodes and the grid reduces, this can make the channel width between source electrode and the drain electrode reduce, this can reduce the electric current that passes through between source electrode and the drain electrode, thereby Vout increase degree is reduced, and rises to high level up to the operational amplifier output voltage, the stable output of Vout this moment enters the mu balanced circuit course of work from the power supply power supply initial stage.
In the mu balanced circuit course of work, when output voltage V out hour, the forward input voltage of operational amplifier 102 reduces, when less than reference voltage Vref, operational amplifier 102 output voltages descend, the voltage that a PMOS is managed between 101 source electrodes and the grid increases, and manage resistance between 101 source electrodes and the grid thereby reduced a PMOS, thereby the pressure drop that a PMOS is managed between 101 source electrodes and the drain electrode reduces, thereby has increased output voltage.
This shows that under the cooperation of operational amplifier 102 and PMOS pipe 101, mu balanced circuit can be exported stable output voltage V out.
When mu balanced circuit changes normal work stage over to, operational amplifier 102 output voltages are positioned at the scope of 4.2V～4.4V, therefore the voltage in the load 103 is in the scope of 0.6V～0.8V, this makes dividing potential drop on each load PMOS pipe less than its threshold voltage, therefore the load PMOS pipe is in off state, thereby can not influence the output voltage V out of mu balanced circuit.Therefore, in order to make the influence that is not subjected to load 103 in the mu balanced circuit course of normal operation, preferably, the difference of the voltage of described power supply 100 and institute's operational amplifier 102 output terminal high level is less than the threshold voltage sum of described load PMOS pipe, thereby makes the load PMOS pipe be in off state.
Need to prove that in the above-described embodiments, described mu balanced circuit comprises 3 load PMOS pipes, but the present invention being not restricted to this, can also be 4 load PMOS pipes.
Need to prove, in the above-described embodiments, for the ease of circuit design and manufacturing, the threshold voltage of 3 load PMOS pipes is all identical in the described mu balanced circuit, but the present invention is not restricted to this, the threshold voltage of described 3 load PMOS pipes can also be inequality, and the threshold voltage of described load PMOS pipe can also be inequality with a PMOS pipe threshold voltage.
Also need to prove, for the ease of realizing, in the present embodiment, described load is the load PMOS pipe of a plurality of series connection, but the present invention is not restricted to this, can also be the load NMOS pipe of a plurality of series connection, link to each other between the grid of described load NMOS pipe and the drain electrode, a plurality of load NMOS manage successively source electrode and link to each other with drain electrode, and what link to each other with described PMOS pipe source electrode be the drain electrode of first load NMOS pipe, and draining with described PMOS pipe, what link to each other is the source electrode of last individual NMOS pipe.
Described in addition load can also be the load of other types such as a plurality of diode in series, is the situation of a plurality of diode in series for load, and described a plurality of diodes both positive and negative polarity successively join end to end.
In addition, described load also can be single metal-oxide-semiconductor or diode, and those skilled in the art can correspondingly revise, replace and be out of shape according to the foregoing description.
To sum up, the invention provides a kind of mu balanced circuit, by being connected in the load between PMOS pipe source electrode and the drain electrode, clamp down on the voltage of operational amplifier output terminal, improved the reliability of mu balanced circuit at the power supply power supply initial stage.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. mu balanced circuit, it is characterized in that, comprise power supply successively, the PMOS pipe that source electrode links to each other with described power supply, be connected in the feedback resistance of PMOS pipe drain electrode, one input end is connected in the operational amplifier that described feedback resistance, output terminal are connected in the first gate pmos utmost point, also comprise the load that is connected in described PMOS pipe source electrode and grid, at the power supply power supply initial stage, voltage in the described load is more than or equal to the threshold voltage of a PMOS pipe, and is less than or equal to the rated operational voltage of a PMOS pipe.
2. mu balanced circuit as claimed in claim 1 is characterized in that, described load is the metal-oxide-semiconductor or the diode of one or more series connection.
3. mu balanced circuit as claimed in claim 2 is characterized in that, described load comprises the load PMOS pipe of a plurality of series connection, links to each other a plurality of load PMOS between the grid of each load PMOS pipe and the drain electrode
Manage successively source electrode and link to each other with drain electrode, what link to each other with described PMOS pipe source electrode be the source electrode of first load PMOS pipe, and draining with described PMOS pipe, what link to each other is the drain electrode of last individual load PMOS pipe.
4. mu balanced circuit as claimed in claim 2, it is characterized in that, described load comprises the load NMOS pipe of a plurality of series connection, link to each other between the grid of each load NMOS pipe and the drain electrode, a plurality of load NMOS manage successively, and source electrode links to each other with drain electrode, what link to each other with described PMOS pipe source electrode be the drain electrode of first load NMOS pipe, the source electrode of the last individual load NMOS pipe that links to each other with the drain electrode of described PMOS pipe.
5. mu balanced circuit as claimed in claim 2 is characterized in that, the difference of described power source voltage and operational amplifier output terminal high level is less than the threshold voltage sum of described a plurality of metal-oxide-semiconductors or diode.
6. mu balanced circuit as claimed in claim 2 is characterized in that, the difference of described supply voltage and operational amplifier output terminal high level is more than or equal to the threshold voltage of a described PMOS pipe.
7. mu balanced circuit as claimed in claim 3 is characterized in that, described supply voltage is 5V, and the rated operational voltage of a PMOS pipe is 3.3V, and threshold voltage is 0.6～0.8V.
8. mu balanced circuit as claimed in claim 7 is characterized in that, described load is the load PMOS pipe of 3 series connection, and the threshold voltage of each load PMOS pipe is 0.6～0.8V.
9. mu balanced circuit as claimed in claim 7 is characterized in that, described load is the load PMOS pipe of 4 series connection, and the threshold voltage of each load PMOS pipe is 0.6～0.8V.
10. mu balanced circuit as claimed in claim 8 or 9 is characterized in that, the threshold voltage of each load PMOS pipe equates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101031183A CN102298408A (en) | 2011-04-22 | 2011-04-22 | Voltage-stabilizing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101031183A CN102298408A (en) | 2011-04-22 | 2011-04-22 | Voltage-stabilizing circuit |
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| CN102298408A true CN102298408A (en) | 2011-12-28 |
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| CN2011101031183A Pending CN102298408A (en) | 2011-04-22 | 2011-04-22 | Voltage-stabilizing circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104793676A (en) * | 2014-01-17 | 2015-07-22 | 精工电子有限公司 | Voltage regulator and semiconductor device |
| WO2018109473A1 (en) * | 2016-12-16 | 2018-06-21 | Nordic Semiconductor Asa | Voltage regulator |
| CN115202427A (en) * | 2021-04-09 | 2022-10-18 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
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| US20010030530A1 (en) * | 2000-04-12 | 2001-10-18 | Stmicroelectronics S.A. | Low electrical consumption voltage regulator |
| US20010050546A1 (en) * | 2000-04-12 | 2001-12-13 | Stmicroelectronics S.A. | Linear regulator with low overshooting in transient state |
| US7450354B2 (en) * | 2005-09-08 | 2008-11-11 | Aimtron Technology Corp. | Linear voltage regulator with improved responses to source transients |
| CN101354595A (en) * | 2007-07-26 | 2009-01-28 | 盛群半导体股份有限公司 | Low pressure drop voltage stabilizer for enhancing linearity and load regulation rate characteristic |
| CN101634868A (en) * | 2008-07-23 | 2010-01-27 | 三星电子株式会社 | Low dropout voltage stabilizer |
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2011
- 2011-04-22 CN CN2011101031183A patent/CN102298408A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010030530A1 (en) * | 2000-04-12 | 2001-10-18 | Stmicroelectronics S.A. | Low electrical consumption voltage regulator |
| US20010050546A1 (en) * | 2000-04-12 | 2001-12-13 | Stmicroelectronics S.A. | Linear regulator with low overshooting in transient state |
| US7450354B2 (en) * | 2005-09-08 | 2008-11-11 | Aimtron Technology Corp. | Linear voltage regulator with improved responses to source transients |
| CN101354595A (en) * | 2007-07-26 | 2009-01-28 | 盛群半导体股份有限公司 | Low pressure drop voltage stabilizer for enhancing linearity and load regulation rate characteristic |
| CN101634868A (en) * | 2008-07-23 | 2010-01-27 | 三星电子株式会社 | Low dropout voltage stabilizer |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104793676A (en) * | 2014-01-17 | 2015-07-22 | 精工电子有限公司 | Voltage regulator and semiconductor device |
| CN104793676B (en) * | 2014-01-17 | 2018-03-30 | 精工半导体有限公司 | Voltage-stablizer and semiconductor device |
| WO2018109473A1 (en) * | 2016-12-16 | 2018-06-21 | Nordic Semiconductor Asa | Voltage regulator |
| CN115202427A (en) * | 2021-04-09 | 2022-10-18 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
| CN115202427B (en) * | 2021-04-09 | 2023-12-12 | 上海艾为电子技术股份有限公司 | Voltage stabilizing circuit and power management chip |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140423 |
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Application publication date: 20111228 |