CN111294041B - Anti-irradiation reinforced codec - Google Patents

Abstract

The coding and decoding device comprises a coding module and a decoding module, wherein the basic unit gates of an anti-irradiation reinforced structure are partially used in the basic unit gates forming the coding module and the decoding module, and the basic unit gates include but are not limited to a phase inverter of the anti-irradiation reinforced structure and a two-input NAND gate of the anti-irradiation reinforced structure, so that the anti-irradiation reinforcement is realized, and the speed is kept fast; in addition, the register units in the coding module and the decoding module use the register of the bidirectional interlocking storage unit, and a phase inverter is introduced into a two-stage latch structure to increase the driving capability of the front-stage latch to the rear-stage latch and improve the speed of the trigger, so that the invention has good anti-irradiation performance and can meet the speed requirement of a circuit.

Description

Anti-irradiation reinforced codec

Technical Field

The invention belongs to the field of integrated circuit science, relates to an anti-irradiation reinforced codec, and is suitable for an SERDES circuit.

Background

Serial-parallel-serial conversion transceivers (SerDes/deserializers) are interface circuits for a variety of high-speed bus protocols and are widely used in the military and civilian fields. The civil products are mainly applied to protocols such as USB, SATA, PCIe and the like; the military industry and aerospace products mainly apply protocols such as FC-AE, ethernet and the like. Fig. 1 shows a circuit configuration of an 8B10B high-speed SerDes circuit, which is composed of a receive path and a transmit path. The transmitting module comprises an 8B10B encoder, a pseudo-random code generator (PRBS), a parallel-serial conversion circuit, a transmitter, a phase-locked loop (PLL) and other modules; the receiving channel is composed of modules such as a clock data recovery Circuit (CDR), a serial-parallel conversion circuit, a pseudo random code detector (PRBS _ Veri), an 8B10B decoder, a COMMA detection circuit and the like.

In the development of modern weaponry, electronic systems are becoming more and more important, and the role of serial interfaces as key components in various electronic systems is becoming more and more prominent in various weaponry systems. From the application of the domestic military interface circuit, its development characteristics are as follows.

First, military electronic components have high requirements for reliability, environmental suitability, and the like. Military electronic components are complex in application environment and have high performance requirements in extreme environments such as high and low temperature, radiation and the like, so that the design difficulty of chips is greatly increased.

Secondly, the overall development trend of military interface circuits is the same as that of civilians, and with the rapid development of communication technologies, the demand for signal bandwidth is larger and larger, and the quantity of data required to be transmitted is larger and larger. In the information-based construction of weaponry, the way of information communication is more and more prominent.

In this context, high speed SerDes technology and its products have rapidly evolved in the modern military. In many countries, including the united states, germany and russia, the high-speed data processing and transmission technology in the high-speed SerDes technology has been widely applied to the information-based construction of military troops, and has been in a trend of steady and high-speed development. With the development of military industry and aerospace industry in China, the anti-irradiation SerDes has a great demand, and the anti-irradiation SerDes chip is generally used. However, the radiation-resistant SerDes independently developed in China is still a blank, completely depends on import and is expensive, so that the development of the radiation-resistant SerDes has practical significance. At present, no better anti-radiation SerDes substitute product exists in China, so that the development of the anti-radiation SerDes product independently developed in China is imminent. The overall SerDes typically includes input/output register circuitry, 8b/10b codec circuitry, serial-to-parallel/parallel-to-serial conversion circuitry, phase-locked loop circuitry, clock recovery circuitry, receive/transmit circuitry, and equalization circuitry. In SerDes circuits, the on-chip 8B10B codec is a critical module therein, and is critical to its radiation-resistant design.

There are two main types of common irradiation, from cosmic rays and nuclear radiation, respectively. Depending on the mechanism of action, the effects of irradiation can be divided into Total dose Effect (TID) and Single Event Effect (SEE).

When the microelectronic device is irradiated by the total dose, high-energy photons or particles can be injected into the device to lose energy in different forms, so that energy is deposited in the device, and the material is ionized to generate electron-hole pairs. The concentration of electron-hole pairs generated in the material is proportional to the energy of deposition of the radiation inside the device, which in turn has a certain relationship with the mass and energy of the photons or particles generated by the radiation and the atomic number and mass of the target material being irradiated. The cumulative energy deposited in a unit mass of material during an exposure period is referred to as the total dose, which is expressed in units of Gray (Gy) or rad (rad), where Gray is the international standard unit for the total dose, but rad is the most commonly used unit in the field of total dose research, and is reported in most literature as rad.

The single particle effect is that many high-energy charged particles from cosmic rays, solar flares and other radiation sources exist in the space environment. These energetic particles, upon incidence on a device (e.g., random access memory, microprocessor, voltage converter, etc.), often form electron-hole pairs in the sensitive region inside the device. The electron-hole pairs form a signal that opens the junction, and these faults are collectively referred to as Single Event Effects (SEE).

Up to now, there are probably the following radiation-resistant reinforcements for integrated circuits: and (4) process reinforcement, design reinforcement and packaging reinforcement. The process reinforcement meets the requirement of radiation resistance through process optimization, and related researches are carried out on the aspects of processes such as CMOS, SOI, SOS, gallium arsenide, ferroelectric and the like at present, wherein the SOI technology is the most mature and the cost performance is the best. Design hardening is undoubtedly the mainstream method of the current radiation-resistant technology, and more reliable circuit design can be used in the aspect of circuits. For sensitive and important logic circuit parts, a watchdog circuit, a triple modular redundancy design, a bidirectional interlocking memory unit (DICE) structure design for resisting single event upset in the circuit and the like can be adopted. For sensitive logic circuit parts, radiation-resistant schemes such as special gate structure design for resisting total dose effect, isolation ring design for resisting single event latch-up and the like can also be adopted from the aspect of layout. The biggest advantage of designing a reinforcing mode is that the method is compatible with commercial process lines, reduces the process cost, and is suitable for domestic development at present when the forbidden limit is strict. Encapsulation reinforcement was first proposed in 1979 and its feasibility was investigated in the 80 s. The shielding type packaging technology can improve the radiation resistance of the chip by 2-3 orders of magnitude.

The difficulty of the radiation-resistant design is that all radiation-resistant design reinforcement measures can reduce the working frequency of a circuit to a certain extent, so that a SerDes interface cannot meet the design requirement, and therefore, how to obtain a good compromise between the working speed and the radiation resistance of the circuit is the research difficulty in the SerDes interface circuit.

Disclosure of Invention

Aiming at the defect that the balance between the working speed and the radiation resistance is difficult to realize when radiation resistance reinforcement is introduced into a SerDes interface circuit, the invention provides the radiation resistance reinforced coder-decoder, which adopts a design reinforcement mode to realize radiation resistance reinforcement, can be applied to the SerDes interface circuit, and achieves the speed requirement of the circuit while ensuring the radiation resistance.

The technical scheme of the invention is as follows:

the anti-irradiation reinforced codec comprises an encoding module and a decoding module, wherein the encoding module comprises an 8B10B encoder and an encoding register unit, the decoding module comprises a COMMA detection unit, an 8B10B decoder and a decoding register unit, and the 8B10B encoder, the COMMA detection unit and the 8B10B decoder are formed by basic unit gates;

the basic unit gate part in the 8B10B encoder, the COMMA detection unit and the 8B10B decoder uses a basic unit gate of an irradiation-resistant reinforced structure, the basic unit gate of the irradiation-resistant reinforced structure comprises a phase inverter of the irradiation-resistant reinforced structure, the phase inverter of the irradiation-resistant reinforced structure comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube,

the grid electrode of the second PMOS tube is connected with the grid electrodes of the first PMOS tube, the first NMOS tube and the second NMOS tube and serves as the input end of the phase inverter of the anti-irradiation reinforced structure, the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube and the grid electrode of the third NMOS tube and is connected with power supply voltage, and the drain electrode of the second PMOS tube is connected with the drain electrodes of the second NMOS tube, the third NMOS tube and the third PMOS tube and serves as the output end of the phase inverter of the anti-irradiation reinforced structure;

the grid electrode of the third PMOS tube is connected with the source electrodes of the second NMOS tube and the first NMOS tube and is grounded, and the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube;

the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube;

the coding register unit and the decoding register unit comprise a plurality of registers, the registers comprise a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube and a twenty-fifth NMOS tube,

the grid electrode of the ninth PMOS tube is connected with the grid electrode of the ninth NMOS tube and serves as the clock input end of the register, the source electrode of the ninth PMOS tube is connected with the source electrodes of the tenth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube and the seventeenth PMOS tube and is connected with power supply voltage, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube and the grid electrodes of the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube and the twenty-fifth NMOS tube;

the input end of the first phase inverter is used as the data input end of the register, and the output end of the first phase inverter is connected with the input end of the second phase inverter and the source electrodes of the nineteenth NMOS transistor and the twenty-first NMOS transistor;

the output end of the second phase inverter is connected with the source electrodes of the eighteenth NMOS tube and the twentieth NMOS tube;

the grid electrode of the tenth NMOS tube is connected with the grid electrode of the tenth PMOS tube and the drain electrodes of the eleventh NMOS tube, the thirteenth PMOS tube and the eighteenth NMOS tube, the drain electrodes of the tenth NMOS tube and the twenty-first NMOS tube are connected with the drain electrodes of the twelfth PMOS tube and the twenty-first NMOS tube, the grid electrodes of the thirteenth PMOS tube and the thirteenth NMOS tube and the input end of the third phase inverter, and the source electrodes of the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube and the seventeenth NMOS tube are connected with the source electrodes of the ninth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube and the seventeenth NMOS tube and grounded;

the grid electrode of the twelfth NMOS tube is connected with the drain electrodes of the eleventh PMOS tube, the thirteenth NMOS tube and the twentieth NMOS tube and the grid electrode of the twelfth PMOS tube, and the drain electrode of the twelfth NMOS tube is connected with the grid electrodes of the eleventh NMOS tube and the eleventh PMOS tube and the drain electrodes of the tenth PMOS tube and the nineteenth NMOS tube;

the input end of the fourth phase inverter is connected with the output end of the third phase inverter and the drain electrodes of the twenty-second NMOS transistor and the twenty-fourth NMOS transistor, and the output end of the fourth phase inverter is connected with the drain electrodes of the twenty-third NMOS transistor and the twenty-fifth NMOS transistor;

the grid electrode of the fourteenth NMOS tube is connected with the grid electrode of the fourteenth PMOS tube, the source electrode of the twenty-second NMOS tube and the drain electrodes of the fifteenth NMOS tube and the seventeenth PMOS tube, and the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixteenth PMOS tube, the source electrode of the twenty-fifth NMOS tube, the grid electrodes of the seventeenth NMOS tube and the seventeenth PMOS tube and the input end of the fifth phase inverter;

the output end of the fifth inverter is used as the output end of the register;

the grid electrode of the sixteenth NMOS tube is connected with the grid electrode of the sixteenth PMOS tube, the source electrode of the twenty-fourth NMOS tube and the drain electrodes of the seventeenth NMOS tube and the fifteenth PMOS tube, and the drain electrode of the sixteenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube, the source electrode of the twenty-third NMOS tube and the grid electrodes of the fifteenth NMOS tube and the fifteenth PMOS tube.

Specifically, the basic unit gate of the anti-radiation reinforced structure further comprises a two-input nand gate of the anti-radiation reinforced structure, a three-input nand gate of the anti-radiation reinforced structure and a nor gate of the anti-radiation reinforced structure.

Specifically, the two-input NAND gate of the anti-irradiation reinforced structure comprises a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube,

the grid electrode of the fourth PMOS tube is connected with the grid electrodes of the fourth NMOS tube, the seventh NMOS tube and the sixth PMOS tube and serves as the first input end of the two-input NAND gate of the anti-irradiation reinforced structure, the source electrode of the fourth PMOS tube is connected with the source electrodes of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube and the grid electrode of the sixth NMOS tube and is connected with power supply voltage, and the drain electrode of the fourth PMOS tube is connected with the drain electrodes of the fifth PMOS tube, the eighth PMOS tube, the fourth NMOS tube and the sixth NMOS tube and serves as the output end of the two-input NAND gate of the anti-irradiation reinforced structure;

the grid electrode of the fifth PMOS tube is connected with the grid electrodes of the fifth NMOS tube, the eighth NMOS tube and the seventh PMOS tube and serves as the second input end of the two-input NAND gate of the anti-irradiation reinforced structure;

the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the fifth NMOS tube is connected with the grid electrode of the eighth PMOS tube and the source electrode of the eighth NMOS tube and is grounded;

the source electrode of the eighth PMOS tube is connected with the drain electrodes of the sixth PMOS tube and the seventh PMOS tube;

the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, and the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube.

The invention has the beneficial effects that: the codec provided by the invention introduces two anti-irradiation reinforcement measures and combines with a speed-increasing scheme, and a basic unit door of an anti-irradiation reinforcement structure is partially used in the codec, so that the anti-irradiation reinforcement is realized and the speed is kept high; the register of the bidirectional interlocking storage unit is used in the register unit, and the phase inverter is introduced into the two-stage latch structure to increase the driving capability of the front stage to the rear stage latch and improve the speed of the trigger, so that the invention has good radiation resistance and can meet the speed requirement of the circuit.

Drawings

Fig. 1 is an overall circuit framework of a SerDes.

Fig. 2 (a) is a schematic structural diagram of an inverter with an anti-radiation hardened structure for use in an anti-radiation hardened codec according to the present invention; fig. 2 (b) is a schematic structural diagram of a two-input nand gate of the radiation-resistant reinforced structure.

Fig. 3 is a schematic structural diagram of a bidirectional interlocking storage element (DICE) configuration register used in a ruggedized codec according to the present invention.

Fig. 4 is a circuit diagram of a coding module in a codec with radiation hardening resistance according to the present invention.

Fig. 5 is a circuit diagram of a decoding module in a codec with radiation hardening resistance according to the present invention.

Fig. 6 (a) is a schematic structural diagram of a three-input nand gate using an anti-radiation reinforced structure in an anti-radiation reinforced codec according to the present invention, and fig. 6 (b) is a schematic structural diagram of a three-input nor gate using an anti-radiation reinforced structure in an anti-radiation reinforced codec according to the present invention.

Fig. 7 shows the results of the encoder simulation, the input data is 8 bits, the output is 10 bits of encoded data and the input data is from 00000000 to 11111111. Wherein out is the netlist circuit result, out _ o is the encoder result after the irradiation resistance is strengthened, and the encoder result is completely consistent after comparison.

Fig. 8 shows the simulation results of the decoder, and it can be seen that the output of the decoder is from 00000000 to 11111111, which is consistent with the data input by the encoder, and the decoder works normally.

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments.

Fig. 1 is an overall circuit framework of a SerDes circuit, which includes a codec including an encoding module and a decoding module, and fig. 4 and 5 are internal structures of the encoding module and the decoding module, respectively, the encoding module includes an encoding register unit (such as an 18-bit input register in fig. 1), a controller, an 8B10B encoder, a multiplexer, a pseudo-random number generator, and the like, and the decoding module includes a decoding register unit (including an output register in fig. 1 and a shift register, an input register, and the like in fig. 5), an 8B10B decoder, a COMMA detector, a pseudo-random code detector, a multiplexer, and the like.

The invention introduces anti-radiation reinforcement measures based on a coder and a decoder in a SerDes circuit, and the anti-radiation reinforcement measures introduced by the invention are mainly divided into two aspects: for the basic unit gate, the invention adopts two measures of large capacitance and positive feedback to design and reinforce, and improves the single-particle transient pulse resistance of the circuit. The invention provides a method for selecting partial basic unit gates as basic unit gates of an anti-radiation reinforced structure, in particular to partially replace the basic unit gates in an 8B10B encoder, a COMMA detection unit and an 8B10B decoder with the basic unit gates of the anti-radiation reinforced structure. For the storage units such as the register, the invention uses the register of a bidirectional interlocking storage unit (DICE), introduces a phase inverter between two-pole latch structures, increases the driving capability of the front-stage latch to the rear-stage latch, improves the speed of the trigger, and improves the single event upset resistance of the storage node. The two radiation-resistant reinforcing measures proposed by the invention are explained in detail below.

The first radiation-resistant reinforcement measure: the basic unit gate of the irradiation-resistant reinforced structure comprises but is not limited to an inverter of the irradiation-resistant reinforced structure, a two-input NAND gate of the irradiation-resistant reinforced structure, a three-input NAND gate of the irradiation-resistant reinforced structure and a NOR gate of the irradiation-resistant reinforced structure. The following description will take the two-input nand gate of the invention using the inverter with anti-radiation reinforced structure and the anti-radiation reinforced structure as an example.

As shown in fig. 2 (a), the inverter with anti-radiation reinforcing structure used in the present invention includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3, wherein the gate of the second PMOS transistor PM2 is connected to the gates of the first PMOS transistor PM1, the first NMOS transistor NM1, and the second NMOS transistor NM2 and serves as the input terminal of the inverter with anti-radiation reinforcing structure, the source thereof is connected to the source of the first PMOS transistor PM1 and the gate of the third NMOS transistor NM3 and is connected to the power voltage vdd, and the drain thereof is connected to the drains of the second NMOS transistor NM2, the third NMOS transistor NM3, and the third NMOS transistor PM3 and serves as the output terminal of the inverter with anti-radiation reinforcing structure; the grid electrode of the third PMOS tube PM3 is connected with the source electrodes of the second NMOS tube NM2 and the first NMOS tube NM1 and grounded gnd, and the source electrode of the third PMOS tube PM3 is connected with the drain electrode of the first PMOS tube PM 1; the source of the third NMOS transistor NM3 is connected to the drain of the first NMOS transistor NM 1. The gate node vee of the third PMOS transistor PM3 is connected to ground gnd, and the gate node vcc of the third NMOS transistor NM3 is connected to the global power supply, i.e., the supply voltage vdd.

The whole phase inverter consists of six MOS (metal oxide semiconductor) tubes, wherein a second PMOS (P-channel metal oxide semiconductor) tube PM2 and a second NMOS (N-channel metal oxide semiconductor) tube NM2 form a basic phase inverter structure, so that the phase inversion function is realized; the first PMOS pipe PM1 and the first NMOS pipe NM1 are used as backups of a basic phase inverter and are reinforced pull-up and pull-down networks; the third PMOS tube PM3 and the third NMOS tube NM3 form a larger grid source capacitor, and the larger grid source capacitor plays a role in error correction when being irradiated.

As shown in fig. 2 (b), the two-input nand gate of the irradiation-resistant reinforced structure used in the present invention includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8, wherein the gate of the fourth PMOS transistor PM4 is connected to the gates of the fourth NMOS transistor NM4, the seventh NMOS transistor NM7, and the sixth PMOS transistor PM6 and serves as the first input terminal of the two-input nand gate of the irradiation-resistant reinforced structure, the source thereof is connected to the sources of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, and the seventh PMOS transistor PM7 and the ddd of the sixth NMOS transistor NM6 and the drain thereof is connected to the output terminal of the two-input nand gate of the irradiation-resistant reinforced structure, and the drain thereof is connected to the drains of the fifth PMOS transistor PM5, the eighth PMOS transistor PM8, the fourth NMOS transistor NM4, and the sixth NMOS transistor NM6 and the output terminal of the irradiation-resistant reinforced structure; the grid electrode of the fifth PMOS tube PM5 is connected with the grid electrodes of a fifth NMOS tube NM5, an eighth NMOS tube NM8 and a seventh PMOS tube PM7 and serves as a second input end of the two-input NAND gate of the anti-irradiation reinforced structure; the drain electrode of the fifth NMOS tube NM5 is connected with the source electrode of the fourth NMOS tube NM4, and the source electrode thereof is connected with the grid electrode of the eighth PMOS tube PM8 and the source electrode of the eighth NMOS tube NM8 and grounded gnd; the source electrode of the eighth PMOS tube PM8 is connected with the drain electrodes of the sixth PMOS tube PM6 and the seventh PMOS tube PM 7; the drain of the seventh NMOS transistor NM7 is connected to the source of the sixth NMOS transistor NM6, and the source thereof is connected to the drain of the eighth NMOS transistor NM 8.

The basic unit gate of the radiation-resistant reinforced structure which can be introduced includes a three-input nand gate or a nor gate, etc. in addition to the above-mentioned inverter and two-input and gate, as shown in fig. 6, (a) and (b) are specific internal structures of a three-input nand gate and a three-input nor gate of the radiation-resistant reinforced structure which can be used for forming a codec, respectively. In addition, because the work speed is reduced when the basic unit gate of the anti-radiation reinforced structure is introduced, for some combinational logics with long critical paths, if the anti-radiation reinforced unit gate is completely used, the establishment time of the register is not satisfied, therefore, the invention adopts the measure of reducing the anti-single event transient pulse (SET), in order to achieve faster speed, the size of the pipe can be modified, or the traditional basic unit gate and the basic unit gate of the anti-radiation reinforced structure are used together, therefore, the invention provides that part of the basic unit gates are replaced by the basic unit gate of the anti-radiation reinforced structure, and the quantity distribution of the traditional basic unit gate and the basic unit gate of the anti-radiation reinforced structure can be determined according to simulation, therefore, the invention realizes the structure modification to accelerate speed and realize anti-radiation under the condition of ensuring the logic function to be unchanged.

The second radiation-resistant reinforcement measure: the register comprises a first phase inverter inv1, a second phase inverter inv2, a third phase inverter inv3, a fourth phase inverter inv4, a fifth phase inverter inv5, a ninth PMOS tube PM9, a tenth PMOS tube PM10, an eleventh PMOS tube PM11, a twelfth PMOS tube PM12, a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14, a fifteenth PMOS tube PM15, a sixteenth PMOS tube PM16, a seventeenth PMOS tube PM17, a ninth NMOS tube NM9, a tenth NMOS tube NM10, an eleventh NMOS tube NM11, a twelfth NMOS tube NM12, a thirteenth NMOS tube NM13, a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16, a seventeenth NMOS tube NM17, an eighteenth NMOS tube NM18, a nineteenth NMOS tube NM19, a twentieth NMOS tube NM20, a twenty-fourth NMOS tube NM24, a twenty-fourth NMOS 24 and a twenty-fourth NMOS 24, a gate of the ninth PMOS transistor PM9 is connected to a gate of the ninth NMOS transistor NM9 and serves as a clock input terminal of the register, a source thereof is connected to sources of the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, the sixteenth PMOS transistor PM16, and the seventeenth PMOS transistor PM17 and is connected to the power voltage vdd, and a drain thereof is connected to a drain of the ninth NMOS transistor NM9 and gates of the eighteenth NMOS transistor NM18, the nineteenth NMOS transistor NM19, the twentieth NMOS transistor NM20, the twenty-first NMOS transistor NM21, the twenty-second NMOS transistor NM22, the twenty-third NMOS transistor NM23, the twenty-fourth NMOS transistor NM24, and the twenty-fifth NMOS transistor NM 25; an input end of the first inverter inv1 serves as a data input end of the register, and an output end of the first inverter inv1 is connected with an input end of the second inverter inv2 and source electrodes of the nineteenth NMOS transistor NM19 and the twenty-first NMOS transistor NM 21; the output end of the second inverter inv2 is connected with the sources of the eighteenth NMOS transistor NM18 and the twentieth NMOS transistor NM 20; a grid electrode of the tenth NMOS transistor NM10 is connected to a grid electrode of the tenth PMOS transistor PM10 and drain electrodes of the eleventh, thirteenth and eighteenth NMOS transistors NM11, PM13 and NM18, drain electrodes thereof are connected to drain electrodes of the twelfth and twenty-first PMOS transistors PM12 and NM21, grid electrodes of the thirteenth and thirteenth PMOS transistors PM13 and NM13, and an input end of the third inverter inv3, and source electrodes thereof are connected to source electrodes of the ninth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth and seventeenth NMOS transistors NM9, NM11 and gnd, and grounded; the grid electrode of the twelfth NMOS tube NM12 is connected with the drain electrodes of the eleventh, thirteenth and twentieth PMOS tubes PM11, NM13 and PM 20 and the grid electrode of the twelfth PMOS tube PM12, and the drain electrode thereof is connected with the grid electrodes of the eleventh and eleventh NMOS tubes NM11, PM10 and NM 19; an input end of the fourth inverter inv4 is connected to the output end of the third inverter inv3 and drain electrodes of the twenty-second NMOS transistor NM22 and the twenty-fourth NMOS transistor NM24, and an output end thereof is connected to drain electrodes of the twenty-third NMOS transistor NM23 and the twenty-fifth NMOS transistor NM 25; the grid electrode of the fourteenth NMOS tube NM14 is connected with the grid electrode of the fourteenth PMOS tube PM14, the source electrode of the twenty-second NMOS tube NM22 and the drain electrodes of the fifteenth NMOS tube NM15 and the seventeenth PMOS tube PM17, and the drain electrode thereof is connected with the drain electrode of the sixteenth PMOS tube PM16, the source electrode of the twenty-fifth NMOS tube NM25, the grid electrodes of the seventeenth NMOS tube NM17 and the seventeenth PMOS tube PM17 and the input end of the fifth inverter inv 5; the output end of the fifth inverter inv5 is used as the output end of the register; the gate of the sixteenth NMOS transistor NM16 is connected to the gates of the sixteenth PMOS transistor PM16, the twenty-fourth NMOS transistor NM24, and the seventeenth NMOS transistor NM17 and the fifteenth PMOS transistor PM15, and the drain thereof is connected to the drain of the fourteenth PMOS transistor PM14, the source of the twenty-third NMOS transistor NM23, and the fifteenth NMOS transistor NM15 and the fifteenth PMOS transistor PM 15.

According to the register structure provided by the invention, the third inverter inv3 and the fourth inverter inv4 are added in the two-stage latch structure, so that the driving capability of the front-stage latch structure to the rear-stage latch structure is improved, the speed of the trigger is increased, the driving capability is increased, the irradiation resistance reinforcement is realized while the speed is increased.

The invention is based on the anti-irradiation reinforcement design of the codec in the 8B10Bserdes circuit, aiming at the irradiation mechanism and the actual 8B10B circuit design scheme, the anti-irradiation reinforcement is carried out on the circuit structure of the 8B10B codec, and the design reinforcement method is mainly used, so that the anti-irradiation capability is ensured, and the design index of the circuit is achieved. In order to verify that the codec provided by the invention maintains high-level circuit indexes while realizing irradiation resistance, the invention also builds a test circuit platform, and simulation test is carried out on the circuit after irradiation resistance reinforcement design, and the circuit speed of the invention is required to be that the ultimate operating frequency of an 8B10B encoder circuit is not lower than 125MHz, the ultimate operating frequency of a 8B10B decoder circuit is not lower than 250MHz, and the 8B10B codec circuit is designed based on a 0.13 mu m standard process. The test conditions are set as that the operating frequency of an 8B10B encoder is 250MHz, the operating frequency of a 8B10B decoder is 500MHz, the operating frequencies are 2 times of the circuit requirements, and the process angle selected in the test is SS.

The test uses a standard 0.13 μm CMOS process library, which specifically includes the following steps:

step 1: through the functional study of the 8B10B codec, as shown in FIG. 1, the 8B10B codec is described by using a hardware description language, and simulation is performed by Modelsim software to confirm that the code functions are correct.

Step 2: using Synopsys Design Compiler software, the DC software automatically generated a gate-level netlist description of the circuit using code descriptions, timing constraint files and a standard 0.13 μm process library as input files, which resulted in a circuit using a combination of NOR-based gates.

And step 3: and (3) based on the gate-level netlist obtained in the step (2), using an anti-irradiation reinforced basic gate in Cadence to build a 8B10B circuit, wherein the combinational logic reinforcement uses two methods, one is that the basic cell gate part in the codec uses the basic cell gate of an anti-irradiation reinforced structure, a larger capacitor is introduced to reduce the influence of single-particle bombardment, and the other is that positive feedback is introduced to improve the overturning threshold value of the gate, so that the circuit generates a hysteresis curve similar to a Schmitt trigger, and burrs generated by the single-particle bombardment are reduced, as shown in figure 2. For sequential logic, i.e., registers, the present invention uses bidirectional interlocking memory element (DICE) flip-flops to improve the single event upset resistance of the storage node, as shown in fig. 3.

And 4, step 4: combining all sub-modules with irradiation resistance reinforcement to obtain a complete 8B10B encoder and decoder circuit diagram, as shown in fig. 4 and fig. 5, firstly respectively carrying out simulation test on an 8B10B encoder and decoder, testing the encoding capacity of the encoder with a test clock of 125MHz, and comparing with the code simulation data in the step 1 to obtain a completely correct comparison result; the testing clock of the decoder is 250MHz, and the decoding result is completely consistent with the code simulation, which indicates that the circuit works normally.

And 5: the encoder and decoder were connected for joint simulation, with the encoder test image as in fig. 7 and the decoder test image as in fig. 8. The coder and the decoder use asynchronous clocks, after the coder codes input data, the decoder decodes the coded data into input original data, the input and output data are completely consistent, the coder and the decoder work correctly, and the expected target is achieved.

The invention combines the anti-irradiation measure with the 8B10B coder-decoder, designs a circuit with excellent coding and decoding performance and good anti-irradiation performance, and the test result shows that the coding and decoding circuit provided by the invention successfully reaches the design index, has normal function, can be widely applied to the field of military industry or aerospace and aviation, and meets the urgent needs of the state.

In summary, the invention designs and reinforces the 8B10B codec circuit in the SerDes circuit based on a design reinforcement method aiming at the damage caused by the space radiation environment or the nuclear radiation environment to the circuit, provides two radiation-resistant reinforcement measures and combines with a speed-increasing scheme, and partially uses a basic unit gate of a radiation-resistant reinforcement structure in the codec, so that the radiation-resistant reinforcement is realized while a faster speed is maintained; the register of the bidirectional interlocking storage unit is used in the register unit, and the phase inverter is introduced into the two-stage latch structure to increase the driving capability of the front stage to the rear stage latch and improve the speed of the trigger, so that the invention has good radiation resistance and can meet the speed requirement of the circuit.

Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its aspects.

Claims (3)

1. The anti-irradiation reinforced codec comprises an encoding module and a decoding module, wherein the encoding module comprises an 8B10B encoder and an encoding register unit, the decoding module comprises a COMMA detection unit, an 8B10B decoder and a decoding register unit, and the 8B10B encoder, the COMMA detection unit and the 8B10B decoder are formed by basic unit gates;

the method is characterized in that basic unit gates in the 8B10B encoder, the COMMA detection unit and the 8B10B decoder are partially basic unit gates of an irradiation-resistant reinforced structure, the basic unit gates of the irradiation-resistant reinforced structure comprise phase inverters of the irradiation-resistant reinforced structure, the phase inverters of the irradiation-resistant reinforced structure comprise a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube,

the grid electrode of the second PMOS tube is connected with the grid electrodes of the first PMOS tube, the first NMOS tube and the second NMOS tube and serves as the input end of the phase inverter of the anti-irradiation reinforced structure, the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube and the grid electrode of the third NMOS tube and is connected with power supply voltage, and the drain electrode of the second PMOS tube is connected with the drain electrodes of the second NMOS tube, the third NMOS tube and the third PMOS tube and serves as the output end of the phase inverter of the anti-irradiation reinforced structure;

the grid electrode of the third PMOS tube is connected with the source electrodes of the second NMOS tube and the first NMOS tube and is grounded, and the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube;

the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube;

the coding register unit and the decoding register unit comprise a plurality of registers, the registers comprise a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube and a twenty-fifth NMOS tube,

the grid electrode of the ninth PMOS tube is connected with the grid electrode of the ninth NMOS tube and serves as the clock input end of the register, the source electrode of the ninth PMOS tube is connected with the source electrodes of the tenth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube and the seventeenth PMOS tube and is connected with power supply voltage, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube and the grid electrodes of the eighteenth NMOS tube, the nineteenth NMOS tube, the twentieth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube and the twenty-fifth NMOS tube;

the input end of the first phase inverter is used as the data input end of the register, and the output end of the first phase inverter is connected with the input end of the second phase inverter and the source electrodes of the nineteenth NMOS transistor and the twenty-first NMOS transistor;

the output end of the second phase inverter is connected with the source electrodes of the eighteenth NMOS tube and the twentieth NMOS tube;

the grid electrode of the tenth NMOS tube is connected with the grid electrode of the tenth PMOS tube and the drain electrodes of the eleventh NMOS tube, the thirteenth PMOS tube and the eighteenth NMOS tube, the drain electrodes of the tenth NMOS tube and the twenty-first NMOS tube are connected with the drain electrodes of the twelfth PMOS tube and the twenty-first NMOS tube, the grid electrodes of the thirteenth PMOS tube and the thirteenth NMOS tube and the input end of the third phase inverter, and the source electrodes of the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube and the seventeenth NMOS tube are connected with the source electrodes of the ninth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube and the seventeenth NMOS tube and grounded;

the grid electrode of the twelfth NMOS tube is connected with the drain electrodes of the eleventh PMOS tube, the thirteenth NMOS tube and the twentieth NMOS tube and the grid electrode of the twelfth PMOS tube, and the drain electrode of the twelfth NMOS tube is connected with the grid electrodes of the eleventh NMOS tube and the eleventh PMOS tube and the drain electrodes of the tenth PMOS tube and the nineteenth NMOS tube;

the input end of the fourth phase inverter is connected with the output end of the third phase inverter and the drain electrodes of the twenty-second NMOS transistor and the twenty-fourth NMOS transistor, and the output end of the fourth phase inverter is connected with the drain electrodes of the twenty-third NMOS transistor and the twenty-fifth NMOS transistor;

the grid electrode of the fourteenth NMOS tube is connected with the grid electrode of the fourteenth PMOS tube, the source electrode of the twenty-second NMOS tube and the drain electrodes of the fifteenth NMOS tube and the seventeenth PMOS tube, and the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixteenth PMOS tube, the source electrode of the twenty-fifth NMOS tube, the grid electrodes of the seventeenth NMOS tube and the seventeenth PMOS tube and the input end of the fifth phase inverter;

the output end of the fifth inverter is used as the output end of the register;

the grid electrode of the sixteenth NMOS tube is connected with the grid electrode of the sixteenth PMOS tube, the source electrode of the twenty-fourth NMOS tube and the drain electrodes of the seventeenth NMOS tube and the fifteenth PMOS tube, and the drain electrode of the sixteenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube, the source electrode of the twenty-third NMOS tube and the grid electrodes of the fifteenth NMOS tube and the fifteenth PMOS tube.

2. The codec of claim 1, wherein the basic unit gate of the radiation-hardening structure further comprises a two-input nand gate of the radiation-hardening structure, a three-input nand gate of the radiation-hardening structure, and a nor gate of the radiation-hardening structure.

3. The codec of claim 2, wherein the two-input NAND gate of the anti-radiation reinforcement structure comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor,

the grid electrode of the fourth PMOS tube is connected with the grid electrodes of the fourth NMOS tube, the seventh NMOS tube and the sixth PMOS tube and serves as a first input end of a two-input NAND gate of the anti-irradiation reinforced structure, the source electrode of the fourth PMOS tube is connected with the source electrodes of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube and the grid electrode of the sixth NMOS tube and is connected with power supply voltage, and the drain electrode of the fourth PMOS tube is connected with the drain electrodes of the fifth PMOS tube, the eighth PMOS tube, the fourth NMOS tube and the sixth NMOS tube and serves as an output end of the two-input NAND gate of the anti-irradiation reinforced structure;

the grid electrode of the fifth PMOS tube is connected with the grid electrodes of the fifth NMOS tube, the eighth NMOS tube and the seventh PMOS tube and is used as a second input end of the two-input NAND gate of the anti-radiation reinforced structure;

the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the fifth NMOS tube is connected with the grid electrode of the eighth PMOS tube and the source electrode of the eighth NMOS tube and is grounded;

the source electrode of the eighth PMOS tube is connected with the drain electrodes of the sixth PMOS tube and the seventh PMOS tube;

the drain electrode of the seventh NMOS tube is connected with the source electrode of the sixth NMOS tube, and the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube.

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