CN104409093A - Differential ten-tube storage cell resistant to single-event upset - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit storages, and particularly relates to a differential ten-tube storage cell resistant to single-event upset. The cell structure comprises two cross-coupled PMOS (P-channel Metal Oxide Semiconductor) pairs, two cross-coupled NMOS (N-channel Metal Oxide Semiconductor) pairs and a pair of NMOS transfer tubes, and contains four interlocking storage nodes. The first storage node and the second storage node are interlocked through the first cross-coupled PMOS pair; the first storage node and the third storage node are interlocked through the first cross-coupled NMOS pair; the second storage node and the fourth storage node are interlocked through the second cross-coupled NMOS pair; the third storage node and the fourth storage node are interlocked through the second cross-coupled NMOS pair; when the storage cell is subjected to single-particle event interference, the interlocked storage nodes can effectively resist single-particle interference, and stored data are protected from being upset. The differential ten-tube storage cell is the same as a six-tube storage cell, and has the same differential reading and writing operating modes, but eliminates frequent reading damage and semi-selective damage of the six-tube storage cell.

Description

Difference 10 transistor memory unit of anti-single particle reversion

Technical field

The invention belongs to integrated circuit memory and establish technical field, be specifically related to a kind of register file (Register File) and static RAM (Static Random Access Memory, SRAM) unit.

Background technology

Along with reducing of process, the electric capacity of signal node is more and more less, and node capacitance stored charge is also thereupon more and more less, and this makes signal node more and more easily be subject to the interference of single event.Disturb the chip mistake caused usually to be called soft error (soft error) by single event, this is a kind of random, nonrecurring impermanency mistake caused because of high energy particle impact.

In the encapsulating material of chip, there is a small amount of radioelement uranium, thorium, they produce α particle in decay process, when α particle impact signal node, can produce high energy electron pulse instantaneously, thus reverse signal.Along with the development of technique, the material of encapsulation is more and more purer, makes because encapsulating the soft error rate caused more and more lower.But at present, the high-energy neutron from space is the main source of chip soft error.For being applied to aerospace chip, the likelihood ratio ground chip that soft error occurs for it at least exceeds three orders of magnitude.

In chip, logical circuit and storer are all vulnerable to the interference of single event, but for storer, particularly static RAM, due to its high density and do not have mask mechanism, make it more easily soft error occur.Therefore, the SRAM of anti-soft error seems particularly important.

Design all be inclined to the SRAM adopting support position interleaving function, add that the error correcting code (error correction code, ECC) of unit realizes the SRAM of anti-soft error.Such as, 2009, author I. J. Chang, deliver in magazine " Journal of Solid-State Circuits " " 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS ", propose the subthreshold value 10TSRAM with an interleaving function; 2011, author Do Anh-Tuan delivers in magazine " Transaction on Circuits and Systems-I:Regular Papers " " An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS ", proposes one equally and respectively adopts the position of AND structure to hand over 8 transistor memory units.2012, author Ming-Hsien Tu, deliver in magazine " Journal of Solid-State Circuits " " A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure; Negative Bit-Line; and adaptive Read Operation Timing Tracing ", propose the subthreshold value 9TSRAM that has an interleaving function.

But these SRAM can only solve the soft error problem of unit data, and need the assistance of ECC error correcting code, for the soft error of multidigit, then need the SRAM designing anti-single particle reversion especially.

Summary of the invention

The object of the present invention is to provide a kind of 10 transistor memory units with the anti-single particle reversion of higher reading and writing stability.

10 transistor memory units of anti-single particle reversion provided by the invention, comprising: two to cross-linked PMOS couple, two to cross-linked NMOS couple, and a pair NMOS transfer tube, 4 storage nodes mutually locked.Wherein:

The grid of first PMOS is connected with the drain electrode of second PMOS, and the grid of second PMOS is connected with the drain electrode of first PMOS, and their source electrodes are connected with power vd D, forms first to cross-linked PMOS couple; The grid of first NMOS tube is connected with the drain electrode of second NMOS tube, and the grid of second NMOS tube is connected with the drain electrode of first NMOS tube, and their source electrodes are connected with ground GND, forms first to cross-linked NMOS couple; The grid of the 3rd NMOS tube is connected with the drain electrode of the 4th NMOS tube, and the grid of the 4th NMOS tube is connected with the drain electrode of the 3rd NMOS tube, and their source electrodes are connected with ground GND, forms second to cross-linked NMOS couple; The grid of the 3rd PMOS is connected with the drain electrode of the 4th PMOS, and the grid of the 4th PMOS is connected with the drain electrode of the 3rd PMOS, and their source electrodes are connected with power vd D, forms second to cross-linked PMOS couple;

Further, first storage node and second storage node by first to cross-linked PMOS to interlocking; First storage node and the 3rd storage node by first to cross-linked NMOS to interlocking; Second storage node and the 4th storage node by second to cross-linked NMOS to interlocking; 3rd storage node and the 4th storage node by second to cross-linked PMOS to interlocking; The value of first storage node storage equals the value of the 4th storage node storage, and the value of second storage node storage equals the value of the 3rd storage node storage;

Meanwhile, two NMOS transfer tubes control by wordline WL, and their source electrode is connected with second storage node with first storage node respectively, and drain electrode is connected with paratope line BLB with bit line BL respectively, form the reading and writing circuit of storage unit.

When storage unit is subject to single event interference, storage node interlocked with one another effectively can resist single-particle interference, and the data that protection stores are not inverted.Further, it and 6 traditional transistor memory units have same difference reading and writing mode of operation, and what but eliminate that 6 transistor memory units often occur reads a character with two or more ways of pronunciation bad and partly select to destroy.

Anti-single particle reversion storage unit provided by the invention can effectively resist soft error, and has higher reading and writing stability.

Accompanying drawing explanation

Fig. 1 is electrical block diagram of the present invention.

Fig. 2 is that the present invention deposits the circuit operation schematic diagram of " 1 " node by single-particle interference.

Fig. 3 is that the present invention deposits the circuit operation schematic diagram of " 0 " node by single-particle interference.

Fig. 4 is reading circuit operation chart of the present invention.

Embodiment

The invention describes 10 transistor memory units of a kind of anti-single particle reversion, below set forth design philosophy of the present invention and example.

Figure 1 shows that anti-single particle that the present invention realizes reverses 10 transistor memory unit circuit structures.PMOS 301 and 302 forms first to cross-linked PMOS to 311, PMOS 307 and 308 forms second to cross-linked PMOS to 341, NMOS tube 303 and 304 forms first to cross-linked NMOS to 321, NMOS tube 305 and 306 forms second to cross-linked NMOS to 331, NMOS tube 309 and 310 is two transfer tubes, and 320,330,340 and 350 is four storage nodes mutually locked.Wherein, the grid of PMOS 301 is connected with the drain electrode of PMOS 302, and the grid of PMOS 302 pipe is connected with the drain electrode of PMOS 301, and their source electrodes are connected with power vd D, cross coupled with one another; The grid of NMOS tube 303 is connected with the drain electrode of NMOS tube 304, and the grid of NMOS tube 304 is connected with the drain electrode of NMOS tube 303, and their source electrodes are connected with ground GND, cross coupled with one another; The grid of NMOS tube 305 is connected with the drain electrode of NMOS tube 306, and the grid of NMOS tube 306 is connected with the drain electrode of NMOS tube 305, and their source electrodes are connected with ground GND, cross coupled with one another; The grid of PMOS 307 is connected with the drain electrode of PMOS 308, and the grid of PMOS 308 is connected with the drain electrode of PMOS 307, and their source electrodes are connected with power vd D, cross coupled with one another.Further, first storage node 320 and second storage node 330 interlock 311 cross-linked PMOS by first; First storage node 320 and the 3rd storage node 340 interlock 321 cross-linked NMOS by first; Second storage node 330 and the 4th storage node 350 interlock 331 cross-linked NMOS by second; 3rd storage node 340 and the 4th storage node 350 interlock 341 cross-linked PMOS by second.The value of first storage node 320 storage equals the value of the 4th storage node 350 storage, and the value of second storage node 330 storage equals the value of the 3rd storage node 340 storage.Meanwhile, two NMOS transfer tubes control by wordline WL, and their source electrode is connected with second storage node 330 with first storage node 320 respectively, and drain electrode is connected with paratope line BLB with bit line BL respectively, form the reading and writing circuit of storage unit.

Fig. 2 represents that the present invention deposits " 1 " node is by the circuit operation of single-particle interference.Now, the value that node 320 and 350 is deposited is " 1 ", and the value that node 330 and 340 is deposited is " 0 ".If node 320 disturbs by single-particle, produce a negative pulse, then it is " 0 " from " 1 " instantaneous abrupt change.Due to this saltus step, PMOS 302 is opened, and starts to charge to storage node 330, because the node of storage node 340 and 350 and generation saltus step is isolated, so the value that their store can not be affected.Therefore, NMOS tube 305 is in opening all the time, carries out drop-down to node 330, then now node 330 exists the charging of PMOS and the electric discharge of NMOS tube simultaneously, produces larger short-circuit current, likely produces the positive current pulses of moment.After the single event of moment terminates, PMOS weakens the charging of 330, then node 330 is pulled original " 0 " state again, and then, the node 320 that single-particle shock occurs also is retracted one state by PMOS 301.This whole process lasts is comparatively of short duration, and the storage node of interlocking makes whole storage unit can recover after single-particle clashes into.

Fig. 3 represents that storage unit of the present invention deposits the circuit operation of " 0 " node by single-particle interference.Now, the value that node 320 and 350 is deposited is " 0 ", and the value that node 330 and 340 is deposited is " 1 ".If node 320 disturbs by single-particle, produce a positive pulse, then it is " 1 " from " 0 " instantaneous abrupt change.Due to this saltus step, NMOS tube 304 is opened, and starts to discharge to storage node 340, because the node of storage node 330 and 350 and generation saltus step is isolated, so the value that their store can not be affected.Therefore, NMOS tube 307 is in opening all the time, fills the people to node 340, then now node 340 exists the charging of PMOS and the electric discharge of NMOS tube simultaneously, produces larger short-circuit current, likely produces the negative current pulse of moment.After the single event of moment terminates, NMOS tube weakens the charging of 340, then node 340 is filled back original one state again, and then, the node 320 that single-particle shock occurs also is retracted " 0 " state by NMOS tube 303.This whole process lasts is comparatively of short duration, and the storage node of interlocking makes whole storage unit can recover after single-particle clashes into.So what value no matter the present invention stores, can recover when being subject to single-particle interference, effectively having resisted the generation of soft error from interference.

Fig. 4 represents the circuit operation under storage unit reading mode of the present invention.When storage unit carries out read operation, wordline WL is high, and BL preliminary filling is high and floating.The data of difference read on bit line by 309,303 and 310,305.In read operation process, due to the existence of process deviation, the magnitude of voltage of node 320 or 330 may reach a high level, but due to other storage node be isolate with participating in the node of read operation, so the value of other storage node is interference-free.After read operation terminates, the value being disturbed node storage can be retracted original state by other undisturbed node equally.And in traditional storage unit, this reading a character with two or more ways of pronunciation produced because of process deviation badly cannot be avoided.Therefore, in other words, the present invention completely eliminate read a character with two or more ways of pronunciation bad, certainly also eliminate because of read a character with two or more ways of pronunciation bad cause partly select destroy.

Claims (1)

1. 10 transistor memory units of anti-single particle reversion, it is characterized in that comprising: two to cross-linked PMOS couple, two to cross-linked NMOS couple, a pair NMOS transfer tube, 4 storage nodes mutually locked; Wherein:

The grid of first PMOS is connected with the drain electrode of second PMOS, and the grid of second PMOS is connected with the drain electrode of first PMOS, and their source electrodes are connected with power vd D, forms first to cross-linked PMOS couple; The grid of first NMOS tube is connected with the drain electrode of second NMOS tube, and the grid of second NMOS tube is connected with the drain electrode of first NMOS tube, and their source electrodes are connected with ground GND, forms first to cross-linked NMOS couple; The grid of the 3rd NMOS tube is connected with the drain electrode of the 4th NMOS tube, and the grid of the 4th NMOS tube is connected with the drain electrode of the 3rd NMOS tube, and their source electrodes are connected with ground GND, forms second to cross-linked NMOS couple; The grid of the 3rd PMOS is connected with the drain electrode of the 4th PMOS, and the grid of the 4th PMOS is connected with the drain electrode of the 3rd PMOS, and their source electrodes are connected with power vd D, forms second to cross-linked PMOS couple;

Further, first storage node and second storage node by first to cross-linked PMOS to interlocking; First storage node and the 3rd storage node by first to cross-linked NMOS to interlocking; Second storage node and the 4th storage node by second to cross-linked NMOS to interlocking; 3rd storage node and the 4th storage node by second to cross-linked PMOS to interlocking; The value of first storage node storage equals the value of the 4th storage node storage, and the value of second storage node storage equals the value of the 3rd storage node storage;

Meanwhile, two NMOS transfer tubes control by wordline WL, and their source electrode is connected with second storage node with first storage node respectively, and drain electrode is connected with paratope line BLB with bit line BL respectively, form the reading and writing circuit of storage unit.