CN106330164A - NOR gate or And gate-based preparation method for anti-radiation latch - Google Patents

Abstract

The invention belongs to the field of integrated circuits and relate to a/an NOR gate or And gate-based circuit design method for an anti-radiation latch, in particular to a/an NOR gate or And gate-based preparation method for an anti-radiation latch. According to the latch, 8 basic units formed by NOR gates or AND gates are connected in a mutually twisted manner. When a storage node value is changed due to radiation, other mutually-twisted nodes restrain this change through the NOR gates. After the radiation effect disappears, the false storage node will be driven to recover to the original correct value, so the latch has the anti-radiation fault tolerant characteristic.

Description

A kind of based on nor gate with the preparation method of the radioprotective latch with door

Technical field

The invention belongs to integrated circuit fields, relate to a kind of circuit based on nor gate with the radioprotective latch of door and set Meter method, particularly relates to a kind of based on nor gate with the preparation method of the radioprotective latch with door,

Background technology

Research report is along with the minimizing of process, and the integrated circuit in chip is in high-rise space or near-earth spherical space more More it is easily subject to heavy particle or proton irradiation impact and produces mistake；Radiation is if it occur that in the storage of latch circuit Node, may directly result in latch storage erroneous values, produce single event upset；Radiation is if it occur that in group Close circuit node, single event transient pulse may be caused, change the logic state of circuit node；This single-ion transient state arteries and veins The improper value that punching causes is transmitted to latch can be likely to the storage that is captured, and produces single event upset.So simple grain Sub-rollover event can change the logic state of latch circuit storage, is likely to result in integrated circuit capability error.Therefore, Need to propose to support radiation-resistant latch circuit method for designing.

At present, the method for designing of radioprotective latch circuit mainly comprises multi-mode redundant, error correcting code and radiation hardening skill Arts etc., wherein, multi-mode redundant method, with triplication redundancy technology as representative, uses redundant circuit module and majority voting electricity The output of road shielding erroneous circuits module, but this method can bring the biggest area overhead；Error correction code approach is with Hamming Code is representative, by the check value of calculation code, the position of Wrong localization bit；Radiation hardening technology with dual mutually Latch storage unit is representative, increases extra transistor and the most stranded interconnection on the basis of basic unit of storage structure Line, strengthens the capability of resistance to radiation of sensitive nodes；But error correcting code and radiation hardening technology can bring bigger area overhead, And reduce circuit performance.

In view of the present situation of prior art, present inventor intends providing a kind of radioprotective based on nor gate with door to lock The preparation method of storage, with the defect overcoming the method for designing of prior art radioprotective latch circuit to exist.

List of references related to the present invention has:

[1]Baumann R.Soft Errors in Advanced Computer Systems[J],IEEE Transactions on Device and Materials Reliability,2005,22(3),pp.258-266

[2] Oliveira R., Jagirdar A., Chakraborty T.J.:A TMR Scheme for SEU Mitigation in Scan Flip-Flops [C], in International Symposium on QualityElectronic Design, 2007, pp.905 –910

[3]Tausch H.J.Simplified Birthday Statistics and Hamming EDAC[J],IEEE Transactions on Nuclear Science,2009,56(2),pp.474–478

[4]Calin T.,Nicolaidis M.,Velazco R.Upset Hardened Memory Design for Submicron CMOS Technology[J],IEEE Transactions on Nuclear Science,1996,43(6),pp. 2874–2878

[5]S.Yang.Logic Synthesis and Optimization Benchmarks User Guide,Research Triangle Park,NC:Microelectronics Center ofNorth Carolina(MCNC),1991。

Summary of the invention

It is an object of the invention to, for defect present in the design of radioprotective latch circuit in integrated circuit, propose one Kind based on nor gate and the circuit design method of the radioprotective latch with door, be specifically related to a kind of based on nor gate and with The preparation method of the radioprotective latch of door.

Specifically, the present invention a kind of is based on nor gate with the preparation method of the radioprotective latch with door, its feature It is, uses a nor gate and one and door one elementary cell of composition, mutually twist by eight elementary cells the most again Close and connect, construct a radioprotective latch；When a memory node value changes because of radiation, mutual stranded company Other node connect suppresses this change by nor gate, so that this latch has Anti-radioactive Fault-tolerant characteristic.

The inventive method includes following two steps:

Step 1: according to circuit structure shown in Fig. 1, uses traditional integrated circuit method for designing design radioprotective latch Circuit,

Circuit structure as shown in Figure 1, design based on nor gate and with the radioprotective latch circuit of door；If in Fig. 1 Two line infalls have stain, represent that two lines are connected；If two line infalls do not have stain, represent that two lines do not connect； In Fig. 1 nor gate N1 and with door A1 constitute first elementary cell；Nor gate N2 and with door A2 constitute second Elementary cell；Nor gate N3 and constitute the 3rd elementary cell with door A3；Nor gate N4 and constitute the with door A4 Four elementary cells；Nor gate N5 and constitute the 5th elementary cell with door A5；Nor gate N6 and with door A6 structure Become the 6th elementary cell；Nor gate N7 and constitute the 7th elementary cell with door A7；Nor gate N8 and with door A8 Constitute the 8th elementary cell；In elementary cell, nor gate realizes logic or non-functional, realizes logical AND function with door； With the data input pin D and input end of clock CLK that the input of door A1, A3, A5 and A7 is latch, defeated Go out end and be respectively D1, D3, D5 and D7；Inverse value is held in the data input pin D inverted device V1 output of latch Signal Db；Being Db and input end of clock CLK with the input of door A2, A4, A6 and A8, outfan is respectively For D2, D4, D6 and D8.

In the present invention, the input of each nor gate, outfan are as shown in table 1.

The input of table 1 nor gate and output

Nor gate	Input	Output
			N1	C3、Q、D1	C4
N2	C6、C4、D2	Q
			N3	Q、C1、D3	C5
N4	C7、C5、D4	C1
			N5	C1、C2、D5	C6
N6	C4、C6、D6	C2
			N7	C2、C3、D7	C7
N8	C5、C7、D8	C3

In conjunction with Fig. 1 and Biao 1, when input end of clock CLK value is 1, the value of data input pin D and phase inverter V1 Value (Db value is the inverse value of D) the write latch of outfan Db, the value of data output end Q is input D Value；When input end of clock CLK value is 0, D and the Db value of write is stored in the memory node C1-C7 of latch With outfan Q；Such as, when D value is 1, and CLK value is 1, phase inverter V1 outfan Db value is 0, with door A1 outfan D1 value is 1, is 1 with door A5 outfan D5 value, is 0 with door A2 outfan D2 value；Due to D1 Value is 1, so the outfan C4 value of nor gate N1 is 0, is 1 due to D5 value again, so nor gate N5's is defeated Going out to hold C6 value is 0；It is all 0 due to C6, C4 and D2 value, so the outfan Q-value of nor gate N2 is 1；With Reason, C5, C7 value is all 0 and C1, C2, C3 value is all 1；When input end of clock CLK value is 0, with door The outfan D1 of A1 and A2 and D2 value are all 0, but are still 1 due to Q-value, so the outfan of nor gate N1 C4 value remains 0；It is still 1 due to C2 value, so the outfan C6 value of nor gate N5 remains 0；Due to C6, C4 and D2 value is all 0, so the outfan Q-value of nor gate N2 is 1, this strengthens the numerical value 1 before Q further, So that the storage numerical value 0 and 1 that memory node C4 and outfan Q is the most stable；In like manner, memory node C5, C6, C7 all stable storage numerical value 0, and C1, C2, C3 value all stable storage numerical value 1；The most such as, when D value it is When 0, CLK value is 1, phase inverter V1 outfan Db value is 1, is 0 with door A1 outfan D1 value, with door A2 Outfan D2 value is 1, is 1 with door A8 outfan D8 value；Owing to D2 value is 1, so nor gate N2's is defeated Going out to hold Q-value is 0, is 1 due to D8 value again, so the outfan C3 value of nor gate N8 is 0；Due to C3, Q It is all 0 with D1 value, so the outfan C4 value of nor gate N1 is 1；In like manner, C1, C2 value be all 0 and C5, C6, C7 value is all 1；When input end of clock CLK value is 0, with outfan D1 and D2 of door A1 and A2 Value is all 0, but is still 1 due to C4 value, so the outfan Q-value of nor gate N2 remains 0；Due to C7 value still It is 1, so the outfan C3 value of nor gate N8 remains 0；It is all 0 due to C3, Q and D1 value, thus or non- The outfan C4 value of door N1 is 1, and this strengthens the numerical value 1 before C4 further so that memory node C4 with Storage numerical value 1 and 0 the most stable for outfan Q；In like manner, memory node C5, C6, C7 all stable storage numerical value 1, And C1, C2, C3 value all stable storage numerical value 0；

If any one nodal value is because of radiation generation temporarily change, phase in memory node C1-C7 and data output end Q Other node of mutual stranded connection can suppress this change by nor gate；Such as, when data input pin D value is 1, Then when input end of clock CLK value is 0, memory node C1, C2, C3 and data output end Q store numerical value 1, Memory node C4, C5, C6, C7 store numerical value 0；Assume that memory node C5 temporarily becomes 1 from 0, then because of radiation Nor gate N4 outfan C1 value becomes 0 from 1, and nor gate N8 outfan C3 value becomes 0 from 1, but Q-value is still 1, so nor gate N3 outfan C5 value effect to be irradiated reverts to 0 after disappearing, now C7, D4, D8 value is still 0, so C1 value and C3 value also revert to 1；Assume that data output end Q-value is temporarily changed 0 because of radiation from 1, but by Remaining 1 in C3 value and C1 value, nor gate N1 outfan C4 value and nor gate N3 outfan C5 value all keep Being 0, C6 value and D2 value also remain 0；After effect to be irradiated disappears, remain C4, C6 and D2 value of 0 and make Nor gate N2 outfan Q-value reverts to 1；The most such as, when data input pin D value is 0, then at input end of clock When CLK value is 0, memory node C1, C2, C3 and data output end Q store numerical value 0, memory node C4, C5, C6, C7 store numerical value 1；Assume that memory node C5 temporarily becomes 0 from 1 because of radiation, but C7 value is still 1, so Nor gate N4 outfan C1 value and nor gate N8 outfan C3 value remain 0, and D3 value and Q-value also remain 0, After effect to be irradiated disappears, C1, the D3 and the Q-value that remain 0 make nor gate N3 outfan C5 value revert to 1； Assume that data output end Q-value is temporarily changed 1 because of radiation from 0, then nor gate N1 outfan C4 value becomes 0 from 1, Nor gate N3 outfan C5 value becomes 0 from 1, but C7 value and C6 value are still 1, so nor gate N4 outfan C1 value remains 0, and nor gate N2 outfan Q-value effect to be irradiated reverts to 0 after disappearing, now C3, D1 and D3 value is still 0, so C4 value and C5 value also revert to 1；

Step 2: the input end of clock CLK of latch in Fig. 1 is operated, makes data can write this latch, And make this latch have radioprotective characteristic；

In Fig. 1, latch has both of which: write data, stable storage data；

If latch is under write-ining data mode, input end of clock CLK value is set to 1, the value of data input pin D Writing latch with the value (Db value is the inverse value of D) of Db, the value of data output end Q is the value of input D；

If latch is under stable storage data pattern, input end of clock CLK value is set to 0, write latch D and Db value is stored in the memory node C1-C7 and outfan Q of latch；Memory node C1, C2, C3 and data The value of outfan Q storage D, the value of memory node C4, C5, C6, C7 storage Db；If memory node C1-C7 Temporarily change, other node meeting of mutual stranded connection is there is because of radiation with any one nodal value in data output end Q Suppress this change by nor gate, effect to be irradiated making after disappearing to make a mistake the node of change recover before correct Value.

The invention have the advantages that

The present invention propose a kind of based on nor gate and with the radioprotective latch circuit of door, this latch make eight by or Not gate and mutual with the elementary cell that door is constituted stranded be connected, when a memory node value changes because of radiation, phase Other node of mutual stranded connection suppresses this change by nor gate, so that this latch has Anti-radioactive Fault-tolerant spy Property.

Accompanying drawing illustrates:

Fig. 1 is the electrical block diagram of the radioprotective latch of the present invention.

Embodiment 1 test experiments,

In experiment, realize 6 benchmark test circuit without capability of resistance to radiation initially with traditional standard circuit design method Bigkey, dsip, S38417, S13207.1, S15850.1, S38584.1, divide by triplication redundancy scheme and the present invention the most again Do not realize these benchmark test circuit, be allowed to that there is capability of resistance to radiation；Respectively these are used the base of different schemes realization Quasi-test circuit random radiation 1000 times, the test wrong frequency of gained, area and power consumption meansigma methods such as table 2 institute Show；Area and power consumption in table 2 have passed through normalized, and its numerical value is circuit realized relative to the present invention program Area and the multiple of power consumption.Show from result shown in table 2, use mistake frequency in the method for the present invention minimum (mistake frequency is 0), so capability of resistance to radiation is the strongest, and the area of the present invention and power consumption are superfluous with three traditional moulds Area and the power consumption of remaining radioprotective scheme are close.

Table 2 area, power consumption and capability of resistance to radiation compare

Scheme	Mistake frequency	Area	Power consumption
				Traditional standard method for designing without capability of resistance to radiation	253	0.42	0.37
The radiation-hardened design method of the present invention	0	1	1
				The radiation-hardened design method of triplication redundancy	4	0.95	0.91

。

Claims (3)

1. one kind based on nor gate and the preparation method of the radioprotective latch with door, it is characterised in that use one or Not gate and one and door one elementary cell of composition, the most again with eight mutual stranded connections of elementary cell, construct one Radioprotective latch；It comprises the steps:

Step 1: according to circuit structure shown in Fig. 1, uses traditional integrated circuit method for designing design radioprotective latch electricity Road；

Step 2: operate the input end of clock CLK of latch in Fig. 1, makes data can write this latch, and This latch is made to have radioprotective characteristic.

2. the method as described in claim 1, it is characterised in that described step 1) in, by described circuit knot Structure, designs radioprotective latch circuit；Wherein nor gate N1 and with door A1 constitute first elementary cell；Nor gate N2 and with door A2 constitute second elementary cell；Nor gate N3 and constitute the 3rd elementary cell with door A3；Or it is non- Door N4 and constitute the 4th elementary cell with door A4；Nor gate N5 and constitute the 5th elementary cell with door A5； Nor gate N6 and constitute the 6th elementary cell with door A6；Nor gate N7 and with door A7 constitute the 7th the most single Unit；Nor gate N8 and constitute the 8th elementary cell with door A8；In elementary cell, nor gate realizes logic or non-functional, Logical AND function is realized with door；With the data input pin D that the input of door A1, A3, A5 and A7 is latch With input end of clock CLK, outfan is respectively D1, D3, D5 and D7；The data input pin D of latch is through anti- The signal Db of inverse value is held in phase device V1 output；To be Db defeated with clock with the input of door A2, A4, A6 and A8 Enter to hold CLK, outfan to be respectively D2, D4, D6 and D8；The input of nor gate N1-N8, outfan such as table Shown in 1；When input end of clock CLK value is 1, the value of data input pin D and phase inverter V1 outfan Db's Value (Db value is the inverse value of D) write latch, the value of data output end Q is the value of input D；Work as clock When input CLK value is 0, D and the Db value of write is stored in the memory node C1-C7 and outfan Q of latch； Memory node C1, C2, C3 and the value of data output end Q storage D, memory node C4, C5, C6, C7 store The value of number Db；If any one nodal value is because of radiation generation temporarily in memory node C1-C7 and data output end Q Change, other node of mutual stranded connection can suppress this change by nor gate, and effect to be irradiated makes after disappearing to send out The node of raw mistake change recovers right value in the past；

The input of table 1 nor gate and output

Nor gate Input Output

N1 C3、Q、D1 C4 N2 C6、C4、D2 Q N3 Q、C1、D3 C5 N4 C7、C5、D4 C1 N5 C1、C2、D5 C6 N6 C4、C6、D6 C2 N7 C2、C3、D7 C7 N8 C5、C7、D8 C3

。

3. the method as described in claim 1, it is characterised in that described step 2) including:

Latch shown in Fig. 1, this latch has both of which: write data, stable storage data；

Wherein, if latch is under write-ining data mode, input end of clock CLK value is set to 1, data input pin The value of D and value (Db value is the inverse value of D) the write latch of Db, the value of data output end Q is input D Value；

If latch is under stable storage data pattern, input end of clock CLK value is set to 0, write latch D and Db value is stored in the memory node C1-C7 and outfan Q of latch；Memory node C1, C2, C3 and data The value of outfan Q storage D, the value of memory node C4, C5, C6, C7 storage Db；If memory node C1-C7 Temporarily change, other node meeting of mutual stranded connection is there is because of radiation with any one nodal value in data output end Q Suppress this change by nor gate, effect to be irradiated making after disappearing to make a mistake the node of change recover before correct Value.