CN110377967B - Low-overhead reinforcement method for anti-single event error of combinational logic circuit - Google Patents
Low-overhead reinforcement method for anti-single event error of combinational logic circuit Download PDFInfo
- Publication number
- CN110377967B CN110377967B CN201910563659.0A CN201910563659A CN110377967B CN 110377967 B CN110377967 B CN 110377967B CN 201910563659 A CN201910563659 A CN 201910563659A CN 110377967 B CN110377967 B CN 110377967B
- Authority
- CN
- China
- Prior art keywords
- door
- circuit
- node
- error probability
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The invention discloses a low-overhead reinforcement method for a combinational logic circuit to resist single event errors, which comprises the following steps: firstly, reading a netlist file of a circuit to be reinforced, numbering nodes in sequence, and obtaining the connection relation of all gates and nodes from input to output of the circuit; then presetting the door error probability of each door; calculating according to the second step to obtain the door weighting error probability of each door, and aiming at a certain node, obtaining the soft error probability of the node so as to obtain the soft error probability density of the node; and finally, for each output node of the circuit, generating a soft error probability density sorting table of all nodes in the circuit aiming at a certain circuit to obtain the node corresponding to the minimum item in the sorting table, selecting all gates between the node and the output node for reinforcement, carrying out the same operation on each circuit, finally merging all the circuits and outputting a selective reinforced circuit netlist.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a low-overhead reinforcement method for a combinational logic circuit to resist single event errors.
Background
When the chip is in severe radiation environments such as outer space and the like, the single event upset of data of the memory can be caused by high-energy particle striking, and the single event transient pulse error of the combinational logic circuit can also be caused. With the rapid development of microelectronics and modern manufacturing processes, the size of integrated circuits is continuously decreasing. Meanwhile, the radiation environment has an increasing influence on the nano-scale CMOS circuit, resulting in a decrease in the reliability of the CMOS device. Therefore, more and more people are concerned about how to strengthen the combinational logic circuit to improve the single event resistance reliability of the circuit.
A common method is triple modular redundancy, i.e. the entire logic circuit is duplicated in two parts and then connected to a voter together with the original circuit. The method can effectively improve the reliability of output, but brings huge power consumption and area overhead. Partial fault tolerance techniques, i.e. selective hardening of the original circuit, are another way to deal with the above problems. Therefore, it is important to reduce the area and power consumption to the maximum extent on the basis of improving the reliability of the circuit as much as possible. .
Disclosure of Invention
Aiming at the problems, the invention provides a low-overhead reinforcement method for the resistance of the combinational logic circuit to the single event error, which reduces the area and power consumption overhead brought by the traditional triple-modular redundancy mode while improving the reliability of the resistance of the circuit to the single event.
In order to realize the technical scheme, the invention provides a low-overhead reinforcement method for a combinational logic circuit to resist single event errors, which is characterized by comprising the following steps of:
the method comprises the following steps: reading a netlist file of a circuit to be reinforced, numbering nodes in sequence, and obtaining the connection relation of all gates and nodes from input to output of the circuit;
step two: presetting the door error probability of each door, calculating the sum of fan-in and fan-out of each door, and multiplying the sum by the door error probability of the door to obtain the door weighting error probability of the door;
step three: calculating the door weighting error probability of each door according to the second step, accumulating the door weighting error probabilities of all the doors which are input to the node from the beginning of input aiming at a certain node to obtain the soft error probability of the node, and dividing the soft error probability by the number of all the doors which are input to the node to obtain the soft error probability density of the node;
step four: and for each output node of the circuit, all the gates which are fanned in from the input start form a line, the soft error probability density of each node is obtained according to the calculation of the third step, a soft error probability density sorting table of all the nodes in the line is generated for a certain line, the node corresponding to the minimum item in the sorting table is obtained, all the gates between the node and the output node are selected for reinforcement, the same operation is carried out on each line, and finally all the lines are merged, and the selective reinforcement circuit netlist is output.
The further improvement is that: in the second step, the door error probability is the probability of soft error of a single door under the radiation condition, the door error probability of a certain door is multiplied by the sum of fan-in and fan-out of the certain door to obtain the door weighting error probability, and both the door error probability and the door weighting error probability are only related to the door.
The further improvement is that: in step three, starting from the input of the circuit, the soft error generated by each gate in the radiation environment is transmitted to the next gate, and finally the soft error is accumulated to be the probability of the soft error generated by the output of the circuit; in effect, the soft error probability shows the probability of soft errors occurring at each node in the circuit.
The further improvement is that: in the combinational logic circuit of the fourth step, compared with the gate close to the input, the gate close to the output has a larger probability of causing output errors when soft errors occur, when all gates from the node corresponding to the minimum item of the sorting table to the output node are reinforced, the requirement of improving the reliability of the circuit as much as possible on the basis of reducing the area loss and optimizing the traditional TMR can be met, the same operation is carried out on each line, all the lines are finally merged, the selective reinforcement circuit netlist is output, and if a certain gate is shared by two or more lines and the selective reinforcement netlist output by one line comprises the gate, the gate is contained in the final selective reinforcement circuit netlist.
The invention has the beneficial effects that: the low-overhead reinforcement method for the resistance of the combinational logic circuit to the single event errors improves the reliability of the circuit to the single event errors and reduces the area and power consumption overhead brought by the traditional triple-modular redundancy mode.
Drawings
FIG. 1 is a schematic diagram of a combinational logic circuit according to the present invention.
Fig. 2 is a schematic diagram of a circuit 1 of a combinational logic circuit according to the present invention.
FIG. 3 is a schematic diagram of a circuit 2 of a combinational logic circuit according to the present invention.
Fig. 4 is a schematic diagram of a reinforcing circuit of line 1 of a combinational logic circuit according to the present invention.
Fig. 5 is a schematic diagram of a reinforcing circuit for line 2 of a combinational logic circuit according to the present invention.
FIG. 6 is a schematic diagram of a selective reinforcement circuit for a combinational logic circuit.
Detailed Description
In order to further understand the present invention, the following detailed description will be made with reference to the following examples, which are only used for explaining the present invention and are not to be construed as limiting the scope of the present invention.
The embodiment provides a low-overhead reinforcement method for a combinational logic circuit to resist single event errors, which comprises the following steps:
the method comprises the following steps: reading a netlist file of a circuit to be reinforced, numbering nodes in sequence, and obtaining the connection relation of all gates and nodes from input to output of the circuit;
step two: presetting the door error probability q of each door 1 Calculating the sum m of fan-in and fan-out of a certain door i Multiplying the gate error probability of the gate to obtain a gate weighted error probability q of the gate 2 The same operation is carried out on all the doors, the door error probability is the probability of soft error of a single door under the radiation condition, the door error probability of a certain door is multiplied by the sum of fan-in and fan-out of the door to obtain the door weighting error probability, and the door error probability and the door weighting error probability are only related to the door;
step three: according to the door weighting error probability of each door calculated in the second step, the door weighting error probabilities of all the doors entering the node from the input are accumulated aiming at a certain node, and the soft error probability q of the node is obtained r Dividing the soft error probability by the number n of all the doors fanning into the node to obtain the soft error probability density P of the node r Starting from circuit input, soft errors generated by each gate in a radiation environment are transmitted to the next gate, and finally, the soft errors are accumulated to be the probability of the soft errors generated by circuit output;
step four: for each output node of the circuit, all the gates which are fanned in from the input form a line, the soft error probability density of each node is obtained through calculation in the step three, a soft error probability density sorting table of all the nodes in the line is generated for a certain line, the node corresponding to the minimum term in the sorting table is obtained, and in the combinational logic circuit, compared with the gate close to the input, the output error is caused by the more probable rate when the gate close to the output generates the soft error. When all the gates between the node corresponding to the minimum item of the sorting table and the output node are reinforced, the requirement of improving the reliability of the circuit as much as possible on the basis of reducing the area loss and optimizing the traditional TMR can be met, the same operation is carried out on each line, and finally all the lines are combined to output the selective reinforced circuit netlist. If a gate is shared by two or more lines and the gate is included in the selectively reinforced netlist output by one of the lines, then the gate should be included in the final selectively reinforced circuit netlist.
As shown in FIG. 1, a combinational logic circuit includes five inputs a, b, c, d, e and two outputs O 1 、O 2 . The circuit of fig. 1 is split into two lines, which are respectively marked as line 1 and line 2, where line 1 includes O 1 All gates of the output node, line 2 containing O 2 All of the fan-in gates of the output nodes are as shown in fig. 2 and 3.
First, a door error probability q of each door is set in advance 1 ：
q 1 (AND_2)＝0.1
q 1 (NAND_2)＝0.08
q 1 (NOR_2)＝0.02
The probability of a door error for a certain door multiplied by the sum m of the fan-in and fan-out of that door i Obtaining a gate weighted error probability q 2 As shown in formula (1):
q 2 (i)＝q 1 (i)×m i (1)
then in the circuit shown in figure 2,
q 2 (AND_2)＝0.1×3＝0.3
q 2 (NAND_2)＝0.08×3＝0.24
q 2 (NOR_2)＝0.02×3＝0.06
secondly, calculating the soft error probability q of a certain node according to the door weighting error probability r ，q r Dividing the number n of all the doors entering the node to obtain the soft error probability density P of the node r As shown in formula (2):
then in the line 1 shown in figure 2,
it can be seen that the soft error probability densities of nodes ii, iii, and v are all the smallest in line 1, and the area loss should be minimized on the basis of reducing the soft error occurrence probability, so that the circuit from node v to the output is selected for reinforcement. The optional reinforcing circuit of the output is shown in solid line part in fig. 5.
Similarly, in line 2 of fig. 3,
it can be seen that node ii has the lowest soft error probability density in line 2, so the circuit from node ii to the output is selected for reinforcement. The optional reinforcing circuit of the output is shown in solid line part in fig. 5.
And finally, combining the two output selective reinforcement circuits to output a final selective reinforcement circuit netlist, as shown in fig. 6. It should be noted that, a NAND _2 gate is shared by the two lines, and since this gate belongs to the selective reinforcement circuit in line 2, this gate should be included in the final output selective reinforcement circuit netlist.
The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (4)
1. A low-overhead reinforcement method for a combinational logic circuit to resist single event errors is characterized by comprising the following steps:
the method comprises the following steps: reading a netlist file of a circuit to be reinforced, numbering nodes in sequence, and obtaining connection relations of all gates and nodes from input to output of the circuit;
step two: presetting the door error probability of each door, calculating the sum of fan-in and fan-out of each door, and multiplying the sum by the door error probability of the door to obtain the door weighting error probability of the door;
step three: calculating the door weighting error probability of each door according to the second step, accumulating the door weighting error probabilities of all the doors which are input to the node from the beginning of input aiming at a certain node to obtain the soft error probability of the node, and dividing the soft error probability by the number of all the doors which are input to the node to obtain the soft error probability density of the node;
step four: and for each output node of the circuit, all the gates which are fanned in from the input start form a line, the soft error probability density of each node is obtained according to the calculation of the third step, a soft error probability density sorting table of all the nodes in the line is generated for a certain line, the node corresponding to the minimum item in the sorting table is obtained, all the gates between the node and the output node are selected for reinforcement, the same operation is carried out on each line, and finally all the lines are merged, and the selective reinforcement circuit netlist is output.
2. The method according to claim 1, wherein the method comprises the following steps: in the second step, the door error probability is the probability of soft error of a single door under the radiation condition, the door error probability of a certain door is multiplied by the sum of fan-in and fan-out of the certain door to obtain the door weighting error probability, and both the door error probability and the door weighting error probability are only related to the door.
3. The method according to claim 1, wherein the method for reinforcing the low-overhead combinational logic circuit against the single event errors comprises the following steps: in step three, starting from the circuit input, the soft error generated by each gate in the radiation environment is transmitted to the next gate, and finally, the soft error is accumulated into the probability of the soft error generated by the circuit output.
4. The method according to claim 1, wherein the method for reinforcing the low-overhead combinational logic circuit against the single event errors comprises the following steps: in the combinational logic circuit of the fourth step, compared with the gate close to the input, the gate close to the output has a larger probability of causing output errors when soft errors occur, when all gates from the node corresponding to the minimum item of the sorting table to the output node are reinforced, the requirement of improving the reliability of the circuit as much as possible on the basis of reducing the area loss and optimizing the traditional TMR can be met, the same operation is carried out on each line, all the lines are finally merged, the selective reinforcement circuit netlist is output, and if a certain gate is shared by two or more lines and the selective reinforcement netlist output by one line comprises the gate, the gate is contained in the final selective reinforcement circuit netlist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910563659.0A CN110377967B (en) | 2019-06-26 | 2019-06-26 | Low-overhead reinforcement method for anti-single event error of combinational logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910563659.0A CN110377967B (en) | 2019-06-26 | 2019-06-26 | Low-overhead reinforcement method for anti-single event error of combinational logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110377967A CN110377967A (en) | 2019-10-25 |
| CN110377967B true CN110377967B (en) | 2022-12-13 |
Family
ID=68250975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910563659.0A Active CN110377967B (en) | 2019-06-26 | 2019-06-26 | Low-overhead reinforcement method for anti-single event error of combinational logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110377967B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112671378B (en) * | 2020-12-24 | 2023-04-14 | 中国人民解放军国防科技大学 | Frequency-loss-free integrated circuit single event upset resistance reinforcing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108320767A (en) * | 2018-02-12 | 2018-07-24 | 河海大学常州校区 | A kind of selective reinforcement means of combinational logic circuit anti-single particle mistake |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070226572A1 (en) * | 2005-11-07 | 2007-09-27 | Ming Zhang | Soft error rate analysis system |
-
2019
- 2019-06-26 CN CN201910563659.0A patent/CN110377967B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108320767A (en) * | 2018-02-12 | 2018-07-24 | 河海大学常州校区 | A kind of selective reinforcement means of combinational logic circuit anti-single particle mistake |
Non-Patent Citations (1)
| Title |
|---|
| 基于CVSL结构的组合逻辑选择性加固方案;韩健等;《合肥工业大学学报(自然科学版)》;20141228(第12期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110377967A (en) | 2019-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6910173B2 (en) | Word voter for redundant systems | |
| US6963217B2 (en) | Method and apparatus for creating circuit redundancy in programmable logic devices | |
| US6396307B1 (en) | Semiconductor integrated circuit and method for designing the same | |
| US20100205571A1 (en) | Synchronous to asynchronous logic conversion | |
| WO2018218898A1 (en) | Anti-single event transient clock tree structure | |
| Saha et al. | DPL-based novel binary-to-ternary converter on CMOS technology | |
| Sirisantana et al. | Enhancing yield at the end of the technology roadmap | |
| CN105574270B (en) | A kind of anti-single particle reinforcing circuit unit placement-and-routing method | |
| CN110377967B (en) | Low-overhead reinforcement method for anti-single event error of combinational logic circuit | |
| JP2007124343A (en) | Data-holding circuit | |
| CN105334906A (en) | Multistage gated clock network optimization method in nanometer technology | |
| CN109408839B (en) | Radiation-resistant fault-tolerant FPGA circuit design method for reducing sensitive configuration bits through local redundancy | |
| CN108320767B (en) | Selective reinforcement method for single event error resistance of combined logic circuit | |
| Ayache et al. | A reliability model for error correcting memory systems | |
| Chen et al. | A statistical reliability model for single-electron threshold logic | |
| JP3095229B2 (en) | Microprocessors and complex logic circuits | |
| Singh et al. | Evaluation of circuit reliability based on distribution of different signal input patterns | |
| CN108304278B (en) | Protection method for optimal redundancy allocation of engineering code modules based on improved modular factorial algorithm | |
| Rafiee et al. | Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications | |
| US11144697B1 (en) | Processing method for applying analog dynamic circuit to digital testing tool | |
| Shen et al. | Reliability enhanced data processing system capable of runtime fault recovery | |
| Guo et al. | A CMOS majority logic gate and its application to one-step ML decodable codes | |
| KR102505200B1 (en) | Ternary logic circuit device | |
| Parhami | Recursive Implementation of Voting Networks | |
| Kuang et al. | Low power operation using self-timed circuits and ultra-low supply voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |