CN102176322A - Single-event-proximity-effect-resistant static storage unit of physical space interleaving type - Google Patents
Single-event-proximity-effect-resistant static storage unit of physical space interleaving type Download PDFInfo
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- CN102176322A CN102176322A CN 201110031829 CN201110031829A CN102176322A CN 102176322 A CN102176322 A CN 102176322A CN 201110031829 CN201110031829 CN 201110031829 CN 201110031829 A CN201110031829 A CN 201110031829A CN 102176322 A CN102176322 A CN 102176322A
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Abstract
The invention discloses a single-event-proximity-effect-resistant static storage unit of a physical space interleaving type. The static storage unit comprises a transistor of a storage unit A and a transistor of a storage unit B, wherein the transistor of storage unit A is composed of a first access transistor AMG1 of the storage unit A, a second access transistor AMG2 of the storage unit A, a first pull-up transistor AMP1 of the storage unit A, a second pull-up transistor AMP2 of the storage unit A, a first pull-down transistor AMN1 of the storage unit A and a second pull-down transistor AMN2 of the storage unit A, which are arranged on a silicon substrate; and the transistor of the storage unit B is composed of a first access transistor BMG1 of the unit B, a second access transistor BMG2 of the unit B, a first pull-up transistor BMP1 of the unit B, a second pull-up transistor BMP2 of the unit B, a first pull-down transistor BMN1 of the unit B and a second pull-down transistor BMN2 of the unit B, which are arranged on the silicon substrate. Proximity effect can be effectively reduced by adopting the invention, and therefore, the critical charges of SEU (Single Event Upset) of the storage units are enlarged to enhance the single event resistance.
Description
Technical field:
The invention belongs to the static memory field, relate to a kind of static storage cell, especially a kind of static storage cell of physical space alternating expression anti-single particle approach effect.
Background technology:
Along with CMOS technology characteristics size and supply voltage continue to reduce, make cmos device face great reliability challenge.The single-particle inversion of cmos memory cell (SEU) is exactly one of challenge.When particle incides the sensitizing range (drain region of the NMOS that normally closes) of storage unit, thereby transistor is collected the content that electric charge changes cell stores in the storage unit, claims that at this moment SEU has taken place storage unit.
The progress of semiconductor CMOS technology makes device dimensions shrink, and the distance in storage unit between the transistor is more and more littler, and approach effect is more and more serious.After so-called approach effect is meant particle incident, a plurality of transistors in the storage unit are exerted an influence.Approach effect has two classes, and a class is that particle is incident in the trap, and a plurality of transistors that are positioned at trap are exerted an influence simultaneously.Another kind of is after particle is incident on the transistor drain that is positioned at substrate, to pass well region again; Perhaps the diameter that influences of particle directly covers in the well region and the outer transistor of well region, and the two all can influence a plurality of transistors of a storage unit simultaneously.
For common interlocking storage organization, traditional SEU is meant that the node of storage 1 state is pulled to 0, and making the upset of storage 0 state complementary node then is 1, finishes once inside out; Vice versa.To this storage unit, along with the reduction of unit size, the second class approach effect odds is increasing.The particle incident of approach effect taking place, can make the node of storage 1 state pull to 0, makes the node of storage 0 state pull to 1, the unit upset.For this upset, required projectile energy is lower.Because the storage unit of interlocking can be amplified the energizing signal that both sides occur, upset is more prone to, required particle energy has just reduced.Along with semiconductor technology enters 45nm and following process node, approach effect will make low energy particles a large amount of on the ground become SEU generation source, reduces device reliability.
The domestic and international research emphasis all is placed on the first kind approach effect at present, and has proposed some solutions.Domestic article " the single-particle radiation electric charge of 130nm nmos device is shared effect " (the 35th volume first phase of semiconductor technology) has carried out simulation analysis to first kind approach effect, and points out that protection ring has inhibiting effect to approach effect.Protection ring can be used in register or the common storage unit, and area overhead is big, is unsuitable for being used in the high storage array of density.The domestic article of also not seeing about the second class approach effect.The electric charge approach effect is also concentrated on the first kind at present abroad, article " Multiple bit upsets and error mitigation in ultra-deep submicron SRAMs " (IEEE TRANSACTIONSON NUCLEAR SCIENCE, VOL.55, NO.6, DECEMBER 2008) mainly set forth in the well region electric charge and shared effect.Article " Mitigation techniques for single event induced charge sharing in a 90nm bulk CMOS process " (IEEE TRANSACTIONS ON DEVICEAND MATERIALS RELIABILITY; VOL.9; NO.2; JUNE 2009) mainly set forth and how from domain, the storage unit of radiation hardening such as the electric charge in the DICE unit inhibition well region to have been shared effect; as increase protection ring, increase distance between sensitive nodes etc.
Along with further dwindling of process, in the SRAM storage unit, it will be more and more serious that the electric charge that the second class approach effect causes is shared, and also not propose concrete solution at present.
Summary of the invention:
The technical matters that the present invention solves is: suppress to dwindle the second serious day by day class approach effect because of process, provide a kind of area overhead the little memory cell structure that is applicable to storage array.
Substantially the thinking that instructs of the present invention is as described below.To a kind of storage unit of symmetrical structure, when realizing on physical layout, two unit that need draw simultaneously might as well remember that a unit is A, and another unit is B.Because A and B unit are symmetrical, so the A storage unit can be divided into 0.5A and 0.5A, the B unit is also similar.Common storage unit when physical layout is realized, has been adopted the arrangement mode of 0.5A, 0.5A, 0.5B, 0.5B.In order to increase the distance of two the sensing crystal pipes (N pipe of promptly closing and the P pipe of closing) in the unit, thereby reduce the influence of the second class approach effect, adopted staggered the putting of mode of 0.5A, 0.5B, 0.5A, 0.5B, between first 0.5A and second 0.5A, realize being connected at last with metal, between first 0.5B and second 0.5B, realize being connected, finished the physics realization of 2 unit like this with metal.
Two sensing crystal pipes in common 6 transistor memory units are arranged in the diagonal position of rectangle domain, suppose that the horizontal range of two sensing crystal pipes equates with vertical range, are a, and then two sensing crystal pipe diagonal distance are 1.414a.By the domain that adopts the present invention to realize, horizontal range has become 2a, and vertical range is constant, and then two sensing crystal pipe diagonal distance are 2.236.At first on physical space, increase distance, reduced the probability of approach effect, promptly had only the incident of wide-angle specific direction just serious approach effect may take place.
To the 180nm of SMIC, 1.8V technology has been carried out electric charge and has been injected emulation, is used to simulate various particle condition of incidence.Single node (10: 0) electric charge injects and is used to simulate the vertical particle incident that no electric charge is shared effect, binode (7: 3) electric charge injects to be used to simulate and has the particle incident that electric charge is shared effect, and vast scale binode (9: 1) electric charge injects and is used to simulate effect of the present invention.According to the result of emulation, drawn the SEU critical charge 62,45 and the 60fC of three kinds of situations respectively.Above emulation as seen, the binode charge-trapping can effectively reduce the critical charge of storage unit.Adopt the present invention can effectively reduce approach effect, thereby increase the critical charge of storage unit SEU, improve the anti-single particle performance.
Description of drawings:
Fig. 1 is traditional 12T double memory cell circuit diagram.
Fig. 2 is a planimetric map.
Fig. 3 is a planimetric map.
Description of reference numerals:
210,220,223,230,233,240,243,250,253,261,263,271,273,281～the first metal layer M1 interconnection line;
311,321,331,341,352,355,361,365～the second metal level M2 interconnection lines;
353,357,363,367～the 3rd metal level M3 interconnection lines;
214,216,221,222,224,231,232,234,241,242,244,251,252,254,260,262,270,272,280,282～polycrystalline and active contact hole to M1;
310,312,320,322,330,332,340,342,350,354,360,364～M1 is to the M2 through hole;
351,356,362,366～M2 is to the through hole of M3;
270～n well;
290～double memory cell;
AB～A storage unit bit line;
ABN～A storage unit paratope line;
The bit line of BB～B storage unit;
The paratope line of BBN～B storage unit;
AMN1～A storage unit first pull-down transistor;
AMP1～A storage unit first pulls up transistor;
AMG1～A storage unit first access transistor;
AMN2～A storage unit second pull-down transistor;
AMP2～A storage unit second pulls up transistor;
AMG2～A storage unit second access transistor;
First pull-down transistor of BMN1～B storage unit;
First of BMP1～B storage unit pulls up transistor;
First access transistor of BMG1～B storage unit;
Second pull-down transistor of BMN2～B storage unit;
Second of BMP2～B storage unit pulls up transistor;
Second access transistor of BMG2～B storage unit;
WL～word line.
Embodiment:
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Referring to Fig. 1-3, referring to Fig. 1, comprise 26 pipe SRAM storage unit in this synoptic diagram, promptly 12 manage two SRAM storage unit, these two storage unit are called A storage unit and B storage unit.Being that the line and the device of beginning belongs to the A storage unit with alphabetical A wherein, is that the line and the device of beginning belongs to the B storage unit with the letter b.Because storage unit left-right symmetric, so for convenience of description, we split into 4 parts with two storage unit in this synoptic diagram, promptly the A storage unit splits into 0.5A and 0.5A along the center line of symmetry, and the B storage unit splits into 0.5B and 0.5B along the center line of symmetry.These four parts no longer are 0.5A, 0.5A, and 0.5B, 0.5B series arrangement, but 0.5A, 0.5B, 0.5A, 0.5B is staggered like this, has formed and the corresponding relation in domain position.Generally speaking, interlocking 6 transistor memory unit comprise the first access transistor AMG1, the second access transistor AMG2, first pull up transistor AMP1, second pull up transistor AMP2, the first pull-down transistor AMN1 and the second pull-down transistor AMN2, promptly among Fig. 1 all with the transistor of A beginning of letter.
Fig. 2 and Fig. 3 are the 12 pipe double memory cell layout planimetric maps of one embodiment of the invention.Fig. 2 has shown contact hole, the ground floor metal M 1 layout planimetric map of active area, polysilicon, active and polycrystalline and ground floor metal M 1; Fig. 3 has shown ground floor metal M 1, second layer metal M2 and three-layer metal M3.
See also Fig. 2 now, this 12 pipe double memory cell layout planimetric map comprises the A storage unit first access transistor AMG1, the A storage unit second access transistor AMG2, the A storage unit first that are formed on the silicon substrate pull up transistor AMP1, A storage unit second pull up transistor AMP2, the A storage unit first pull-down transistor AMN1 and the A storage unit second pull-down transistor AMN2, i.e. whole A memory cell transistors; Also comprise the B unit first access transistor BMG1, the B unit second access transistor BMG2, the B unit first that are formed on the silicon substrate pull up transistor BMP1, B unit second pull up transistor BMP2, the B unit first pull-down transistor BMN1 and the B unit second pull-down transistor BMN2, i.e. whole transistors of B storage unit.For convenience of description, the figure that includes tiny stain is an active area, and the figure that includes empty oblique line is a polysilicon, the interconnection line of unfilled thick line diagrammatic representation ground floor metal M 1.And above-mentioned silicon substrate can be＜110〉bulk silicon,＜100〉bulk silicon, material such as silicon (SOI) or non-bulk silicon on the germanium silicon, strained silicon, insulation course.The maximum channel length of the technology that the present invention is suitable for is 350nm, preferable transistor channel length 90nm, and along with the development of technology, this method still is suitable for, and channel length is more little, and the anti-single particle effect of using this method to obtain is remarkable more.
The preferably, A storage unit first AMP1, A storage unit second AMP2, B unit first BMP1, B unit second BMP2 that pulls up transistor that pulls up transistor that pulls up transistor that pulls up transistor is the PMOS transistor that is formed at n trap 270 or dark n trap, and other transistor then is a nmos pass transistor.A storage unit first AMP1, A storage unit second AMP2, B unit first the pull up transistor source electrode of BMP2 of BMP1 and B unit second that pulls up transistor that pulls up transistor that pulls up transistor is connected together with the voltage source V CC interconnection line 210 that is positioned at the M1 layer with 216 via active contact hole 214 to the first metal layer M1 respectively.
The pull up transistor drain electrode of AMP1, the drain electrode of the first pull-down transistor AMN1, the drain electrode of the first access transistor AMG1 of A storage unit first is connected together with the first memory node AN1 interconnection line 220 that is positioned at the M1 layer with 222 via active contact hole 221 to the first metal layer M1; Second grid that pulls up transistor AMP2 is connected together with the first memory node AN1 interconnection line 223 that is positioned at the M1 layer via the contact hole 224 of polycrystalline to the first metal layer M1 with the grid of the second pull-down transistor AMN2.See also Fig. 3 now, for convenience of description, the interconnection line of unfilled thick line diagrammatic representation ground floor metal M 1 includes the interconnection line of the diagrammatic representation second metal level M2 of oblique line, includes the diagrammatic representation three-layer metal line of thick stain.As seen from Figure 3, the M1 interconnection line 220 of AN1 is connected on the first memory node AN1 interconnection line 311 that is positioned at the M2 layer to the through hole 310 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 223 of AN1 also is connected on the first memory node AN1 interconnection line 311 that is positioned at the M2 layer to the through hole 312 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two AN1 interconnection lines like this on the second metal level M2.Get back to Fig. 2, the pull up transistor drain electrode of AMP2, the drain electrode of the second pull-down transistor AMN2, the drain electrode of the second access transistor AMG2 of A storage unit second is connected together with the second memory node AN2 interconnection line 230 that is positioned at the M1 layer with 232 via active contact hole 231 to the first metal layer M1; First grid that pulls up transistor AMP1 is connected together with the second memory node AN2 interconnection line 233 that is positioned at the M1 layer via the contact hole 234 of polycrystalline to the first metal layer M1 with the grid of the first pull-down transistor AMN1.Fig. 3 again, the M1 interconnection line 233 of AN2 is connected on the second memory node AN2 interconnection line 321 that is positioned at the M2 layer to the through hole 320 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 230 of AN2 is connected on the second memory node AN2 interconnection line 321 that is positioned at the M2 layer to the through hole 322 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two AN2 interconnection lines like this on the second metal level M2.
The pull up transistor drain electrode of BMP1, the drain electrode of the first pull-down transistor BMN1, the drain electrode of the first access transistor BMG1 of B unit first is connected together with the first memory node BN1 interconnection line 240 that is positioned at the M1 layer with 242 via active contact hole 241 to the first metal layer M1; Second grid that pulls up transistor BMP2 is connected together with the first memory node BN1 interconnection line 243 that is positioned at the M1 layer via the contact hole 244 of polycrystalline to the first metal layer M1 with the grid of the second pull-down transistor BMN2.See also Fig. 3 now, the M1 interconnection line 240 of BN1 is connected on the first memory node BN1 interconnection line 331 that is positioned at the M2 layer to the through hole 330 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 243 of BN1 also is connected on the first memory node BN1 interconnection line 331 that is positioned at the M2 layer to the through hole 332 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two BN1 interconnection lines like this on the second metal level M2.Get back to Fig. 2, the pull up transistor drain electrode of BMP2, the drain electrode of the second pull-down transistor BMN2, the drain electrode of the second access transistor BMG2 of B unit second is connected together with the second memory node BN2 interconnection line 250 that is positioned at the M1 layer with 252 via active contact hole 251 to the first metal layer M1; First grid that pulls up transistor BMP1 is connected together with the second memory node BN2 interconnection line 253 that is positioned at the M1 layer via the contact hole 254 of polycrystalline to the first metal layer M1 with the grid of the first pull-down transistor BMN1.See also Fig. 3 now, the M1 interconnection line 250 of BN2 is connected on the second memory node BN2 interconnection line 341 that is positioned at the M2 layer to the through hole 342 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 253 of BN2 is connected on the second memory node BN2 interconnection line 341 that is positioned at the M2 layer to the through hole 340 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two BN2 interconnection lines like this on the second metal level M2.
In Fig. 2, the source electrode of the A storage unit first access transistor AMG1 is realized electrically connecting with the interconnection line 261 of the bit line AB that is positioned at the M1 layer by active contact hole 260 to the first metal layer M1.The first access transistor AMG1 and bit line AB electrical couplings to the first the pull up transistor drain electrode of AMP1 and the drain electrode of the first pull-down transistor AMN1.The source electrode of the A storage unit second access transistor AMG2 is realized electrically connecting with the interconnection line 263 of the complementary bit line ABN that is positioned at the M1 layer by active contact hole 262 to the first metal layer M1.The second access transistor AMG2 and complementary bit line ABN electrical couplings to the second the pull up transistor drain electrode of AMP2 and the drain electrode of the second pull-down transistor AMN2.
The source electrode of the first access transistor BMG1 of B unit is realized electrically connecting with the interconnection line 271 of the bit line BB that is positioned at the M1 layer by active contact hole 270 to the first metal layer M1.The first access transistor BMG1 and bit line BB electrical couplings to the first the pull up transistor drain electrode of BMP1 and the drain electrode of the first pull-down transistor BMN1.The source electrode of the second access transistor BMG2 of B unit is realized electrically connecting with the interconnection line 273 of the complementary bit line BBN that is positioned at the M1 layer by active contact hole 272 to the first metal layer M1.The second access transistor BMG2 and complementary bit line BBN electrical couplings to the second the pull up transistor drain electrode of BMP2 and the drain electrode of the second pull-down transistor BMN2.
The grid polycrystalline of the first access transistor BMG1 of the A storage unit first access transistor AMG1, the A storage unit second access transistor AMG2, B unit, the second access transistor BMG2 of B unit connects together, realize interconnection with the WL word line that is positioned at the second metal level M2 343 shown in Figure 3 after this pair unit repeats certain number of times, the number of times of repetition depends on the resistance of polycrystalline resistance.In addition, also can take two unit to realize once interconnection with the WL word line, in addition can one the unit realize once interconnection with the WL word line, but may increase the area of unit like this, repeat no more here.
The source electrode of the A storage unit first pull-down transistor AMN1 has been realized electric connection by active contact hole 280 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage Vss of M1 layer, and the source electrode of the A storage unit second pull-down transistor AMN2 has been realized electric connection by active contact hole 282 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage VSS of M1 layer.And the source electrode of the first pull-down transistor BMN1 of B unit has been realized electric connection by active contact hole 280 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage Vss of M1 layer, and the source electrode of the second pull-down transistor BMN2 of B unit has been realized electric connection by active contact hole 282 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage VSS of M1 layer.
In Fig. 3, to the A storage unit, be positioned at the AB bit line 261 of the first metal layer M1, be connected to the AB bit line 352 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 350 of the second metal level M2, be connected on the AB bit line 353 that is positioned at the M3 layer by the through hole 351 that connects the second metal level M2 to the, three metal level M3 again.Be positioned at the ABN paratope line 263 of M1 layer, be connected to the ABN paratope line 355 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 354 of the second metal level M2, be connected to by the through hole 356 that connects the second metal level M2 to the, three metal level M3 again and be positioned on the M3 layer ABN paratope line 357.
To the B unit, be positioned at the BB bit line 271 of the first metal layer M1, be connected to the BB bit line 361 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 360 of the second metal level M2, be connected to by the through hole 362 that connects the second metal level M2 to the, three metal level M3 again and be positioned on the M3 layer BB bit line 363.Be positioned at the BBN paratope line 273 of M1 layer, be connected to the BBN paratope line 365 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 364 of the second metal level M2, be connected to by the through hole 366 that connects the second metal level M2 to the, three metal level M3 again and be positioned on the M3 layer BBN paratope line 367.
Above content is to further describing that the present invention did in conjunction with concrete preferred implementation; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of being submitted to.
Claims (10)
1. the static storage cell of physical space alternating expression anti-single particle approach effect, comprise A memory cell transistor and B memory cell transistor, it is characterized in that: the A memory cell transistor constitutes by being arranged at the A storage unit first access transistor AMG1, the A storage unit second access transistor AMG2, A storage unit first on the silicon substrate pull up transistor AMP2, the A storage unit first pull-down transistor AMN1 and the A storage unit second pull-down transistor AMN2 of AMP1, A storage unit second that pull up transistor; The B memory cell transistor also constitutes by being arranged at the B unit first access transistor BMG1, the B unit second access transistor BMG2, B unit first on the silicon substrate pull up transistor BMP2, the B unit first pull-down transistor BMN1 and the B unit second pull-down transistor BMN2 of BMP1, B unit second that pull up transistor.
2. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1 is characterized in that:
A storage unit first AMP1, A storage unit second AMP2, B unit first BMP1, B unit second BMP2 that pulls up transistor that pulls up transistor that pulls up transistor that pulls up transistor is the PMOS transistor that is formed at n trap 270 or dark n trap, and other transistor then is a nmos pass transistor; A storage unit first AMP1, A storage unit second AMP2, B unit first the pull up transistor source electrode of BMP2 of BMP1 and B unit second that pulls up transistor that pulls up transistor that pulls up transistor is connected together with the voltage source V CC interconnection line 210 that is positioned at the M1 layer with 216 via active contact hole 214 to the first metal layer M1 respectively;
The pull up transistor drain electrode of AMP1, the drain electrode of the first pull-down transistor AMN1, the drain electrode of the first access transistor AMG1 of A storage unit first is connected together with the first memory node AN1 interconnection line 220 that is positioned at the M1 layer with 222 via active contact hole 221 to the first metal layer M1; Second grid that pulls up transistor AMP2 is connected together with the first memory node AN1 interconnection line 223 that is positioned at the M1 layer via the contact hole 224 of polycrystalline to the first metal layer M1 with the grid of the second pull-down transistor AMN2.
3. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1 is characterized in that:
The M1 interconnection line 220 of the A storage unit first memory node AN1 is connected on the first memory node AN1 interconnection line 311 that is positioned at the M2 layer to the through hole 310 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 223 of AN1 also is connected on the first memory node AN1 interconnection line 311 that is positioned at the M2 layer to the through hole 312 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two AN1 interconnection lines like this on the second metal level M2.
4. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1 is characterized in that:
The pull up transistor drain electrode of AMP2, the drain electrode of the second pull-down transistor AMN2, the drain electrode of the second access transistor AMG2 of A storage unit second is connected together with the second memory node AN2 interconnection line 230 that is positioned at the M1 layer with 232 via active contact hole 231 to the first metal layer M1; First grid that pulls up transistor AMP1 is connected together with the second memory node AN2 interconnection line 233 that is positioned at the M1 layer via the contact hole 234 of polycrystalline to the first metal layer M1 with the grid of the first pull-down transistor AMN1.
5. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1, it is characterized in that: the M1 interconnection line 233 of the A storage unit second memory node AN2 is connected on the second memory node AN2 interconnection line 321 that is positioned at the M2 layer to the through hole 320 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 230 of AN2 is connected on the second memory node AN2 interconnection line 321 that is positioned at the M2 layer to the through hole 322 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two AN2 interconnection lines like this on the second metal level M2;
The pull up transistor drain electrode of BMP1, the drain electrode of the first pull-down transistor BMN1, the drain electrode of the first access transistor BMG1 of B unit first is connected together with the first memory node BN1 interconnection line 240 that is positioned at the M1 layer with 242 via active contact hole 241 to the first metal layer M1; Second grid that pulls up transistor BMP2 is connected together with the first memory node BN1 interconnection line 243 that is positioned at the M1 layer via the contact hole 244 of polycrystalline to the first metal layer M1 with the grid of the second pull-down transistor BMN2.
6. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1, it is characterized in that: the M1 interconnection line 240 of B unit B N1 is connected on the first memory node BN1 interconnection line 331 that is positioned at the M2 layer to the through hole 330 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 243 of BN1 also is connected on the first memory node BN1 interconnection line 331 that is positioned at the M2 layer to the through hole 332 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two BN1 interconnection lines like this on the second metal level M2.
7. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1 is characterized in that: the pull up transistor drain electrode of BMP2, the drain electrode of the second pull-down transistor BMN2, the drain electrode of the second access transistor BMG2 of B unit second is connected together with the second memory node BN2 interconnection line 250 that is positioned at the M1 layer with 252 via active contact hole 251 to the first metal layer M1; First grid that pulls up transistor BMP1 is connected together with the second memory node BN2 interconnection line 253 that is positioned at the M1 layer via the contact hole 254 of polycrystalline to the first metal layer M1 with the grid of the first pull-down transistor BMN1; The M1 interconnection line 250 of B unit B N2 is connected on the second memory node BN2 interconnection line 341 that is positioned at the M2 layer to the through hole 342 of the second metal level M2 by the first metal layer M1, and another M1 interconnection line 253 of BN2 is connected on the second memory node BN2 interconnection line 341 that is positioned at the M2 layer to the through hole 340 of the second metal level M2 by the first metal layer M1, has realized the interconnection of two BN2 interconnection lines like this on the second metal level M2.
8. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1, it is characterized in that: the source electrode of the A storage unit first access transistor AMG1 is realized electrically connecting with the interconnection line 261 of the bit line AB that is positioned at the M1 layer by active contact hole 260 to the first metal layer M1; The first access transistor AMG1 and bit line AB electrical couplings to the first the pull up transistor drain electrode of AMP1 and the drain electrode of the first pull-down transistor AMN1; The source electrode of the A storage unit second access transistor AMG2 is realized electrically connecting with the interconnection line 263 of the complementary bit line ABN that is positioned at the M1 layer by active contact hole 262 to the first metal layer M1.The second access transistor AMG2 and complementary bit line ABN electrical couplings to the second the pull up transistor drain electrode of AMP2 and the drain electrode of the second pull-down transistor AMN2;
The source electrode of the first access transistor BMG1 of B unit is realized electrically connecting with the interconnection line 271 of the bit line BB that is positioned at the M1 layer by active contact hole 270 to the first metal layer M1; The first access transistor BMG1 and bit line BB electrical couplings to the first the pull up transistor drain electrode of BMP1 and the drain electrode of the first pull-down transistor BMN1.The source electrode of the second access transistor BMG2 of B unit is realized electrically connecting with the interconnection line 273 of the complementary bit line BBN that is positioned at the M1 layer by active contact hole 272 to the first metal layer M1.The second access transistor BMG2 and complementary bit line BBN electrical couplings to the second the pull up transistor drain electrode of BMP2 and the drain electrode of the second pull-down transistor BMN2.
9. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1 is characterized in that:
The grid polycrystalline of the first access transistor BMG1 of the A storage unit first access transistor AMG1, the A storage unit second access transistor AMG2, B unit, the second access transistor BMG2 of B unit connects together, realize interconnection with the WL word line 343 that is positioned at the second metal level M2 after this unit repeats certain number of times, the number of times of repetition depends on the resistance of polycrystalline resistance;
The source electrode of the A storage unit first pull-down transistor AMN1 has been realized electric connection by active contact hole 280 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage Vss of M1 layer, and the source electrode of the A storage unit second pull-down transistor AMN2 has been realized electric connection by active contact hole 282 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage VSS of M1 layer; And the source electrode of the first pull-down transistor BMN1 of B unit has been realized electric connection by active contact hole 280 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage Vss of M1 layer, and the source electrode of the second pull-down transistor BMN2 of B unit has been realized electric connection by active contact hole 282 to the first metal layer M1 with the interconnection line 281 that is positioned at the ground voltage VSS of M1 layer.
10. the static storage cell of physical space alternating expression anti-single particle approach effect according to claim 1 is characterized in that:
In the A storage unit, be positioned at the AB bit line 261 of the first metal layer M1, be connected to the AB bit line 352 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 350 of the second metal level M2, be connected on the AB bit line 353 that is positioned at the M3 layer by the through hole 351 that connects the second metal level M2 to the, three metal level M3 again; Be positioned at the ABN paratope line 263 of M1 layer, be connected to the ABN paratope line 355 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 354 of the second metal level M2, be connected to by the through hole 356 that connects the second metal level M2 to the, three metal level M3 again and be positioned on the M3 layer ABN paratope line 357;
In the B unit, be positioned at the BB bit line 271 of the first metal layer M1, be connected to the BB bit line 361 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 360 of the second metal level M2, be connected to by the through hole 362 that connects the second metal level M2 to the, three metal level M3 again and be positioned on the M3 layer BB bit line 363; Be positioned at the BBN paratope line 273 of M1 layer, be connected to the BBN paratope line 365 that is positioned at the M2 layer by connecting the first metal layer M1 to the through hole 364 of the second metal level M2, be connected to by the through hole 366 that connects the second metal level M2 to the, three metal level M3 again and be positioned on the M3 layer BBN paratope line 367.
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