CN107393584A - A kind of single-ended reading memory cell of full swing based on FinFET - Google Patents
A kind of single-ended reading memory cell of full swing based on FinFET Download PDFInfo
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- CN107393584A CN107393584A CN201710462410.1A CN201710462410A CN107393584A CN 107393584 A CN107393584 A CN 107393584A CN 201710462410 A CN201710462410 A CN 201710462410A CN 107393584 A CN107393584 A CN 107393584A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention discloses a kind of single-ended reading memory cell of full swing based on FinFET,Including write word line,Write bit line,Anti-phase write bit line,Readout word line,Sense bit line,First FinFET is managed,2nd FinFET is managed,3rd FinFET is managed,4th FinFET is managed,5th FinFET is managed,6th FinFET is managed,7th FinFET is managed,8th FinFET is managed and the 9th FinFET pipes,First FinFET is managed,2nd FinFET is managed and the 7th FinFET pipes are respectively the p-type FinFET pipes of Low threshold,3rd FinFET is managed,4th FinFET is managed,5th FinFET is managed,6th FinFET is managed and the 9th FinFET pipes are respectively to be managed for the N-type FinFET of Low threshold,8th FinFET pipes are managed for the N-type FinFET of high threshold；Advantage is in the case where not influenceing circuit function, and delay, power consumption and power-consumption design are smaller, and data will not malfunction during read operation, and circuit stability is higher.
Description
Technical field
The present invention relates to a kind of memory cell, reads to store more particularly, to a kind of full swing based on FinFET is single-ended
Unit.
Background technology
As process enters nanoscale, power consumption turns into the problem of IC designer must not be not concerned with.In big portion
Point digital display circuit in memory power consumption occupy way circuit power consumption ratio it is increasing.Static RAM
(SRAM, Static Random Access Memory), is an important part in memory, thus is designed high
Stability low-power consumption SRAM has important Research Significance.Static RAM is mainly by storage array and other peripheries
Circuit is formed, and storage array is made up of memory cell, and memory cell is the core of static RAM, memory cell
Performance directly determine the performance of static RAM.
With the continuous diminution of transistor size, limited by short-channel effect and present production process, common CMOS
The space that transistor size reduces extremely reduces.When the size reduction of common CMOS transistor is to below 20nm, the leakage of device
Electric current can be increased drastically, cause larger circuit to leak power consumption.Also, circuit short-channel effect becomes readily apparent from, and device becomes
Rather unstable, it significantly limit the raising of circuit performance.FinFET manages (fin field-effect transistor, Fin Field-
Effect Transistor) it is that a kind of new CMOS (CMOS) transistor is a kind of new 3D transistors,
The raceway groove of FinFET pipes using zero doping or it is low-doped, raceway groove is enclosed by the bread of grid three.This special 3-D solid structure, increase
Strong control dynamics of the grid to raceway groove, greatly inhibit short-channel effect, it is suppressed that the leakage current of device.FinFET pipes have
It is low in energy consumption, the advantages of area is small, it is increasingly becoming and takes over conventional CMOS devices, continue one of improved device of Moore's Law.
It is traditional use the memory cell that FinFET designs as BSIMIMG technology libraries in classical memory cell.
The circuit diagram of classical memory cell is as shown in Figure 1 in BSIMIMG technology libraries.The memory cell managed by six FinFET (M1, M2,
M3, M4, M5 and M6) composition, wherein FinFET pipes M1 and FinFET pipe M3 one phase inverter of composition, FinFET pipes M2 and FinFET
Pipe M4 forms another phase inverter.The memory cell may destroy the data value of storage point storage in read operation, simultaneously as
Voltage may compress when read operation has the partial pressure of bit line capacitance and causes to read, if the compressed conference causes institute
Data are read just with data storage on the contrary, thus causing corrupt data during read operation, circuit function is unstable；Also, by
The pulldown network that FINFET pipe M3 and FINFET pipes M4 is formed has the road of two leakage currents when memory cell is in hold mode
Footpath, so leakage current is larger, it is larger so as to cause to leak power consumption, while it is also larger to be delayed, this is unfavorable for fast and stable access number
According to.
In view of this, for design one kind in the case where not influenceing circuit performance, delay, power consumption and power-consumption design are smaller, read
For operation hour according to that will not malfunction, the single-ended memory cell of reading of the higher full swing based on FinFET of circuit stability has weight
Want meaning.
The content of the invention
The technical problems to be solved by the invention are to provide one kind in the case where not influenceing circuit performance, delay, power consumption
Smaller with power-consumption design, data will not malfunction during read operation, the higher full pendulum based on FinFET of circuit stability
Single-ended reading memory cell.
Technical scheme is used by the present invention solves above-mentioned technical problem：A kind of full swing list based on FinFET
Read memory cell, including write word line, write bit line, anti-phase write bit line, readout word line, sense bit line, the first FinFET pipe, second in end
FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, the
Eight FinFET are managed and the 9th FinFET pipes, the first described FinFET pipes, the 2nd described FinFET pipes and the described the 7th
FinFET pipes are respectively the p-type FinFET pipes of Low threshold, and the 3rd described FinFET pipes, the 4th described FinFET are managed, are described
The 5th FinFET pipe, the 6th described FinFET pipe and the 9th described FinFET pipe be respectively for Low threshold N-type
FinFET is managed, and the 8th described FinFET pipes are managed for the N-type FinFET of high threshold, the source electrode of the first described FinFET pipes, institute
The source electrode for the 2nd FinFET pipes stated connects with the source electrode of the 7th described FinFET pipes and its connection end decouples for described reading
The power end of memory cell, the power end of described reading decoupling memory cell are used to accessing external power source, and described first
The front gate of FinFET pipes, the backgate of the first described FinFET pipes, the draining of the 2nd described FinFET pipes, the described the 3rd
The front gate of FinFET pipes, the draining of the 4th described FinFET pipes, the draining of the 5th described FinFET pipes, the described the 5th
The backgate of FinFET pipes, the front gate of the 7th described FinFET pipes, the backgate and the described the 8th of the 7th described FinFET pipes
The front gate connections of FinFET pipes and its connection end for described reading decoupling memory cell reversed-phase output, described first
The draining of FinFET pipes, the front gate of the 2nd described FinFET pipes, the backgate of the 2nd described FinFET pipes, the described the 3rd
The draining of FinFET pipes, the drain electrode and the described the 6th of the front gate, the 6th described FinFET pipes of the 4th described FinFET pipes
The back-gate connection of FinFET pipes and its connection end decouple the output end of memory cell, the 3rd described FinFET pipes for described reading
Source electrode, the described backgate of the 3rd FinFET pipes, the source electrode of the 4th described FinFET pipes, the 4th described FinFET pipes
Backgate connects with the source electrode of the 8th described FinFET pipes and its connection end is the earth terminal of described reading decoupling memory cell, institute
The earth terminal for the reading decoupling memory cell stated is used to accessing the earth, the source electrode of the 5th described FinFET pipes and described anti-phase writes
Bit line connects, and front gate, the front gate of the 6th described FinFET pipes of the 5th described FinFET pipes connect with described write word line,
The source electrode of the 6th described FinFET pipes connects with described write bit line, the backgate of the 8th described FinFET pipes, described
The front gate of nine FinFET pipes, the backgate of the 9th described FinFET pipes connect with described readout word line, the 7th described FinFET
The draining of pipe, the drain electrode of the 8th described FinFET pipes connects with the drain electrode of the 9th described FinFET pipes, and the described the 9th
The source electrode of FinFET pipes connects with described sense bit line.
The quantity of the fin of the first described FinFET pipes is 1, and the quantity of the fin of the 2nd described FinFET pipes is 1, described
The quantity of fin of the 3rd FinFET pipes be 1, the quantity of the fin of the 4th described FinFET pipes is 1, the 5th described FinFET
The quantity of the fin of pipe is 1, and the quantity of the fin of the 6th described FinFET pipes is 1, the quantity of the fin of the 7th described FinFET pipes
For 1, the quantity of the fin of the 8th described FinFET pipes is 1, and the quantity of the fin of the 9th described FinFET pipes is 1.
The threshold voltage of the first described FinFET pipes is 0.3v, and the threshold voltage of the 2nd described FinFET pipes is
0.3v, the threshold voltage of the 3rd described FinFET pipes is 0.3v, and the threshold voltages of the 4th described FinFET pipes is 0.3v, institute
The threshold voltage for the 5th FinFET pipes stated is 0.3v, and the threshold voltage of the 6th described FinFET pipes is 0.3v, described
The threshold voltage of seven FinFET pipes is 0.3v, and the threshold voltages of the 8th described FinFET pipes is 0.6v, the described the 9th
The threshold voltage of FinFET pipes is 0.3v.The circuit makes power consumption relatively low on the basis of ensureing to have the faster speed of service.
Compared with prior art, the advantage of the invention is that passing through the first FinFET pipes, the 2nd FinFET pipes, the 3rd
FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, the 8th FinFET pipes and the
Nine FinFET manage this nine FinFET pipes and form the single-ended reading memory cell of full swing based on FinFET, in write operation,
Write word line WWL is high level, the 5th FinFET pipes and the conducting of the 6th FinFET pipes, enters row write to output end Q by write bit line WBL
Enter operation, write operation is carried out to reversed-phase output Qb by anti-phase write bit line WBLb；In read operation, readout word line RWL is height
Level, the conducting of the 9th FinFET pipes, the 8th FinFET pipes according to the reversed-phase output Qb conditional conducting of storage value so that
Sense bit line RBL is discharged over the ground, and when wherein Qb is " 1 ", the 8th FinFET pipes conducting, RBL is discharged over the ground by the 8th FinFET pipes,
The 8th FinFET pipes end when Qb is " 0 ", and RBL voltages are constant, the 7th FinFET pipes, the 8th FinFET pipes and the 9th FinFET pipes
Isolate reversed-phase output and sense bit line, do not affect reversed-phase output Qb numerical value, reversed-phase output Qb data will not be by
Influence, while reversed-phase output Qb value passes through the phase inverter that the 7th FinFET pipes and the 8th FinFET pipes are formed to the 7th
The connection end Qbb of the drain electrode of FinFET pipes, the drain electrode of the 8th FinFET pipes and the drain electrode of the 9th FinFET pipes so that Qbb ends are
From 0 to power vd D full swings so that the sensitivity of reading improves, and can greatly improve the noise margin of read operation so that RSNM
It is of substantially equal with the SNM during holding, solve voltage by after partial pressure, it is possible to be compressed to out and now read out data inversion mistake
Problem, data will not malfunction during read operation, and circuit stability is higher, while is also substantially increased under the operating voltage of low-voltage
RSNM, during non-reading, when readout word line RWL is low level, the 8th FinFET pipe and the 9th FinFET pipes cut-off cause it is anti-phase
The data of output end reduce leakage current not by ectocine, simultaneously because read-write operation causes device most after separating
Small size requirement will not be too strict, and all transistors can go minimum breadth length ratio, so that sram cell is with feature
Size reduce when at low supply voltages can be more stable work；First FinFET is managed, the 2nd FinFET pipes and the 7th FinFET
The backgate of pipe connects front gate, reduces the backgate ground connection of leakage current, the 3rd FinFET pipes and the 4th FinFET pipes, reduces circuit power consumption,
5th FinFET is managed and the 6th FinFET pipes are connected to dynamic memory point, ensures that electric current is read in circuit work, the 8th FinFET pipes are
High threshold FinFET is managed, and the 7th FinFET pipes and the 9th FinFET pipes are managed for Low threshold FinFET, is ensureing that circuit function is correct
On the basis of, ensure during holding and leakage current will not change reading end data during write operation；Thus the present invention is not influenceing
In the case of circuit performance, delay, power consumption and power-consumption design are smaller, and data will not malfunction during read operation, circuit stability
It is higher.
Brief description of the drawings
Fig. 1 is the circuit diagram of classical memory cell in BSIMIMG technology libraries；
Fig. 2 is the single-ended circuit diagram for reading memory cell of the full swing based on FinFET of the present invention；
Fig. 3 is normal voltage (1v), and under the conditions of frequency 1G, the single-ended reading of the full swing of the invention based on FinFET is deposited
Simulation waveform of the storage unit under BSIMIMG standard technologies.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment one：As shown in Fig. 2 a kind of reading decoupling memory cell based on FinFET, including write word line WWL,
Write bit line WBL, anti-phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipes B1, the 2nd FinFET pipes B2,
Three FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6, the 7th FinFET pipes B7, the 8th
FinFET pipes B8 and the 9th FinFET pipe B9, the first FinFET pipes B1, the 2nd FinFET pipes B2 and the 7th FinFET pipes B7 difference
Managed for the p-type FinFET of Low threshold, the 3rd FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET
Pipe B6 and the 9th FinFET pipes B9 is respectively to be managed for the N-type FinFET of Low threshold, and the 8th FinFET pipes B8 is the N-type of high threshold
FinFET is managed, the source electrode connection of the first FinFET pipes B1 source electrode, the 2nd FinFET pipes B2 source electrode and the 7th FinFET pipes B7
And its connection end is reads the power end of decoupling memory cell, the power end for reading decoupling memory cell is used to access external power source VDD,
First FinFET pipes B1 front gate, the first FinFET pipes B1 backgate, the 2nd FinFET pipes B2 drain electrode, the 3rd FinFET pipes B3
Front gate, the 4th FinFET pipes B4 drain electrode, the 5th FinFET pipes B5 drain electrode, the 5th FinFET pipes B5 backgate, the 7th
FinFET pipes B7 front gate, the 7th FinFET pipes B7 backgate connect with the 8th FinFET pipes B8 front gate and its connection end is reading
Decouple the reversed-phase output of memory cell, the first FinFET pipes B1 drain electrode, the 2nd FinFET pipes B2 front gate, the 2nd FinFET
Pipe B2 backgate, the 3rd FinFET pipes B3 drain electrode, the 4th FinFET pipes B4 front gate, the 6th FinFET pipes B6 drain electrode and
Six FinFET pipes B6 back-gate connection and its connection end decouple the output end of memory cell, the 3rd FinFET pipes B3 source for reading
Pole, the 3rd FinFET pipes B3 backgate, the 4th FinFET pipes B4 source electrode, the 4th FinFET pipes B4 backgate and the 8th FinFET
Pipe B8 source electrode connection and its connection end decouple the earth terminal of memory cell for reading, and the earth terminal for reading decoupling memory cell is used to connect
Enter the earth, the 5th FinFET pipes B5 source electrode connects with anti-phase write bit line WBLb, the 5th FinFET pipes B5 front gate, the 6th
FinFET pipes B6 front gate connects with write word line WWL, and the 6th FinFET pipes B6 source electrode connects with write bit line WBL, and the 8th
FinFET pipes B8 backgate, the 9th FinFET pipes B9 front gate, the 9th FinFET pipes B9 backgate connect with readout word line RWL, the
Seven FinFET pipes B7 drain electrode, the 8th FinFET pipes B8 drain electrode connects with the 9th FinFET pipes B9 drain electrode, the 9th FinFET
Pipe B9 source electrode connects with sense bit line RBL.
Embodiment two：As shown in Fig. 2 a kind of reading decoupling memory cell based on FinFET, including write word line WWL,
Write bit line WBL, anti-phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipes B1, the 2nd FinFET pipes B2,
Three FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6, the 7th FinFET pipes B7, the 8th
FinFET pipes B8 and the 9th FinFET pipe B9, the first FinFET pipes B1, the 2nd FinFET pipes B2 and the 7th FinFET pipes B7 difference
Managed for the p-type FinFET of Low threshold, the 3rd FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET
Pipe B6 and the 9th FinFET pipes B9 is respectively to be managed for the N-type FinFET of Low threshold, and the 8th FinFET pipes B8 is the N-type of high threshold
FinFET is managed, the source electrode connection of the first FinFET pipes B1 source electrode, the 2nd FinFET pipes B2 source electrode and the 7th FinFET pipes B7
And its connection end is reads the power end of decoupling memory cell, the power end for reading decoupling memory cell is used to access external power source VDD,
First FinFET pipes B1 front gate, the first FinFET pipes B1 backgate, the 2nd FinFET pipes B2 drain electrode, the 3rd FinFET pipes B3
Front gate, the 4th FinFET pipes B4 drain electrode, the 5th FinFET pipes B5 drain electrode, the 5th FinFET pipes B5 backgate, the 7th
FinFET pipes B7 front gate, the 7th FinFET pipes B7 backgate connect with the 8th FinFET pipes B8 front gate and its connection end is reading
Decouple the reversed-phase output of memory cell, the first FinFET pipes B1 drain electrode, the 2nd FinFET pipes B2 front gate, the 2nd FinFET
Pipe B2 backgate, the 3rd FinFET pipes B3 drain electrode, the 4th FinFET pipes B4 front gate, the 6th FinFET pipes B6 drain electrode and
Six FinFET pipes B6 back-gate connection and its connection end decouple the output end of memory cell, the 3rd FinFET pipes B3 source for reading
Pole, the 3rd FinFET pipes B3 backgate, the 4th FinFET pipes B4 source electrode, the 4th FinFET pipes B4 backgate and the 8th FinFET
Pipe B8 source electrode connection and its connection end decouple the earth terminal of memory cell for reading, and the earth terminal for reading decoupling memory cell is used to connect
Enter the earth, the 5th FinFET pipes B5 source electrode connects with anti-phase write bit line WBLb, the 5th FinFET pipes B5 front gate, the 6th
FinFET pipes B6 front gate connects with write word line WWL, and the 6th FinFET pipes B6 source electrode connects with write bit line WBL, and the 8th
FinFET pipes B8 backgate, the 9th FinFET pipes B9 front gate, the 9th FinFET pipes B9 backgate connect with readout word line RWL, the
Seven FinFET pipes B7 drain electrode, the 8th FinFET pipes B8 drain electrode connects with the 9th FinFET pipes B9 drain electrode, the 9th FinFET
Pipe B9 source electrode connects with sense bit line RBL.
In the present embodiment, the quantity of the first FinFET pipes B1 fin is 1, and the quantity of the 2nd FinFET pipes B2 fin is 1, the
The quantity of three FinFET pipes B3 fin is 1, and the quantity of the 4th FinFET pipes B4 fin is 1, the number of the 5th FinFET pipes B5 fin
Measure as 1, the quantity of the 6th FinFET pipes B6 fin is 1, and the quantity of the 7th FinFET pipes B7 fin is 1, the 8th FinFET pipes B8
The quantity of fin be 1, the quantity of the 9th FinFET pipes B9 fin is 1.
Embodiment three：As shown in Fig. 2 a kind of reading decoupling memory cell based on FinFET, including write word line WWL,
Write bit line WBL, anti-phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipes B1, the 2nd FinFET pipes B2,
Three FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6, the 7th FinFET pipes B7, the 8th
FinFET pipes B8 and the 9th FinFET pipe B9, the first FinFET pipes B1, the 2nd FinFET pipes B2 and the 7th FinFET pipes B7 difference
Managed for the p-type FinFET of Low threshold, the 3rd FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET
Pipe B6 and the 9th FinFET pipes B9 is respectively to be managed for the N-type FinFET of Low threshold, and the 8th FinFET pipes B8 is the N-type of high threshold
FinFET is managed, the source electrode connection of the first FinFET pipes B1 source electrode, the 2nd FinFET pipes B2 source electrode and the 7th FinFET pipes B7
And its connection end is reads the power end of decoupling memory cell, the power end for reading decoupling memory cell is used to access external power source VDD,
First FinFET pipes B1 front gate, the first FinFET pipes B1 backgate, the 2nd FinFET pipes B2 drain electrode, the 3rd FinFET pipes B3
Front gate, the 4th FinFET pipes B4 drain electrode, the 5th FinFET pipes B5 drain electrode, the 5th FinFET pipes B5 backgate, the 7th
FinFET pipes B7 front gate, the 7th FinFET pipes B7 backgate connect with the 8th FinFET pipes B8 front gate and its connection end is reading
Decouple the reversed-phase output of memory cell, the first FinFET pipes B1 drain electrode, the 2nd FinFET pipes B2 front gate, the 2nd FinFET
Pipe B2 backgate, the 3rd FinFET pipes B3 drain electrode, the 4th FinFET pipes B4 front gate, the 6th FinFET pipes B6 drain electrode and
Six FinFET pipes B6 back-gate connection and its connection end decouple the output end of memory cell, the 3rd FinFET pipes B3 source for reading
Pole, the 3rd FinFET pipes B3 backgate, the 4th FinFET pipes B4 source electrode, the 4th FinFET pipes B4 backgate and the 8th FinFET
Pipe B8 source electrode connection and its connection end decouple the earth terminal of memory cell for reading, and the earth terminal for reading decoupling memory cell is used to connect
Enter the earth, the 5th FinFET pipes B5 source electrode connects with anti-phase write bit line WBLb, the 5th FinFET pipes B5 front gate, the 6th
FinFET pipes B6 front gate connects with write word line WWL, and the 6th FinFET pipes B6 source electrode connects with write bit line WBL, and the 8th
FinFET pipes B8 backgate, the 9th FinFET pipes B9 front gate, the 9th FinFET pipes B9 backgate connect with readout word line RWL, the
Seven FinFET pipes B7 drain electrode, the 8th FinFET pipes B8 drain electrode connects with the 9th FinFET pipes B9 drain electrode, the 9th FinFET
Pipe B9 source electrode connects with sense bit line RBL.
In the present embodiment, the first FinFET pipes B1 threshold voltage is 0.3v, and the 2nd FinFET pipes B2 threshold voltage is
0.3v, the 3rd FinFET pipes B3 threshold voltage are 0.3v, and the 4th FinFET pipes B4 threshold voltage is 0.3v, the 5th FinFET
Pipe B5 threshold voltage is 0.3v, and the 6th FinFET pipes B6 threshold voltage is 0.3v, the 7th FinFET pipes B7 threshold voltage
For 0.3v, the 8th FinFET pipes B8 threshold voltage is 0.6v, and the 9th FinFET pipes B9 threshold voltage is 0.3v.
Example IV：As shown in Fig. 2 a kind of reading decoupling memory cell based on FinFET, including write word line WWL,
Write bit line WBL, anti-phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipes B1, the 2nd FinFET pipes B2,
Three FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6, the 7th FinFET pipes B7, the 8th
FinFET pipes B8 and the 9th FinFET pipe B9, the first FinFET pipes B1, the 2nd FinFET pipes B2 and the 7th FinFET pipes B7 difference
Managed for the p-type FinFET of Low threshold, the 3rd FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET
Pipe B6 and the 9th FinFET pipes B9 is respectively to be managed for the N-type FinFET of Low threshold, and the 8th FinFET pipes B8 is the N-type of high threshold
FinFET is managed, the source electrode connection of the first FinFET pipes B1 source electrode, the 2nd FinFET pipes B2 source electrode and the 7th FinFET pipes B7
And its connection end is reads the power end of decoupling memory cell, the power end for reading decoupling memory cell is used to access external power source VDD,
First FinFET pipes B1 front gate, the first FinFET pipes B1 backgate, the 2nd FinFET pipes B2 drain electrode, the 3rd FinFET pipes B3
Front gate, the 4th FinFET pipes B4 drain electrode, the 5th FinFET pipes B5 drain electrode, the 5th FinFET pipes B5 backgate, the 7th
FinFET pipes B7 front gate, the 7th FinFET pipes B7 backgate connect with the 8th FinFET pipes B8 front gate and its connection end is reading
Decouple the reversed-phase output of memory cell, the first FinFET pipes B1 drain electrode, the 2nd FinFET pipes B2 front gate, the 2nd FinFET
Pipe B2 backgate, the 3rd FinFET pipes B3 drain electrode, the 4th FinFET pipes B4 front gate, the 6th FinFET pipes B6 drain electrode and
Six FinFET pipes B6 back-gate connection and its connection end decouple the output end of memory cell, the 3rd FinFET pipes B3 source for reading
Pole, the 3rd FinFET pipes B3 backgate, the 4th FinFET pipes B4 source electrode, the 4th FinFET pipes B4 backgate and the 8th FinFET
Pipe B8 source electrode connection and its connection end decouple the earth terminal of memory cell for reading, and the earth terminal for reading decoupling memory cell is used to connect
Enter the earth, the 5th FinFET pipes B5 source electrode connects with anti-phase write bit line WBLb, the 5th FinFET pipes B5 front gate, the 6th
FinFET pipes B6 front gate connects with write word line WWL, and the 6th FinFET pipes B6 source electrode connects with write bit line WBL, and the 8th
FinFET pipes B8 backgate, the 9th FinFET pipes B9 front gate, the 9th FinFET pipes B9 backgate connect with readout word line RWL, the
Seven FinFET pipes B7 drain electrode, the 8th FinFET pipes B8 drain electrode connects with the 9th FinFET pipes B9 drain electrode, the 9th FinFET
Pipe B9 source electrode connects with sense bit line RBL.
In the present embodiment, the quantity of the first FinFET pipes B1 fin is 1, and the quantity of the 2nd FinFET pipes B2 fin is 1, the
The quantity of three FinFET pipes B3 fin is 1, and the quantity of the 4th FinFET pipes B4 fin is 1, the number of the 5th FinFET pipes B5 fin
Measure as 1, the quantity of the 6th FinFET pipes B6 fin is 1, and the quantity of the 7th FinFET pipes B7 fin is 1, the 8th FinFET pipes B8
The quantity of fin be 1, the quantity of the 9th FinFET pipes B9 fin is 1.
In the present embodiment, the first FinFET pipes B1 threshold voltage is 0.3v, and the 2nd FinFET pipes B2 threshold voltage is
0.3v, the 3rd FinFET pipes B3 threshold voltage are 0.3v, and the 4th FinFET pipes B4 threshold voltage is 0.3v, the 5th FinFET
Pipe B5 threshold voltage is 0.3v, and the 6th FinFET pipes B6 threshold voltage is 0.3v, the 7th FinFET pipes B7 threshold voltage
For 0.3v, the 8th FinFET pipes B8 threshold voltage is 0.6v, and the 9th FinFET pipes B9 threshold voltage is 0.3v.
In order to verify the single-ended excellent benefit for reading memory cell of the full swing based on FinFET of the present invention,
Under BSIMIMG standard technologies, under conditions of the incoming frequency of circuit is 1GHz, circuit is used under the conditions of supply voltage 1V, 0.7V
Emulation tool HSPICE is to shown in the single-ended reading memory cell of the full swing based on FinFET and Fig. 1 of the present invention
The performance of classical both circuits of memory cell carries out simulation comparison in BSIMIMG technology libraries, wherein, BSIMIMG technology libraries pair
The standard mains voltage answered is 1V.Contrast reading and writing gimp tolerance limit simultaneously.Under normal voltage (1v), it is of the invention based on
The single-ended memory cell of reading of the full swing of FinFET is based on BSIMIMG standard technologies simulation waveform as shown in figure 3, analysis chart
3 understand, the single-ended memory cell of reading of the full swing of the invention based on FinFET has correct work-based logic.
Table 1 be under BSIMIMG standard technologies, supply voltage 1V, when incoming frequency is 1GHz, it is of the invention based on
Classical two kinds of electricity of memory cell in BSIMIMG technology libraries shown in the single-ended reading memory cell of full swing and Fig. 1 of FinFET
The performance comparision data on road.
Table 1
| Circuit types | Transistor size | It is delayed (ps) | Total power consumption (μ W) | Power-consumption design (fJ) |
| The present invention | 9 | 12.66 | 48.36 | 0.612 |
| Classical memory cell | 6 | 18.25 | 57.24 | 1.045 |
As can be drawn from Table 1：The full swing based on FinFET of the present invention is single-ended to read memory cell and and Fig. 1 institutes
Classical memory cell is compared in the BSIMIMG technology libraries shown, and delay reduces 30.63%, and average total power consumption reduces
15.51%, power-consumption design reduces 41.44%.
Table 2 be under BSIMIMG standard technologies, supply voltage 0.7V, when incoming frequency is 1GHz, it is of the invention based on
Classical two kinds of electricity of memory cell in BSIMIMG technology libraries shown in the single-ended reading memory cell of full swing and Fig. 1 of FinFET
The performance comparision data on road.
Table 2
| Circuit types | Transistor size | It is delayed (ps) | Total power consumption (μ W) | Power-consumption design (fJ) |
| The present invention | 9 | 23.11 | 32.85 | 0.759 |
| Classical memory cell | 6 | 30.56 | 39.13 | 1.196 |
As can be drawn from Table 2：The full swing based on FinFET of the present invention is single-ended to read memory cell and and Fig. 1 institutes
Classical memory cell is compared in the BSIMIMG technology libraries shown, and delay reduces 24.38%, and average total power consumption reduces
16.05%, power-consumption design reduces 36.54%.
Table 3 be under BSIMIMG standard technologies, supply voltage 0.7V, when incoming frequency is 1GHz, it is of the invention based on
Classical two kinds of electricity of memory cell in BSIMIMG technology libraries shown in the single-ended reading memory cell of full swing and Fig. 1 of FinFET
The read operation on road/write operation noise margin compares data
Table 3
As can be drawn from Table 3：The full swing based on FinFET of the present invention is single-ended to read memory cell and and Fig. 1 institutes
Classical memory cell is compared in the BSIMIMG technology libraries shown, and read noise tolerance limit adds 221.74%, is write noise margin and is added
108.96%.
From above-mentioned comparison data, the full swing of the invention based on FinFET is single-ended to read memory cell and figure
Classical memory cell compares in BSIMIMG technology libraries shown in 1, and the speed of service is improved, the power consumption and power consumption of circuit
Delay product is also optimized, and solves voltage by after partial pressure, it is possible to the problem of now reading out data inversion mistake is compressed to out,
Data will not malfunction during read operation, and circuit stability is higher.
Claims (3)
- A kind of 1. single-ended reading memory cell of full swing based on FinFET, it is characterised in that in including write word line, write bit line, Anti-phase write bit line, readout word line, sense bit line, the first FinFET pipes, the 2nd FinFET pipes, the 3rd FinFET are managed, the 4th FinFET is managed, 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, the 8th FinFET pipes and the 9th FinFET pipes, described first FinFET pipes, the 2nd described FinFET pipes and the 7th described FinFET pipes are respectively the p-type FinFET pipes of Low threshold, described The 3rd FinFET pipe, the 4th described FinFET pipe, the 5th described FinFET pipe, the 6th described FinFET pipe and it is described The 9th FinFET pipe be respectively for Low threshold N-type FinFET manage, the 8th described FinFET pipe for high threshold N-type FinFET is managed, the source electrode of the first described FinFET pipes, the source electrode of the 2nd described FinFET pipes and the 7th described FinFET The source electrode connection of pipe and its connection end decouple the power end of memory cell, the electricity of described reading decoupling memory cell for described reading Source is used to access external power source, the front gate of the first described FinFET pipes, the backgate of the first described FinFET pipes, described The draining of 2nd FinFET pipes, the draining of the front gate of the 3rd described FinFET pipes, the 4th described FinFET pipes, described The draining of five FinFET pipes, the backgate of the 5th described FinFET pipes, the front gate of the 7th described FinFET pipes, the described the 7th The backgate of FinFET pipes connects with the front gate of the 8th described FinFET pipes and its connection end decouples memory cell for described reading Reversed-phase output, the draining of the first described FinFET pipes, the front gate of the 2nd described FinFET pipes, described second The backgate of FinFET pipes, the draining of the 3rd described FinFET pipes, the front gate of the 4th described FinFET pipes, the described the 6th The drain electrode of FinFET pipes and the back-gate connection of the 6th described FinFET pipes and its connection end are described reading decoupling memory cell Output end, the described source electrode of the 3rd FinFET pipes, the backgate of the 3rd described FinFET pipes, the 4th described FinFET pipe Source electrode, the backgate of the 4th described FinFET pipes is connected with the source electrode of the 8th described FinFET pipes and its connection end is described Reading decoupling memory cell earth terminal, the earth terminal of described reading decoupling memory cell is used to accessing the earth, the described the 5th The source electrode of FinFET pipes connects with described anti-phase write bit line, the front gate of the 5th described FinFET pipes, the described the 6th The front gate of FinFET pipes connects with described write word line, and the source electrode of the 6th described FinFET pipes connects with described write bit line, The described backgate of the 8th FinFET pipes, the front gate of the 9th described FinFET pipes, the backgate of the 9th described FinFET pipes and Described readout word line connection, the draining of the 7th described FinFET pipes, the drain electrode of the 8th described FinFET pipes and described the The drain electrode connection of nine FinFET pipes, the source electrode of the 9th described FinFET pipes connect with described sense bit line.
- A kind of 2. single-ended reading memory cell of full swing based on FinFET according to claim 1, it is characterised in that The quantity of the fin of the first described FinFET pipes is 1, and the quantity of the fin of the 2nd described FinFET pipes is the 1, the described the 3rd The quantity of the fin of FinFET pipes is 1, and the quantity of the fin of the 4th described FinFET pipes is 1, the fin of the 5th described FinFET pipes Quantity be 1, the quantity of the fin of the 6th described FinFET pipes is 1, and the quantity of the fin of the 7th described FinFET pipes is 1, institute The quantity of the fin for the 8th FinFET pipes stated is 1, and the quantity of the fin of the 9th described FinFET pipes is 1.
- 3. the single-ended reading memory cell of a kind of full swing based on FinFET according to claim 1 or 2, its feature exist It is 0.3v in the threshold voltage of the first described FinFET pipes, the threshold voltage of the 2nd described FinFET pipes is 0.3v, described The threshold voltages of the 3rd FinFET pipes be 0.3v, the threshold voltages of the 4th described FinFET pipes is 0.3v, the described the 5th The threshold voltage of FinFET pipes is 0.3v, and the threshold voltage of the 6th described FinFET pipes is 0.3v, the 7th described FinFET The threshold voltage of pipe is 0.3v, and the threshold voltage of the 8th described FinFET pipes is 0.6v, the threshold of the 9th described FinFET pipes Threshold voltage is 0.3v.
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| WO2020039168A1 (en) * | 2018-08-21 | 2020-02-27 | Arm Limited | Switched source lines for memory applications |
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