CN112509621A - MOSFET-TFET mixed 11T SRAM unit circuit - Google Patents
MOSFET-TFET mixed 11T SRAM unit circuit Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The invention discloses a MOSFET-TFET mixed 11T SRAM unit circuit, which comprises five NTFET transistors, four PTFET transistors and two NMOSFET transistors, wherein: the power supply VDD is electrically connected to the source of PTFET transistor P3; the drain of PTFET transistor P3 is electrically connected to the source of PFET transistor P1; the drain of the PTFET transistor P2 is electrically connected to the drain of the NTFET transistor N2, the drain of the NMOSFET transistor N4, the gate of the PTFET transistor P1, the gate of the NTFET transistor N1, and the gate of the NTFET transistor N6, respectively; the source of the NTFET transistor N5 and the source of the NTFET transistor N6 are both electrically connected to GND. The circuit not only enhances the writing capability of the SRAM unit, but also reduces the static power consumption of the circuit and improves the stability of the SRAM unit in a holding state.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a MOSFET-TFET hybrid 11T SRAM unit circuit.
Background
With the development of mobile electronic products, the demand for low power consumption of integrated circuits is becoming more and more urgent. In recent years, MOSFETs (metal-oxide semiconductor field effect transistors) have become an important component of digital integrated circuits and analog integrated circuits. However, as integrated circuit technology nodes evolve, some of the drawbacks of MOSFETs in ultra-low power circuits make it difficult to obtain satisfactory results. Since the turn-off capability of the MOSFET at the sub-threshold voltage is weakened due to the short channel effect of the MOSFET as the size of the MOSFET is reduced, so that the static leakage current and the static power consumption of the circuit are increased, in the microprocessor, a Static Random Access Memory (SRAM) occupies more than 50% of the chip area and consumes most of the static power consumption of the processor, so that it becomes very critical to reduce the static power consumption of the SRAM.
Although many methods for reducing the static power consumption of an SRAM at sub-threshold voltages have been proposed extensively, conventional MOSFET technology has almost reached physical limits in ultra-low power applications, and the sub-threshold swing theoretical value at room temperature is not lower than 60 mV/dec. Further reduction of SRAM static power consumption at sub-threshold operating voltages remains quite limited. With respect to MOSFETs, the currently most promising low-power device is a Tunneling Field-Effect Transistor (TFET) based on Band-to-Band Tunneling (Band-to-Band Tunneling) mechanism. The subthreshold swing of the TFET can break through the limit of 60mV/dec, and the TFET can work under lower voltage to obtain larger current switching ratio, so that the static power consumption can be greatly reduced. However, due to the structural characteristics of TFETs, which have unidirectional conductivity and which differently dope the P and N regions of the MOS transistor, there are challenges in designing circuits using TFETs that have forward biased P-I-N currents that are not controlled by the gate due to the asymmetry of the source and drain doping, which increase the static power consumption of the circuit and also affect the stability of the storage node in the retention state.
Disclosure of Invention
The invention aims to provide a MOSFET-TFET hybrid 11T SRAM unit circuit, which improves the writing capability of an SRAM unit by adding a writing auxiliary tube, eliminates positive bias P-I-N current when a TFET is used as an SRAM access tube by using an NMOSFET transistor as the access tube, reduces the static power consumption of the circuit and improves the stability of the SRAM unit in a holding state.
The purpose of the invention is realized by the following technical scheme:
a MOSFET-TFET hybrid 11T SRAM cell circuit, the circuit comprising five NTFET transistors, denoted in order as N1, N2, N5, N6, N7; four PTFET transistors, designated sequentially as P1, P2, P3, P4; two NMOSFET transistors, denoted in sequence as N3, N4, wherein:
power supply VDD is electrically connected to the source of PTFET transistor P3, while power supply VDD is also electrically connected to the source of PTFET transistor P4;
the drain of PTFET transistor P3 is electrically connected to the source of PFET transistor P1;
the drain of PTFET transistor P4 is electrically connected to the source of PTFET transistor P2;
the drain of PTFET transistor P1 is electrically connected to the drain of NFET transistor N1, the drain of NMOSFET transistor N3, the gate of PTFET transistor P2, and the gate of NTFET transistor N2, respectively;
the drain of the PTFET transistor P2 is electrically connected to the drain of the NTFET transistor N2, the drain of the NMOSFET transistor N4, the gate of the PTFET transistor P1, the gate of the NTFET transistor N1, and the gate of the NTFET transistor N6, respectively;
the drain electrode of the NTFET transistor N5 is electrically connected with the source electrode of the NMOSFET transistor N3 and the source electrode of the NMOSFET transistor N4;
the drain of NTFET transistor N6 is electrically connected to the source of NTFET transistor N7;
the source of the NTFET transistor N5 and the source of the NTFET transistor N6 are both electrically connected with GND;
further, the PTFET transistor P1 and the NTFET transistor N1, and the PTFET transistor P2 and the NTFET transistor N2 constitute two inverters, which in turn constitute a latch circuit in the SRAM cell;
the PTFET transistors P3 and P4 are used for interrupting a latch circuit structure during write operation, so that the aim of improving the write capability of the SRAM cell during write operation is fulfilled;
the NTFET transistor N5, the NMOSFET transistors N3 and N4 form a transmission tube part of the SRAM unit, and the problem of positive bias P-I-N current when the TFET is used as the transmission tube of the SRAM unit is solved;
the NTFET transistors N6 and N7 form a read separation circuit for read operation to improve the read capability and speed of the SRAM cell.
According to the technical scheme provided by the invention, the writing capability of the SRAM unit is improved by adding the writing auxiliary tube in the circuit, the positive bias P-I-N current generated when TFET is used as the SRAM access tube is eliminated by using the NMOSFET transistor as the access tube, the static power consumption of the circuit is reduced, and the stability of the SRAM unit in a holding state is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a MOSFET-TFET hybrid 11T SRAM cell according to an embodiment of the present invention;
FIG. 2 is a data diagram illustrating comparison of write margins of a circuit with write margins of other cells according to an embodiment of the present invention;
fig. 3 is a data diagram illustrating comparison between static power consumption of a circuit and static power consumption of other units according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The basic devices used by the traditional SRAM memory unit circuit are MOSFETs, and the basic devices used by the MOSFET-TFET mixed type 11T SRAM unit circuit provided by the invention are Tunneling Field Effect Transistors (TFETs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Referring to the drawings, the embodiment of the present invention will be described in further detail, as shown in fig. 1, a circuit structure diagram of a MOSFET-TFET hybrid 11T SRAM cell provided by the embodiment of the present invention is shown, where the circuit includes five NTFET transistors, which are sequentially denoted as N1, N2, N5, N6, and N7; four PTFET transistors, designated sequentially as P1, P2, P3, P4; two NMOSFET transistors, denoted in sequence as N3, N4, wherein:
power supply VDD is electrically connected to the source of PTFET transistor P3, while power supply VDD is also electrically connected to the source of PTFET transistor P4;
the drain of PTFET transistor P3 is electrically connected to the source of PFET transistor P1;
the drain of PTFET transistor P4 is electrically connected to the source of PTFET transistor P2;
the drain of PTFET transistor P1 is electrically connected to the drain of NFET transistor N1, the drain of NMOSFET transistor N3, the gate of PTFET transistor P2 (denoted as G), and the gate of NTFET transistor N2, respectively;
the drain of the PTFET transistor P2 is electrically connected to the drain of the NTFET transistor N2, the drain of the NMOSFET transistor N4, the gate of the PTFET transistor P1, the gate of the NTFET transistor N1, and the gate of the NTFET transistor N6, respectively;
the drain electrode of the NTFET transistor N5 is electrically connected with the source electrode of the NMOSFET transistor N3 and the source electrode of the NMOSFET transistor N4;
the drain of NTFET transistor N6 is electrically connected to the source of NTFET transistor N7;
the source of the NTFET transistor N5 and the source of the NTFET transistor N6 are both electrically connected with GND;
the PTFET transistor P1 and the NTFET transistor N1, the PTFET transistor P2 and the NTFET transistor N2 form two inverters, and the two inverters form a latch circuit in the SRAM unit;
the PTFET transistors P3 and P4 are used for interrupting a latch circuit structure during write operation, so that the aim of improving the write capability of the SRAM cell during write operation is fulfilled;
the NTFET transistor N5, the NMOSFET transistors N3 and N4 form a transmission tube part of the SRAM unit, and the problem of positive bias P-I-N current when the TFET is used as the transmission tube of the SRAM unit is solved;
the NTFET transistors N6 and N7 form a read separation circuit for read operation, thereby improving the read capability and speed of the SRAM cell.
In addition, the NTFET transistors N5 and N7 reduce the leakage current and static power consumption of the SRAM unit in the holding state by using the advantage that the TFET tube has smaller off current.
In a specific implementation, the circuit further includes the following structure:
the write word line WL is electrically connected to the gate of NTFET transistor N5;
the write bit line BL is electrically connected to the gate of the PTFET transistor P3 and the gate of the NMOSFET transistor N3;
the write bit line BLB is electrically connected to the gate of PTFET transistor P4, the gate of NMOSFET transistor N4;
read word line RWL is electrically connected to the gate of NTFET transistor N7;
the read bit line RBL is electrically connected to the drain of an NTFET transistor N7.
Based on the above circuit configuration, the circuit, in the hold state: the write word line WL, write bit line BL, write bit line BLB, and read word line RWL are all low, and the NMOSFET transistors N3, N4 and the NTFET transistors N5, N6 are in an off state; the PTFET transistors P3 and P4 are turned on, so that a latch circuit formed by the PTFET transistor P1 and the NTFET transistor N1, and the PTFET transistor P2 and the NTFET transistor N2 is in a latch state, and the stability of the SRAM unit in a holding state is ensured.
Based on the circuit structure, the circuit, in a read operation phase:
the write word line WL, the write bit line BL and the write bit line BLB are at a low level, the read word line RWL is at a high level, and the read bit line RBL is precharged to a high level;
if the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", the read bit line RBL is discharged through the NTFET transistors N6, N7, completing the operation of reading "0";
if the voltage of the storage node Q is "1" and the voltage of the storage node QB is "0", the read bit line RBL is always kept at a high level to complete the operation of reading "1";
and a sense amplifier in the SRAM unit reads the data stored in the SRAM unit by detecting the change of the RBL level of the read bit line, so that the read operation is completed.
Based on the circuit structure, the circuit, in a write operation phase:
the read word line RWL is set to low level, and the read bit line RBL is precharged to high level;
assuming that the storage node Q is "1" and the storage node QB is "0", when the SRAM cell is to perform a write operation of "0", the write word line WL and the write bit line BL are set to high level, and the write bit line BLB is kept at the original state, i.e., low level; at this time, the NTFET transistor N5 and the NMOSFET transistor N3 are turned on, the PTFET transistor P3 is turned off, the P4 is turned on, the storage node Q is rapidly pulled to a low level because the pull-up path of VDD to the storage node Q is cut off by the turning off of the PTFET transistor P3, the VDD charges the storage node QB through the PTFET transistors P4, P2, so that the voltage of the storage node QB is rapidly raised to a high level, thereby completing the write "0" operation; after the write operation is finished, the write word line WL and the write bit line BL are set to be low level, the PTFET transistor P3 is turned on, the latch state is restored, and the stability of the SRAM unit is guaranteed;
assuming that the storage node Q is "0" and the storage node QB is "1", when the SRAM cell performs a write "1" operation, the write word line WL and the write bit line BLB are set to a high level, the write bit line BL is kept at a low level, the pass transistor NMOSFET transistor N4 and the NTFET transistor N5 are turned on, and the NTFET transistor P4 is turned off; the turning off of the PTFET transistor P4 cuts off the pull-up path of VDD to the storage node QB, which is rapidly pulled low through N4 and N5, and at the same time, since the write bit line BL is low, the PTFET transistor P3 is turned on, VDD charges the storage node Q through the PTFET transistors P3 and P1, so that the voltage of the storage node Q is rapidly raised high, thereby completing the write "1" operation; after the write operation is completed, the write word line WL and the write bit line BLB are set to low level, the PTFET transistor P4 is turned on, the latch state is restored, and the stability of the SRAM cell is ensured. The writing auxiliary technology is adopted in the process, so that the writing capacity and the writing margin of the SRAM unit are greatly improved.
In order to show the structure and effect of the circuit of the present invention more clearly, the SRAM cell circuit provided in the embodiment of the present invention is compared with other TFET SRAM cell circuits with reference to the following specific contents:
1) as shown in fig. 2, which is a data schematic diagram comparing write margins of the circuit provided by the embodiment of the present invention with write margins of other cells, write noise margins are obtained from a voltage transfer characteristic curve (denoted as VTC), because of the write assist technique, the circuit structure according to the embodiment of the present invention has a write margin larger than that of the 7T TFET SRAM cell and the 10T TFET SRAM cell accessed by the combinational transistor in the background art, and the 10T TFET SRAM cell accessed by the combinational transistor in the prior art needs to increase the size of the access transistor to complete the write operation.
2) Fig. 3 is a schematic diagram showing comparison data of static power consumption of the circuit according to the embodiment of the present invention and static power consumption of other units, which shows comparison of static power consumption of the MOSFET-TFET hybrid 11T SRAM cell circuit according to the embodiment of the present invention and the prior art 7T TFET SRAM and 10T TFET SRAM unit accessed by the combination transistor at a voltage of 0.5V to 1V, and it can be seen from experimental simulation results that: as the operating voltage rises, the static power consumption of the SRAM cell increases by orders of magnitude without eliminating the forward bias voltage, since 7T TFET SRAM in the prior art gradually increases due to the forward bias voltage of the access transistor in the retention state.
Compared with the traditional 7T TFET SRAM unit in the prior art, the static power consumption of the MOSFET-TFET hybrid 11T SRAM unit circuit provided by the invention is reduced by at least 3 orders of magnitude, because the NMOSFET with the bidirectional conduction characteristic is used as the access transistor, the problem of positive bias P-I-N current existing when the traditional 7T TFET SRAM unit uses the unidirectional conduction TFET transistor as the access transistor in the holding state is solved.
It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.
In summary, the circuit in the embodiment of the present invention utilizes the bidirectional conduction characteristic of the MOSFET transistor, and the TFET transistor has a smaller sub-threshold swing and a higher switching current ratio characteristic than the MOSFET transistor, so as to eliminate the problem of forward bias leakage current when the TFET is used as an SRAM pass transistor, and reduce the static power consumption of the conventional 7T TFET circuit; in addition, the defect of poor writing capability of the 10T TFET transistor accessed by the combined tube is overcome by using a writing auxiliary technology, and the writing capability and the stability of the SRAM unit are improved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A MOSFET-TFET hybrid 11T SRAM cell circuit comprises five NTFET transistors, which are sequentially marked as N1, N2, N5, N6 and N7; four PTFET transistors, designated sequentially as P1, P2, P3, P4; two NMOSFET transistors, denoted in sequence as N3, N4, wherein:
power supply VDD is electrically connected to the source of PTFET transistor P3, while power supply VDD is also electrically connected to the source of PTFET transistor P4;
the drain of PTFET transistor P3 is electrically connected to the source of PFET transistor P1;
the drain of PTFET transistor P4 is electrically connected to the source of PTFET transistor P2;
the drain of PTFET transistor P1 is electrically connected to the drain of NFET transistor N1, the drain of NMOSFET transistor N3, the gate of PTFET transistor P2, and the gate of NTFET transistor N2, respectively;
the drain of the PTFET transistor P2 is electrically connected to the drain of the NTFET transistor N2, the drain of the NMOSFET transistor N4, the gate of the PTFET transistor P1, the gate of the NTFET transistor N1, and the gate of the NTFET transistor N6, respectively;
the drain electrode of the NTFET transistor N5 is electrically connected with the source electrode of the NMOSFET transistor N3 and the source electrode of the NMOSFET transistor N4;
the drain of NTFET transistor N6 is electrically connected to the source of NTFET transistor N7;
the source of the NTFET transistor N5 and the source of the NTFET transistor N6 are both electrically connected with GND;
further, the PTFET transistor P1 and the NTFET transistor N1, and the PTFET transistor P2 and the NTFET transistor N2 constitute two inverters, which in turn constitute a latch circuit in the SRAM cell;
the PTFET transistors P3 and P4 are used for interrupting a latch circuit structure during write operation, so that the aim of improving the write capability of the SRAM cell during write operation is fulfilled;
the NTFET transistor N5, the NMOSFET transistors N3 and N4 form a transmission tube part of the SRAM unit, and the problem of positive bias P-I-N current when the TFET is used as the transmission tube of the SRAM unit is solved;
the NTFET transistors N6 and N7 form a read separation circuit for read operation to improve the read capability and speed of the SRAM cell.
2. The MOSFET-TFET hybrid 11T SRAM cell circuit of claim 1, further comprising the structure:
the write word line WL is electrically connected to the gate of NTFET transistor N5;
the write bit line BL is electrically connected to the gate of the PTFET transistor P3 and the gate of the NMOSFET transistor N3;
the write bit line BLB is electrically connected to the gate of PTFET transistor P4, the gate of NMOSFET transistor N4;
read word line RWL is electrically connected to the gate of NTFET transistor N7;
the read bit line RBL is electrically connected to the drain of an NTFET transistor N7.
3. The MOSFET-TFET hybrid 11T SRAM cell circuit of claim 2, wherein, based on the circuit configuration, in a holding state:
the write word line WL, write bit line BL, write bit line BLB, and read word line RWL are all low, and the NMOSFET transistors N3, N4 and the NTFET transistors N5, N6 are in an off state; the PTFET transistors P3 and P4 are turned on, so that a latch circuit formed by the PTFET transistor P1 and the NTFET transistor N1, and the PTFET transistor P2 and the NTFET transistor N2 is in a latch state, and the stability of the SRAM unit in a holding state is ensured.
4. The MOSFET-TFET hybrid 11T SRAM cell circuit of claim 2, wherein, based on the circuit configuration, the circuit, during a read operation:
the write word line WL, the write bit line BL and the write bit line BLB are at a low level, the read word line RWL is at a high level, and the read bit line RBL is precharged to a high level;
if the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", the read bit line RBL is discharged through the NTFET transistors N6, N7, completing the operation of reading "0";
if the voltage of the storage node Q is "1" and the voltage of the storage node QB is "0", the read bit line RBL is always kept at a high level to complete the operation of reading "1";
and a sense amplifier in the SRAM unit reads the data stored in the SRAM unit by detecting the change of the RBL level of the read bit line, so that the read operation is completed.
5. The MOSFET-TFET hybrid 11T SRAM cell circuit of claim 2, wherein, based on the circuit configuration, the circuit, during a write operation:
the read word line RWL is set to low level, and the read bit line RBL is precharged to high level;
assuming that the storage node Q is "1" and the storage node QB is "0", when the SRAM cell is to perform a write operation of "0", the write word line WL and the write bit line BL are set to high level, and the write bit line BLB is kept at the original state, i.e., low level; at this time, the NTFET transistor N5 and the NMOSFET transistor N3 are turned on, the PTFET transistor P3 is turned off, the P4 is turned on, the storage node Q is rapidly pulled to a low level because the pull-up path of VDD to the storage node Q is cut off by the turning off of the PTFET transistor P3, the VDD charges the storage node QB through the PTFET transistors P4, P2, so that the voltage of the storage node QB is rapidly raised to a high level, thereby completing the write "0" operation; after the write operation is finished, the write word line WL and the write bit line BL are set to be low level, the PTFET transistor P3 is turned on, the latch state is restored, and the stability of the SRAM unit is guaranteed;
assuming that the storage node Q is "0" and the storage node QB is "1", when the SRAM cell performs a write "1" operation, the write word line WL and the write bit line BLB are set to a high level, the write bit line BL is kept at a low level, the pass transistor NMOSFET transistor N4 and the NTFET transistor N5 are turned on, and the NTFET transistor P4 is turned off; the turning off of the PTFET transistor P4 cuts off the pull-up path of VDD to the storage node QB, which is rapidly pulled low through N4 and N5, and at the same time, since the write bit line BL is low, the PTFET transistor P3 is turned on, VDD charges the storage node Q through the PTFET transistors P3 and P1, so that the voltage of the storage node Q is rapidly raised high, thereby completing the write "1" operation; after the write operation is completed, the write word line WL and the write bit line BLB are set to low level, the PTFET transistor P4 is turned on, the latch state is restored, and the stability of the SRAM cell is ensured.
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| SAYEED AHMAD: "Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis", 《 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 》 * |
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