CN202363120U

CN202363120U - SRAM (static random access memory) unit under near-threshold power supply voltage realized by using virtual ground structure

Info

Publication number: CN202363120U
Application number: CN2011204894965U
Authority: CN
Inventors: 李玮; 陆俊嘉; 狄永清; 尚壮壮; 倪伟
Original assignee: WUXI XINXIANG ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: WUXI XINXIANG ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2011-11-30
Filing date: 2011-11-30
Publication date: 2012-08-01
Anticipated expiration: 2021-11-30

Abstract

The utility model discloses an SRAM (static random access memory) unit under a near-threshold power supply voltage realized by using a virtual ground structure, comprising a pair of cross-coupled phase inverters, wherein one phase inverter is connected between a power supply Vcc and a virtual ground VirVss, and the other phase inverter is connected between the power supply Vcc and a ground Vss; and a pair of complementary MOS (metal oxide semiconductor) transmission gates composed of a PMOS (P-channel metal oxide semiconductor) transistor and an NMOS (N-channel metal oxide semiconductor) transistor, wherein the grid of the PMOS transistor and the grid of the NMOS transistor are connected with a control line respectively, the sources/drains are connected with the phase inverter which is connected between the power supply Vcc and the virtual ground VirVss, and the drains/sources are connected with a bit line. The SRAM unit under a near-threshold power supply voltage realized by using a virtual ground structure disclosed by the utility model can realize the normal work of an SRAM under a near-threshold power supply voltage (ranging from 300 to 500 mv), and realize the SRAM with low power consumption.

Description

A kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize

Technical field

The utility model generally relates to static RAM (SRAM), relates more specifically to a kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize.

Background technology

Because the function of digital integrated circuit becomes increasingly complex, scale is increasing, and integrated storer has become a very important part in the digital circuitry on the sheet.In recent years, static RAM (SRAM) can be preserved data by feat of its power supply, and the characteristics that need not constantly to refresh become important component part indispensable in the on-chip memory, is widely used in the system level chip (SOC).According to the prediction of ITRS (ITRS), will account for 90% of SOC area to internal memory in 2013, this will cause the power consumption of chip more and more to depend on the power consumption of SRAM, and reduce power consumption the most obviously and effective and efficient manner be to reduce supply voltage as far as possible.But,, reduce the performance that supply voltage will certainly reduce sram cell along with further developing of CMOS technology.In addition, under the deep-submicron situation, process environments and the parameter of thereupon bringing change the performance that also can influence sram cell greatly.A kind of known SRAM main flow unit is six transistor units (6T), and it comprises six metal-oxide semiconductor (MOS)s (CMOS) transistor.As shown in fig. 1, say that simply 6T sram cell 100 comprises two identical and

cross-linked phase inverter

102 and 104, phase inverter 102 constitutes latch cicuits with phase inverter 104, links to each other with the input of another phase inverter like the output of a phase inverter.This latch cicuit is connected between power supply and the ground.Each phase inverter 102 or phase inverter 104 all comprise NMOS pull-

down transistor

115 or 125 and PMOS pull up transistor 110 or 120.The output of this phase inverter is as two memory node C and D, and when drop-down memory node a to low-voltage, then another node is pulled to high voltage.Paratope line is coupled to memory node on C and the D through a pair of

transmission gate transistor

130 and 135 respectively to 150 and 155.Usually word line 140 and this transmission gate transistor 130 link to each other with 135 grid.When word line voltage switched to system high voltage or Vcc,

transmission gate transistor

130 and 135 was unlocked to allow through

bit line

150 and 155 couples of memory node C and D being carried out access respectively.When word line voltage switched to system low-voltage or Vss,

transmission gate

130 and 135 was closed, and memory node C and D and bit line are isolated basically, and the state on the node can be kept.

Yet when system voltage or Vcc reduced near threshold region, on the one hand, transistorized switch current ratio can sharply descend, and caused being difficult to distinguish by the read current of addressed location with not by the leakage current of addressed location; On the other hand, under nearly threshold power voltage, the slight shift of PMOS and the interstructural threshold voltage of NMOS can cause 6T unit read stability and the decline of writing stability; Simultaneously, under nearly threshold power voltage, the slight variation of parameter can cause that all very great fluctuation process takes place transistorized drive current in the technological process.And these all will cause under nearly threshold power voltage, and the 6T sram cell can not realize reading and writing normally logic function, causes 6T sram cell cisco unity malfunction.

Summary of the invention

The purpose of the utility model is, in order to address the above problem, a kind of novel sram cell is provided, and makes sram cell under nearly threshold power voltage, can realize reading and writing normally logic function, realizes low-power consumption SRAM.

The utility model adopts following technical scheme for realizing above-mentioned purpose:

A kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize comprises: the phase inverter of pair of cross coupling, and wherein, a phase inverter is connected between power Vcc and the virtual ground VirVss, and another phase inverter is connected between power Vcc and the ground Vss; A pair of complementary MOS transmission gate; Said complementary MOS transmission gate is made up of PMOS transistor and nmos pass transistor; Wherein the transistorized grid of PMOS links to each other with control line; Source/drain links to each other with the above-mentioned output terminal that is connected the phase inverter between power Vcc and the virtual ground VirVss, and drain/source links to each other with bit line, and the grid of nmos pass transistor links to each other with control line; Source/drain links to each other with the above-mentioned output terminal that is connected the phase inverter between power Vcc and the virtual ground VirVss, and drain/source links to each other with bit line.

It is further characterized in that: said virtual ground structure is made up of a nmos pass transistor and a PMOS transistor; Wherein the grid of nmos pass transistor with read control line and link to each other; Drain electrode links to each other with virtual ground VirVss, and source electrode links to each other with ground Vss, and the transistorized grid of PMOS links to each other with ground Vss; Drain electrode links to each other with ground Vss, and source electrode links to each other with virtual ground VirVss.

In addition, the substrate of the nmos pass transistor in the said units all links to each other with ground Vss; The transistorized substrate of PMOS all links to each other with power Vcc.

The utility model can be realized SRAM operate as normal under nearly threshold power voltage (300mv-500mv), realizes low-power consumption SRAM.

Description of drawings

Fig. 1 is the circuit diagram of traditional 6T sram cell;

Fig. 2 is the circuit diagram of the sram cell of the utility model;

Fig. 3 is the SRAM array of figure of another combined with virtual ground structure of the utility model;

Fig. 4 carries out effective waveform of write operation under nearly threshold power voltage for the utility model;

Fig. 5 carries out read operation for the utility model under nearly threshold power voltage effective waveform.

Embodiment

A kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize as shown in Figure 2 comprises: the phase inverter and a pair of complementary MOS transmission gate of pair of cross coupling.

A phase inverter that is made up of PMOS transistor PM1 and nmos pass transistor NM1 in the phase inverter of described pair of cross coupling is connected between power Vcc and the virtual ground VirVss, and another individual phase inverter that is made up of PMOS transistor PM2 and nmos pass transistor NM2 is connected between power Vcc and the ground Vss;

Described a pair of complementary MOS transmission gate; Said complementary MOS transmission gate is made up of PMOS transistor PM0 and nmos pass transistor NM0; Wherein the grid of PMOS transistor PM0 links to each other with control line; Source electrode or drain electrode link to each other with the above-mentioned output terminal that is connected the phase inverter between power Vcc and the virtual ground VirVss, and drain electrode or source electrode link to each other with bit line BL, and the grid of nmos pass transistor NM0 links to each other with control line; Source electrode or drain electrode link to each other with the above-mentioned output terminal that is connected the phase inverter between power Vcc and the virtual ground VirVss, and drain electrode or source electrode link to each other with bit line BL.

Described PMOS transistor gate PM0 control line WLB and nmos pass transistor NM0 gate control lines WL have opposite logic.The control line of said PMOS transistor PM0 and nmos pass transistor NM0 links to each other with two word line WLB, WL respectively; Described word line has opposite logic; And in comprising the memory array of a plurality of said sram cells; Said control line and said word line WLB, WL are vertical, and said word line WLB, WL are parallel with power lead ground wire Vss.

Compare with the traditional 6T sram cell shown in Fig. 1; A reverser in the cross coupling inverter in the utility model is connected between power Vcc and the virtual ground VirVss; Another phase inverter is connected between power Vcc and the ground Vss, and the output that is connected the phase inverter between power Vcc and the virtual ground VirVss links to each other with transmission gate one end; The utility model carries out single-ended read-write; Read-write operation is realized through read-write control signal; The control signal of transmission gate is connected (like WLB signal wire and the WL signal wire among the figure) with corresponding word line, and the other end of transmission gate links to each other with bit line (like BL signal wire among the figure); The transistorized substrate of PMOS in the unit all links to each other with power source voltage Vcc, and the substrate of nmos pass transistor all links to each other with ground Vss.

Refer again to Fig. 2; As SRAM during at write cycles; Through the control write control signal effectively with the opening of complementary cmos transmission gate (switching WL and be high voltage or Vcc and WLB is low-voltage or Vss), the data on the bit line BL are passed through transmission gate write (on the C node) in the cross coupling inverter; When SRAM in read operation during the cycle; Through the opening of control read control signal and complementary cmos transmission gate (switching WL and be high voltage or Vcc and WLB is low-voltage or Vss), the data in the cross coupling inverter (data on the C node) is passed through transmission gate read on the bit line BL.

The concrete structure that on Fig. 2 basis, has provided virtual ground (VirVss) as shown in Figure 3; Said virtual ground VirVss structure is made up of a nmos pass transistor NM3 and a PMOS transistor PM3; Wherein the grid of nmos pass transistor NM3 with read control line rd_sel and link to each other, drain electrode links to each other with virtual ground VirVss, source electrode links to each other with ground Vss; The grid of PMOS transistor PM3, drain electrode and ground Vss link to each other, and source electrode links to each other with virtual ground VirVss.

The described control line of reading in comprising the memory array of a plurality of said sram cells, is read control line and power lead ground line parallel.

Described virtual ground structure, in comprising the memory array of a plurality of said sram cells, the public virtual ground structure of sram cell in each row.

Refer again to Fig. 3, provide the detailed write operation and the process of read operation below:

1) enables under the effective situation writing, if during write data " 1 " (the last data of BL are " 1 "), the rd_sel in the virtual ground structure is invalid; NMOS pipe NM3 is turn-offed, and VirVss is shorted to ground Vss through PMOS pipe PM3, and this moment, transmission gate was open-minded; Data are written to (C node) in the cross coupling inverter; Because the effect of phase inverter makes the voltage of D node become " 0 ", turn-off with the NMOS pipe that links to each other virtually like this, the voltage that C is ordered can maintain on " 1 "; If during write data " 0 " (the last data of BL are " 0 "), the rd_sel in the virtual ground structure is invalid, NMOS pipe (NM3) turn-offs; VirVss is shorted to ground (Vss) through PMOS pipe (PM3); And this moment, transmission gate was open-minded, and data are written to (C node) in the cross coupling inverter, and because the effect of phase inverter makes the voltage of D node become " 1 "; Open-minded with the NMOS pipe that links to each other virtually like this, the voltage that C is ordered can maintain on " 0 ".

2) reading to enable under the situation of effectively (rd_sel is effective); If the rd_sel during read data " 1 " in (data on the C node are " 1 ") virtual ground structure is effective; NM3 is open-minded for the NMOS pipe, and VirVss is shorted to ground Vss through PMOS pipe PM3 and NMOS pipe NM3, and this moment, transmission gate was open-minded; The voltage after the precharge can not descend on the BL because the C point voltage is for " 1 " makes, and has realized reading " 1 "; If during read data " 0 " (data are " 0 " on the C node); Rd_sel in the virtual ground structure is effective, makes NMOS pipe NM3 open-minded, and VirVss is shorted to ground Vss through PMOS pipe PM3 and NMOS pipe NM3; D point voltage " 1 " makes the nmos pass transistor that links to each other with virtual ground VirVss open-minded; And this moment, transmission gate was open-minded, and the voltage after the last precharge of BL has realized reading " 0 " through virtual ground VirVss structure rapid discharge to " 0 ".

Fig. 4 is the effective waveform of sram cell during write operation shown in Figure 3, supposes to write to enable to represent with signal wr_en, and the data on the bit line are represented with BL, the data after the storage of C node writes, and the storage of D node writes the inverse value of data.Can find out that by waveform under nearly threshold power voltage, the C node can be good at storing the data that write on the BL.

Fig. 5 is the effective waveform of sram cell during read operation shown in Figure 3; Data on the bit line are represented with BL, the data that the storage of C node will be read, the inverse value of the data that the storage of D node will be read; Under the effective situation of read signal (rd_sel); Can find out that by waveform under nearly threshold power voltage, BL can be correct reads the data on the C node.

Claims

1. nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize comprises:

The phase inverter of pair of cross coupling, a phase inverter in the phase inverter of described pair of cross coupling are connected between power supply (Vcc) and the virtual ground (VirVss), and another phase inverter is connected between power supply (Vcc) and the ground (Vss);

A pair of complementary MOS transmission gate; Said complementary MOS transmission gate is made up of PMOS transistor (PM0) and nmos pass transistor (NM0); Wherein the grid of PMOS transistor (PM0) links to each other with control line; Source electrode or drain electrode link to each other with the above-mentioned output terminal that is connected the phase inverter between power supply (Vcc) and the virtual ground (VirVss), and drain electrode or source electrode link to each other with bit line (BL), and the grid of nmos pass transistor (NM0) links to each other with control line; Source electrode or drain electrode link to each other with the above-mentioned output terminal that is connected the phase inverter between power supply (Vcc) and the virtual ground (VirVss), and drain electrode or source electrode link to each other with bit line (BL).

2. a kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize according to claim 1, it is characterized in that: described PMOS transistor gate control line and nmos pass transistor gate control lines have opposite logic.

3. a kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize according to claim 2; It is characterized in that: the control line of said PMOS transistor and nmos pass transistor (WL) links to each other with two word lines (WLB) respectively; Described word line has opposite logic, and in comprising the memory array of a plurality of said sram cells; Said control line is (WL) vertical with said word line (WLB), and said word line (WLB) is (WL) parallel with power lead ground wire (Vss).

4. a kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize according to claim 1; It is characterized in that: said virtual ground (VirVss) structure is made up of a nmos pass transistor (NM3) and a PMOS transistor (PM3); Wherein the grid of nmos pass transistor (NM3) with read control line (rd_sel) and link to each other; Drain electrode links to each other with virtual ground (VirVss); Source electrode links to each other with ground (Vss), and grid, drain electrode and the ground (Vss) of PMOS transistor (PM3) link to each other, and source electrode links to each other with virtual ground (VirVss).

5. a kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize according to claim 4; It is characterized in that: the described control line (rd_sel) of reading is in comprising the memory array of a plurality of said sram cells, and it is parallel with power lead ground wire (Vss) to read control line (rd_sel).

6. a kind of nearly threshold power voltage SRAM unit that adopts virtual ground structure to realize according to claim 4; It is characterized in that: described virtual ground structure; In comprising the memory array of a plurality of said sram cells, the public virtual ground structure of sram cell in each row.