TW202022869A - Five-transistor single port static random access memory with fast write speed - Google Patents

Abstract

The invention provides a 5T (five-transistor) port static random access memory with fast write speed, which comprises a memory array, a plurality of control circuits (2), a plurality of pre-charge circuits (3), a standby start-up circuit (4), a plurality of word line voltage level conversion circuits (5), a plurality of high voltage level control circuits (6), and a plurality of write driving circuits (7). The memory array is composed of a plurality of column memory cells and a plurality of rows of memory cells. Each column of memory cells is provided with a control circuit (2), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6). Each row of memory cells is provided with a pre-charge circuit (3) and a write driving circuit (7). In this way, in the write mode, the plurality of control circuits (2) and the plurality of write driving circuits (7) are used to effectively avoid difficulty in writing logic 1, and also increase the speed of writing logic 0. In the read mode, on the one hand, the plurality of control circuits (2) and the plurality of high-voltage level control circuits (6) are used to increase the write speed while avoiding unnecessary power loss and, on the other hand, the plurality of word line voltage level conversion circuits (5) are used to effectively reduce the interference of half-selected cells during reading. In the standby mode, the plurality of control circuits (2) are used to effectively reduce the leakage current, and the design of the standby start-up circuit (4) may effectively enable the static random access memory to quickly enter the standby mode.

Description

5T single-port static random access memory with high write speed

The present invention relates to a 5T single-port static random access memory (SRAM) with a high writing speed, especially a method that can effectively improve the standby performance of SRAM, and can effectively improve the reading speed and writing speed. Speed, and can effectively reduce the leakage current (leakage current), reduce the half-selected cell interference when reading, and avoid unnecessary power consumption SRAM.

The conventional 6T static random access memory (SRAM), as shown in Figure 1a, mainly includes a memory array (memory array) consisting of a plurality of memory blocks (MB ₁ , MB _2, etc.), each memory block is composed of a plurality of rows of memory cells (a plurality of rows of memory cells) and a plurality of rows of memory cells (a plurality of columns of memory cells). A row of memory cell and each row of memory cell each include a plurality of memory cells; a plurality of word lines (WL ₁ , WL _2, etc.), each word line corresponds to a plurality of rows of memory A column in the unit cell; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to one of the plural rows of memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit diagram of a 6T static random access memory (SRAM) unit cell. Among them, PMOS transistors (P1) and (P2) are called load transistors, and NMOS transistors (M1) ) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL and BLB They are the bit line and the complementary bit line. Since the single-port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the read initial instant voltage (V _AR ) of node A must satisfy equation (1): V _AR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 ( 1)

Among them, V _AR represents the read initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3) respectively, and V _DD and V _TM2 represent the power supply respectively The voltage and the threshold voltage of the NMOS transistor (M2), which results in the current drive capability ratio (ie cell ratio) between the drive transistor and the access transistor is usually set between 2.2 and 3.5 (please refer to 98 Patent Specification No. US76060B2 dated October 20, 2010, column 2, lines 8-10).

Figure 1b shows the HSPICE transient analysis simulation results of the 6T static random access memory cell during the write operation. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a schematic circuit diagram of a 5T static random access memory cell with only a single bit line. Compared with the 6T static random access memory cell in Figure 1b, this 5T static random access memory cell The bulk cell is one less transistor and one bit line less than the 6T static random access memory cell. However, the 5T static random access memory cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width-to-length ratio of M2 and M3 (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM unit cell), there is a problem that writing logic 1 is quite difficult. Consider the situation where the node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL) alone, the logic 0 written in node A is overwritten as a logic 1 write The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW =V _DD ×(R _M1 )/(R _M1 +R _M3 ) (2) Among them, V _AW represents the initial instantaneous voltage of node A, R _M1 R _M3 and R _M3 respectively represent the on-resistance of NMOS transistor (M1) and NMOS transistor (M3). Comparing equation (1) and equation (2), we can see that the initial write instant voltage (V _AW ) is less than that of NMOS transistor (M2) The threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The HSPICE transient analysis simulation results of the 5T static random access memory cell shown in Figure 3 during the write operation, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters, which are simulated by The simulation results can confirm that the 5T static random access memory cell with a single bit line has the problem that it is quite difficult to write logic 1.

So far, many methods have been proposed to solve the difficulty of writing logic 1 in the static random access memory cell of Figure 4 5T. The first method is to lower the voltage level supplied to the memory cell during writing. It is lower than the power supply voltage (V _DD ) to facilitate writing logic 1 (assuming node A originally stored logic 0 and now wants to write logic 1), by increasing the on-resistance of the driving transistor NMOS transistor M1 During the writing operation, the driving transistor NMOS transistor M2 can be turned on to complete the operation of writing logic 1. These methods are for example the "Memory System" proposed in Patent Document 1 (April 27, 1999, US 7706203B2) , Patent Document 2 (No. TW I426514B on February 11, 103) proposed "5T static random access memory with reduced power supply voltage during write operation" and Patent Document 3 (No. TW I534802B on May 21, 2015) No.) "Semiconductor memory", etc., which can effectively solve the problem of difficulty in writing logic 1, but because these methods need to set up dual power and/or discharge paths, and these methods must be The voltage level to the memory cell is pulled down to be lower than the power supply voltage (V _DD ) and the voltage level supplied to the memory cell is restored to the power supply voltage (V _DD ) after the writing is completed, so both Will cause unnecessary power loss.

The second method is to redesign the channel width-to-length ratio of PMOS transistors P1 and P2 and NMOS transistors M1, M2, and M3. For example, Non-Patent Document 4 (Satyan and Nalam et al., "5T SRAM with asymmetric sizing for improved read stability ”, IEEE Journal of Solid-State Circuits. ,Vol.46.No.10,pp 2431-2442,Oct.2011.), but because the PMOS transistors P1 and P2 have different channel width-to-length ratios and NMOS transistors M1 The channel width to length ratio is different from that of M2, so the static noise margin (SNM) will be reduced.

The third method is to raise the word line (WL) voltage level of the gate of the access transistor M3 supplied to the memory cell to be higher than the power supply voltage (V _DD ) during writing to facilitate writing logic 1 o'clock (assuming that node A originally stored logic 0, and now wants to write logic 1), by reducing the on-resistance of the access transistor M3 to turn on the driving transistor NMOS transistor M2 at the initial instant of writing. The operation of writing logic 1, such as the "Single-port static random access memory for increasing the voltage level of the word line during writing" proposed in Patent Document 5 (No. TW I404065B on August 1, 102), but Since the word line (WL) voltage level of the gate of the access transistor M3 supplied to the memory cell is pulled up higher than the power supply voltage (V _DD ) during writing, it will increase the writing time by half Half-selected cell disturbance (half-selected cell disturbance).

The fourth method is to pull the source voltage level of the driving transistor NMOS transistor M1 higher than the ground voltage during writing to facilitate writing to logic 1 (assuming that node A originally stores logic 0 and now wants to write Logic 1), by increasing the drain of the driving transistor NMOS transistor M1 Voltage level to enable the drive transistor NMOS transistor M2 to be turned on at the initial instant of writing to complete the operation of writing logic 1, for example, Patent Document 6 (No. TW I638364B on October 11, 107) proposed " 5T single-port static random access memory with high writing speed", "5T static random access memory with high writing speed" proposed in Patent Document 7 (No. TW I638365B on October 11, 107) And patent document 8 (No. TW I638355B on October 11, 107) proposed "5t static random access memory with high writing speed" and so on.

The fifth method is to use back gate bias technology to increase the threshold voltage of the driving transistor NMOS transistor M1 while reducing the threshold voltage of the access transistor M3 to facilitate writing logic At 1 o'clock (assuming that node A originally stored logic 0 and now wants to write logic 1), by increasing the drain voltage level of the driving transistor NMOS transistor M1, the driving transistor NMOS transistor can be enabled at the initial instant of writing. The crystal M2 is turned on to complete the operation of writing logic 1, but this method requires the use of split wells, which will increase the process complexity, so it is less used.

The sixth method is to redesign the connection relationship between PMOS transistors P1 and P2 and NMOS transistors M1, M2 and M3, such as Non-Patent Document 9 (Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process”, 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and Non-Patent Document 10 (Shyam Akashe et al., “High density and low leakage Current based 5T SRAM cell using 45nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.), etc.

Although the above-mentioned technologies can effectively solve the problem of difficulty in writing logic 1, none of these technologies consider how to increase the speed of writing logic 0. Among them, Patent Literature 6 to Patent Literature 8 consider the In the case of logic 1, design a write drive circuit that pulls the bit line voltage level higher than the power supply voltage to effectively prevent the difficulty of writing logic 1, while also effectively improving The speed of writing logic 1 is not considered how to increase the speed of writing logic 0. For example, when writing logic 0, the bit line voltage level is lowered to be lower than the ground voltage. In order to effectively increase the speed of writing logic 0, there is still room for improvement.

In view of this, the main purpose of the present invention is to provide a 5T single-port static random access memory with high writing speed, which can be designed to lower the bit line voltage level to lower than the ground voltage. Into the drive circuit to effectively increase the speed of writing logic 0.

The secondary objective of the present invention is to provide a 5T single-port static random access memory with high writing speed, which can effectively reduce read readings through word-line voltage level conversion circuits and high-voltage level control circuits. While taking half of the time to select the cell interference, it can also effectively improve the reading speed.

Another object of the present invention is to provide a 5T single-port static random access memory with high write speed, which can effectively increase the read speed by the control circuit, and can be controlled by two stages of read While improving the reading speed, it also avoids unnecessary power consumption.

The present invention provides a 5T single-port static random access memory with high writing speed, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby startup circuit ( 4) A plurality of word line voltage level conversion circuits (5), a plurality of high voltage level control circuits (6) and a plurality of write drive circuits (7), the memory array is composed of a plurality of rows of memory crystals It is composed of a cell and a plurality of rows of memory cell, each column of memory cell is provided with a control circuit (2), a word line voltage level conversion circuit (5) and a high voltage level control circuit (6), and Each row of memory cell is provided with a precharge circuit (3) and a write drive circuit (7), so that in the write mode, the plurality of control circuits can be used The circuit (2) and the plurality of write drive circuits (7) effectively prevent the difficulty of writing logic 1 while also increasing the speed of writing logic 0. In the read mode, on the one hand, through the plurality of control circuits (2) and the plurality of high voltage level control circuits (6) to improve the reading speed while avoiding unnecessary power loss. On the other hand, the plurality of word line voltage level conversion circuits (5) ) In order to effectively reduce the half-selected cell interference during reading, in the standby mode, the plurality of control circuits (2) can be used to effectively reduce the leakage current, and the standby start circuit (4) can be designed to In order to effectively promote the static random access memory to quickly enter the standby mode.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Pre-charge circuit

4‧‧‧Standby start circuit

5‧‧‧Character line voltage level conversion circuit

6‧‧‧High voltage level control circuit

7‧‧‧Write drive circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS Transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS Transistor

M13‧‧‧The third NMOS transistor

A‧‧‧Storage Node

B‧‧‧Inverted storage node

BL‧‧‧bit line

WLC‧‧‧Character line control signal

V _DD ‧‧‧Power supply voltage

VH‧‧‧High Voltage Node

VL1‧‧‧The first low voltage node

VL2‧‧‧The second low voltage node

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

M21‧‧‧Fourth NMOS Transistor

M22‧‧‧Fifth NMOS Transistor

M23‧‧‧The sixth NMOS transistor

M24‧‧‧The seventh NMOS transistor

M25‧‧‧Eighth NMOS Transistor

M26‧‧‧Ninth NMOS Transistor

M27‧‧‧Tenth NMOS Transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/RC‧‧‧Inverted reading control signal

/WC‧‧‧Inverted write control signal

INV‧‧‧Third inverter

D1‧‧‧First delay circuit

P31‧‧‧Fourth PMOS Transistor

P‧‧‧Precharge signal

M41‧‧‧Eleventh NMOS Transistor

P41‧‧‧Fifth PMOS Transistor

C‧‧‧node

D2‧‧‧Second delay circuit

WL‧‧‧character line

R‧‧‧Read signal

P51‧‧‧The sixth PMOS transistor

M51‧‧‧Twelfth NMOS Transistor

M52‧‧‧Thirteenth NMOS Transistor

P61‧‧‧The seventh PMOS transistor

P62‧‧‧Eighth PMOS Transistor

I63‧‧‧Fourth inverter

V _{DDH1 ‧‧‧The} highest power supply voltage

V _{DDH2 ‧‧‧The} second highest power supply voltage

P71‧‧‧Ninth PMOS Transistor

M71‧‧‧14th NMOS Transistor

M72‧‧‧Fifteenth NMOS Transistor

M73‧‧‧Sixteenth NMOS Transistor

I71‧‧‧Fifth inverter

I72‧‧‧Sixth inverter

Cap‧‧‧Capacitor

Din‧‧‧Enter data

D3‧‧‧The third delay circuit

D4‧‧‧The fourth delay circuit

Y‧‧‧Line decoder output signal

BLB ₁ ^… BLB _m ‧‧‧Complementary bit line

BLB‧‧‧Complementary bit line

MB ₁ ^… MB _k ‧‧‧Memory block

WL ₁ ^… WL _n ‧‧‧Character line

BL ₁ ^… BL _m ‧‧‧Bit line

I ₁ , I ₂ , I ₃ ‧‧‧Leakage current

M1 ^… M4‧‧‧NMOS transistor

P1 ^… P2‧‧‧PMOS transistor

Figure 1a shows the conventional static random access memory; Figure 1b shows the circuit diagram of the conventional 6T static random access memory cell; Figure 2 shows the conventional 6T static random access memory cell Figure 3 is a schematic diagram showing the circuit of the conventional 5T static random access memory cell; Figure 4 is a time chart showing the writing operation of the conventional 5T static random access memory cell; Fig. 5 is a schematic diagram showing the circuit proposed by the preferred embodiment of the present invention; Fig. 6 is a simplified circuit diagram showing the preferred embodiment of the present invention in Fig. 5 during the writing period; Fig. 7 is a schematic diagram showing the circuit of Fig. 5 The simplified circuit diagram of the preferred embodiment of the present invention during the read period; FIG. 8 shows the simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during the standby period.

According to the above-mentioned main purpose, the present invention proposes a 5T single-port static random access memory with high writing speed, which mainly includes a memory array composed of multiple rows of memory cell and multiple rows of memory Body cell, each row of memory cell and each The row memory cell includes a plurality of memory cell (1); a plurality of control circuits (2), each column of memory cell is provided with a control circuit (2); a plurality of precharge circuits (3), each row The memory cell is equipped with a pre-charging circuit (3); a standby startup circuit (4), the standby startup circuit (4) prompts the SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM; multiple word line voltage levels Standard conversion circuit (5), each row of memory cell is provided with a word line voltage level conversion circuit (5); multiple high voltage level control circuits (6), each row of memory cell is provided with a high voltage level Quasi-control circuit (6); and a plurality of write drive circuits (7), each row of memory cell is provided with a write drive circuit (7).

For ease of description, the static random access memory shown in Figure 5 only uses a memory cell (1), a word line (WL), a bit line (BL), and a control circuit (2). ), a precharge circuit (3), a standby startup circuit (4), a word line voltage level conversion circuit (5), a high voltage level control circuit (6), and a write drive circuit (7) It is described as an example. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) (Transistor P12 and a second NMOS transistor M12) and a third NMOS transistor (M13), wherein the first inverter and the second inverter are mutually coupled, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It is worth noting here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel width to length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) Also has the same channel Aspect ratio.

Please refer to Figure 5 again. The control circuit (2) consists of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an acceleration read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and An inverted standby mode control signal (/S) is composed. The source, gate, and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverted standby mode control signal (/S) and a second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistors (M23) is connected to the ground voltage, while the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor (M25) The source, gate and drain of) are respectively connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the The control signal (RC) is read, and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are connected to the ground voltage and the The drain of the tenth NMOS transistor (M27) And the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are connected to the ground voltage, the write control signal (WC) and the ninth The gate of the NMOS transistor (M26); and the source, gate and drain of the third PMOS transistor (P21) are respectively connected to the inverted standby mode control signal (/S) and the write control signal (WC) and the drain of the tenth NMOS transistor (M27). It is worth noting here that the inverted standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter.

Wherein, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the write control signal (WC) is at a logic low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/S), and when the write control When the signal (WC) is at the logic high level, the voltage level of the node (C) is the ground voltage, so as to stably complete the write operation (because the voltage level of the node C during the write operation is always the ground Voltage).

The control circuit (2) is designed to control the voltage levels of the first low-voltage node (VL1) and the second low-voltage node (VL2) in response to different operating modes. In the write mode, the unit cell is selected The source voltage (that is, the first low voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) closer to the bit line (BL) is set to be a predetermined voltage higher than the ground voltage (that is, The gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23) and the source voltage of another driving transistor in the unit cell (that is, the second NMOS transistor M12) (that is, the second The low voltage node VL2) is set to the ground voltage in order to prevent the problem of difficulty in writing logic 1.

In the first stage of the read mode, the source voltage (ie the first low voltage) of the drive transistor (ie the first NMOS transistor M11) closer to the bit line (BL) in the cell is selected The node VL1) is set to present the accelerated reading voltage (RGND) lower than the ground voltage, and the accelerated reading voltage (RGND) lower than the ground voltage can effectively increase the reading speed. In the second stage, the source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the selected unit cell is set back to the ground voltage to reduce unnecessary power consumption. The time between the second stage and the first stage of the mode selection is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level and reaches the gate of the eighth NMOS transistor (M25) The time until the voltage is sufficient to turn off the eighth NMOS transistor (M25), the value can be determined by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1) Adjustment.

In the standby mode, the source voltages of the driving transistors in all the memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; and in the holding mode, the driving power in the memory cells is set The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The write control signal (WC) in Table 1 is the AND gate operation result of a write signal (W) and the word line (WL) signal. At this time, only the write signal (W) When the signal and the word line (WL) signal are both at a high logic level, the write control signal (WC) is at a high logic level; the read control signal (RC) is a read signal (R) and the character Line (WL) signal and gate operation result. It is worth noting here that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (M24) Current.

Please refer to Figure 5. The precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so that during the precharge period, the precharge signal (P ) To precharge the bit line (BL) to the level of the power supply voltage (V _DD ).

Please refer to Figure 5 again, the standby startup circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby circuit Mode control signal (/S) composed. The source, gate and drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (VDD), the inverted standby mode control signal (/S) and the eleventh NMOS transistor ( M41) the drain; the source, gate and drain of the eleventh NMOS transistor (M41) are connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and The drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected To the gate of the eleventh NMOS transistor (M41).

Please refer to Figure 5 again, the word line voltage level conversion circuit (5) is composed of a Six PMOS transistors (P51), a twelfth NMOS transistor (M51), a thirteenth NMOS transistor (M52), the read control signal (RC), and an inverted write control signal (/WC) , It is composed of an inverted read control signal (/RC) and a word line control signal (WLC). The source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the word line (WL), the inverted write control signal (/WC) and the word line control signal (WLC) ); The source, gate and drain of the twelfth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL) ); And the source, gate and drain of the thirteenth NMOS transistor (M52) are respectively connected to the word line control signal (WLC), the inverted read control signal (/RC) and the word Yuan line (WL).

The detailed working voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

其中V_TM51表示該第十二NMOS電晶體(M51)之臨界電壓。在此值得注意的是，本發明一方面藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，另一方面藉由該字元線電壓位準轉換電路(5)，以於讀取操作期間將施加至選定晶胞之存取電晶體的字元線電壓下拉至低於 該電源供應電壓(即V_DD-V_TM51)，以有效降低讀取時之半選定晶胞干擾。

Where V _TM51 represents the threshold voltage of the twelfth NMOS transistor (M51). It is worth noting that, on the one hand, the present invention uses a two-stage read control to increase the read speed while avoiding unnecessary power loss. On the other hand, the word line voltage level conversion circuit ( 5) To pull down the word line voltage applied to the access transistor of the selected cell during the read operation to be lower than the power supply voltage (ie V _DD -V _TM51 ) to effectively reduce the half of the read time Selected cell interference.

Please refer to Figure 5 again. The high voltage level control circuit (6) consists of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), and the read It is composed of a control signal (RC) and a first high power supply voltage (V _DDH1 ), wherein the source, gate and drain of the seventh PMOS transistor (P61) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and a high voltage node (VH), the source, gate and drain of the eighth PMOS transistor (P62) are respectively connected to the first high power supply voltage ( V _DDH1 ), the output of the fourth inverter (I63) and the high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC) and outputting It is connected to the gate of the eighth PMOS transistor (P62). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to Figure 5 again. The write drive circuit (7) consists of a ninth PMOS transistor (P71), a fourteenth NMOS transistor (M71), a fifteenth NMOS transistor (M72), and a Sixteenth NMOS transistor (M73), a fifth inverter (I71), a sixth inverter (I72), a capacitor (Cap), an input data (Din), a row of decoder output signal (Y ), a third delay circuit (D3), a fourth delay circuit (D4), and a second high power supply voltage (V _DDH2 ), wherein the source and gate of the ninth PMOS transistor (P71) And the drain are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (I71) and the drain of the fourteenth NMOS transistor (M71), the fourteenth NMOS The source, gate and drain of the transistor (M71) are respectively connected to the drain of the sixteenth NMOS transistor (M73), the output of the fifth inverter (I71) and the ninth PMOS transistor (P71), the source, gate and drain of the fifteenth NMOS transistor (M72) are connected to the ground voltage, the output of the third delay circuit (D3) and the ninth PMOS transistor, respectively The drain of the crystal (P71), the source, gate and drain of the sixteenth NMOS transistor (M73) are connected to the ground voltage, the output of the sixth inverter (I72) and the tenth The source of four NMOS transistors (M71), the input of the fifth inverter (I71) is for receiving the input data (Din), and the output is connected to the gate of the ninth PMOS transistor (P71), The gate of the fourteenth NMOS transistor (M71) and the input of the third delay circuit (D3), the input of the sixth inverter (I72) is for receiving the row decoder output signal (Y), and The output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M73), one end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), The other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M71) and the drain of the sixteenth NMOS transistor (M73), wherein the ninth PMOS transistor (P71) ), the drain of the fourteenth NMOS transistor (M71) and the drain of the fifteenth NMOS transistor (M72) are connected to the bit line (BL), the bit line (BL ) The first stage of writing logic 0 is designed to be lower than the ground voltage to accelerate the speed of writing logic 0, and when writing logic 1, it is designed to be higher than the power supply voltage ( The level of the second highest power supply voltage (V _DDH2 ) of V _DD ) is used to accelerate the writing speed of logic 1.

Whether the write drive circuit (7) is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is at a logic low level, the write drive circuit ( 7) is in the disabled state, and when the row decoder output signal (Y) is at a logic high level, the write drive circuit (7) is in the enabled state. When the row decoder output signal (Y) is at a logic low level, the output of the sixth inverter (I72) is at a logic high level. On the one hand, the sixteenth NMOS transistor (M73) is turned on, and on the other hand, it passes through the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged. Because the 16th NMOS transistor (M73) is turned on, the other end of the capacitor (Cap) is the ground voltage , And one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V _DD ) due to the charging of the capacitor (Cap).

The write drive circuit (7) adopts a two-stage operation when writing to the enable state of logic 0. In the first stage of the write drive circuit (7) is enabled, the row decoder output signal at a logic high level (Y) to make the output of the sixth inverter (I72) a logic low level. On the one hand, the sixteenth NMOS transistor (M73) is turned off (OFF), and on the other hand, it passes through the fourth delay circuit After the delay time provided by (D4), one end of the capacitor (Cap) is quickly discharged to the ground voltage. Because the input data (Din) is at a logic low level at this time, the output of the fifth inverter (I71) Is a logic high level, so the fourteenth NMOS transistor (M71) is turned on, and the ninth PMOS transistor (P71) is turned off (OFF), so the voltage level of the bit line (BL) is at the The writing drive circuit (7) satisfies equation (3) when writing the first stage of logic 0: V _BL1 = -V _DD ×Cap/(Cap+C _BL ) (3)

Wherein, V _BL1 represents the voltage level of the bit line (BL) in the first stage of writing logic 0, and the absolute value of V _BL1 is designed to be smaller than the threshold voltage of the third NMOS transistor (M13), for example, it can be designed It is -100mV, -150mV or -200mV, V _{DD is} the voltage level of the power supply voltage (V _DD ), and Cap and C _BL represent the capacitance value of the capacitor (Cap) and the bit line (BL) respectively The parasitic capacitance value.

When the input data (Din) at the logic low level has passed the delay time provided by the fifth inverter (I71) and the third delay circuit (D3), the write drive circuit (7) enters the enabled first In the second stage, since the fifteenth NMOS transistor (M72) is turned on, the voltage level of the bit line (BL) is in the second stage when the write drive circuit (7) writes logic 0 Satisfy equation (4): V _BL2 =0 (4)

Wherein, V _BL2 represents the voltage level of the bit line (BL) in the second stage of writing logic 0.

The working principle of the preferred embodiment of the present invention shown in Figure 5 is described based on the working mode of the SRAM as follows:

(I) write mode

Before the write operation starts, the write control signal (WC) is at a logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth NMOS transistor (M27) is turned off (OFF) , Because the inverted standby mode control signal (/S) is at a logic high level at this time, the drain of the third PMOS transistor (P21) is at a logic high level, and the third PMOS transistor ( The drain of P21) turns on the ninth NMOS transistor (M26) and makes the first low voltage node (VL1) present a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, so that the tenth NMOS transistor (M27) is turned on and the node C is at the ground voltage (because the standby mode control signal (S) is the logic low level of the ground voltage), so the ninth NMOS transistor (M26) is turned off, and the first low voltage node (VL1) is equal to the gate source of the sixth NMOS transistor (M23) The voltage V _{GS (M26)} can effectively prevent the problem of difficulty in writing logic 1. FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during the writing period.

Next, according to the four write states of the single-port SRAM, how to complete the write operation in the preferred embodiment of the present invention shown in FIG. 6 is described.

(1) Node A originally stored logic 0, but now wants to write logic 0: Before the write operation occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on (ON) ). Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, access transistor), the third NMOS transistor (M13) changes from OFF to On (ON), at this time, because the first NMOS transistor (M11) is on, the voltage level of the node A is at the first stage of writing logic 0, although it will be less than the ground voltage due to equation (3) However, in the second phase of writing logic 0, the node A will return to the original ground voltage due to equation (4) until the end of the writing cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1: Before the write action occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on (ON) ). Because the first NMOS transistor (M11) is ON, when the write operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the node A The voltage of will rise with the voltage of the word line control signal (WLC).

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from off (OFF) to on (ON). Because the bit line (BL) is the voltage level of the second high power supply voltage (V _DDH2 ), and because the first NMOS transistor (M11) is still ON and the node B is at the voltage level, it is close to The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V _AWI1 ) written to node A satisfies the equation ( 5): V _AWI1 =V _DDH2 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (5)

V _AWI1 represents the initial instantaneous voltage at which node A is written from logic 0 to logic 1, and R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the The on-resistance of the sixth NMOS transistor (M23), and V _DDH2 and V _TM12 represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively, due to the second high The voltage level of the power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ), and a sixth NMOS transistor is provided at the first low voltage node (VL1) (M23) gate-source voltage V _{GS (M23)} voltage level, so the voltage level of node A can be easily set to be higher than that of the conventional 5T static random access memory cell in Figure 4 The voltage level of node A is much higher. The divided voltage level is much higher enough to turn on the second NMOS transistor (M12), so that node B is discharged to a lower voltage level, and the lower voltage level of node B will make the second NMOS transistor The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A, the The higher voltage level of node A passes through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level. The lower voltage level of B passes through the first inverter (consisting of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, and so on. , The node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It is worth noting here that the first low voltage node (VL1) originally stores logic 0 at node A, and the period of writing logic 1 is equal to the gate-source voltage V of the sixth NMOS transistor (M23) The voltage level of _{GS (M23)} , after writing logic 1, will have the ground voltage level due to the discharge through the ninth NMOS transistor (M26).

(3) Node A originally stored logic 1, but now it wants to write logic 1: Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on (ON) . When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), because the node A is the voltage level of the power supply voltage (V _DD ), and the bit line (BL) is the voltage level of the second high power supply voltage (V _DDH2 ), so the third NMOS transistor (M13) will continue to remain in the OFF state; at this time, because the first PMOS transistor ( P11) is still ON, although the voltage level of the node A will be slightly larger than the power supply voltage (V _DD ) due to the voltage level of the second highest power supply voltage (V _DDH2 ), but After the writing is completed, the node A will return to the original voltage level of the power supply voltage (V _DD ).

(4) Node A originally stored logic 1, but now wants to write logic 0: Before the write action occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is ON ). When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) When the threshold voltage is reached, the third NMOS transistor (M13) turns off (OFF) to on (ON), because the voltage level of the bit line (BL) is the voltage level that satisfies the equation (3) ( V _BL1 ), which is less than 0V, and because the first PMOS transistor (P11) is still ON and the node B is in the initial state where the voltage level is close to the voltage level of the ground voltage, the first NMOS transistor The crystal (M11) is still off, and the initial instantaneous voltage (V _AWI0 ) written to node A satisfies equation (6): V _AWI0 =V _BL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) (6)

V _AWI0 represents the initial instant voltage at which node A is written to logic 0 from logic 1, R _M13 and R _P11 represent the on-resistance of the third NMOS transistor (M13) and the first PMOS transistor (P11), and V _BL1 and V _DD respectively represent the voltage level of the bit line (BL) in the first stage of writing logic 0 and the voltage level of the power supply voltage (V _DD ), because when logic 1 is written to logic 0 , The third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is proportional to the square of its gate-source voltage V _{GS (M13)} minus its threshold voltage. Therefore, by The design of the bit line (BL) with a voltage level (V _BL1 ) of less than 0V in the first stage of writing logic 0 can effectively accelerate the speed of writing logic 0 from logic 1.

(II) Read mode

Before the start of the read operation, the write control signal (WC) is at a logic low level, and the inverted standby mode control signal (/S) is at a logic high level, so that the node C is at a logic high level, which is higher than the logic level. The node C will turn on the ninth NMOS transistor (M26), and make the first low voltage node (VL1) a ground voltage. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It is worth noting here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, thereby precharging the corresponding bit line (BL) to the power supply Voltage (V _DD ) level, but because the operating voltage of the process technology below 10 nanometers will drop below 0.9 volts, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes a two-stage reading The control is used to improve the reading speed and meet the specifications while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in Figure 5 uses a two-stage read control to increase the read speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately The accelerated reading voltage (RGND) whose ground voltage is low, and the accelerated reading voltage (RGND) whose ground voltage is lower than the ground voltage can effectively increase the reading speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but at this time, the eighth NMOS transistor (M25) is turned off, so the first low voltage node (VL1) will be at the ground voltage through the ninth NMOS transistor (M26) turned on, thereby effectively reducing unnecessary power consumption. It is worth noting here that the time between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the first stage. The time until the gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by the fall delay time of the third inverter (INV) and the first delay circuit (D1) Adjust the delay time provided. Furthermore, whether in the first stage or the second stage of the read operation, the ninth NMOS transistor (M26) is in a conducting state (because the gate of the ninth NMOS transistor (M26) is at a high logic level ). FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during the read period.

Next, the invention in Figure 7 will be explained based on the two read states of the SRAM port. The preferred embodiment uses the control circuit (2) and the high voltage level control circuit (6) to improve the reading speed while avoiding unnecessary power loss. On the other hand, the word line voltage level conversion is used Circuit (5) effectively reduces the half-selected cell interference during reading.

(1) Read logic 1 (node A stores logic 1): Before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON ), the node A and the node B are the power supply voltage (V _DD ) and the ground voltage, respectively, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3) . During the reading period, because the word line control signal (WLC) _deducts the threshold voltage of the twelfth NMOS transistor (M51) (ie V _DD -V _TM51 ) for the power supply voltage, and because the node A is The voltage level of the power supply voltage (V _DD ), so the third NMOS transistor (M13) is in an OFF state, thereby effectively keeping the bit line (BL) at the power supply voltage until read The cycle ends and the operation of reading logic 1 is successfully completed. It is worth noting here that during the read operation, the word line control signal (WLC) is used for the power supply voltage to _deduct the threshold voltage of the twelfth NMOS transistor (M51) (ie V _DD -V _TM51 ) , So it can effectively reduce the half-selected cell interference during reading. In addition, in the first stage of the read operation, the read initial instantaneous voltage (V _RVL1I ) of the first low voltage node (VL1) when reading logic 1 must satisfy equation (7): V _RVL1I = RGND×R _M26 /(R _M26 +R _M24 +R _M25 )>-V _TM11 (7) to effectively prevent half-selected cell interference during reading, where V _RVL1I represents the first low voltage node (VL1) during reading Read the initial instantaneous voltage at logic 1, RGND represents the accelerated reading voltage, R _M26 represents the on-resistance of the ninth NMOS transistor (M26), and R _M24 represents the on-resistance of the seventh NMOS transistor (M24). R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM11 represents the threshold voltage of the first NMOS transistor (M11); in the second stage of the read operation, the first low voltage node The voltage (V _RVL1 ) of (VL1) can be expressed by equation (8): V _RVL1 = ground voltage (8), thereby effectively reducing unnecessary power consumption.

Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the absolute value of the accelerated reading voltage (RGND) can be set to be less than that of the first NMOS transistor (M11) more conservatively The threshold voltage (V _TM11 ), namely |RGND|<V _TM11 (9), where |RGND| and V _TM11 respectively represent the absolute value of the acceleration read voltage and the threshold voltage of the first NMOS transistor (M11).

(2) Read logic 0 (node A stores logic 0): Before the read operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF) ), the node (A) and the node (B) are ground voltage and the first high power supply voltage (V _DDH1 ) respectively, and the bit line (BL) is equal to the precharge circuit (3) Power supply voltage (V _DD ). Because the first NMOS transistor (M11) is ON, when the read operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage offsets the twelfth NMOS The threshold voltage of transistor M51 is V _DD -V _TM51 ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from off (OFF) to on (ON). The read initial instantaneous voltage (V _AR0I ) of the node A must satisfy equation (10): V _AR0I =V _DD ×(R _M11 +(R _M24 +R _M25 )∥R _M26 )/(R _M13 +R _M11 +( R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 )∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 + R _M13 )<V _TM12 (10) to avoid turning on the second NMOS transistor (M12), where V _AR0I represents the initial instantaneous voltage when node A reads logic 0, R _M11 , R _M13, R _M24, R _M25 and R _M26 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25) and the ninth NMOS transistor. The on-resistance of the transistor (M26), and V _DD , RGND and V _TM12 respectively represent the _threshold voltage of the power supply voltage (V _DD ), the accelerated reading voltage (RGND) and the second NMOS transistor (M12). It is worth noting here that the accelerated reading voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated reading voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (M11). Furthermore, the word line control signal (WLC) in the reading period of the present invention is set to the power supply voltage to _subtract the threshold voltage (V _DD -V _TM51 ) of the thirteenth NMOS transistor (M51), which On the one hand, it can effectively reduce the half-selected cell interference during reading. On the other hand, the on-resistance (R _M13 ) of the third NMOS transistor (M13) can be increased to more easily satisfy the equation (10).

Furthermore, during the read logic 0 period, since node B is the first high power supply voltage (V _DDH1 ), and the first low voltage node (VL1) is a voltage lower than the ground voltage, due to the first high The power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ). Therefore, the conduction degree of the first NMOS transistor (M11) can be increased to effectively increase the reading speed. It is worth noting here that the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor ( P12) The sum of the absolute value of the threshold voltage |V _TP12 |, that is, V _DD <V _DDH1 <V _DD + |V _TP12 ｜ (11) Where |V _TP12 ｜ represents the threshold voltage of the second PMOS transistor (P12) The absolute value.

It is worth noting here that the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the ninth PMOS transistor ( P71) The sum of the absolute value of the critical voltage｜V _TP71 ｜, that is, V _DD <V _DDH2 <V _DD +｜V _TP71 ｜ (12)

Among them, |V _TP71 | represents the absolute value of the threshold voltage of the ninth PMOS transistor (P71).

Of course, in order to simplify the circuit scale, the first high power supply voltage (V _DDH1 ) can be set to the same potential as the second high power supply voltage (V _DDH2 ).

(III) Standby mode

First, explain how the standby startup circuit (4) in Figure 5 prompts the SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/S) It is logic High, and the inverted standby mode control signal (/S) of the logic High turns off the fourth PMOS transistor (P41) and turns on the twelfth NMOS transistor (M41); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low makes the fourth PMOS transistor (P41) conductive (ON) ), but in the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low to count, to the gate of the twelfth NMOS transistor (M41) The time until the voltage is sufficient to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor (M41) remains Turning on (ON), so the first low voltage node (VL1) can be quickly charged to the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), that is, the single port SRAM can quickly enter standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) turns off and stops supplying current.

Please refer to Figure 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the inverted standby The mode control signal (/S) can make the fourth NMOS transistor (M21) in the control circuit (2) turn off (OFF), and the standby mode control signal (S) of the logic high level can make the fifth The NMOS transistor (M22) is turned on (ON). At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. Make the voltage level of the first low voltage node (VL1) equal to the voltage level of the second low voltage node (VL2), and the voltage levels will all be equal to the threshold of the sixth NMOS transistor (M23) The voltage level of the voltage (V _TM23 ). Figure 8 is a simplified circuit diagram of the preferred embodiment of the present invention in Figure 5 during standby.

Next, the present invention is how to reduce the leakage current in the standby mode (standby mode), please refer to FIG. 8, FIG. 8 described respective leak current (subthreshold leakage current) I ₁ generated by the embodiment of the present invention when in the standby mode , I ₂ , I ₃ , where it is assumed that the output of the first inverter in the SRAM cell (ie node A) is logic Low (it should be noted here that since the second low voltage node (VL2 The voltage level of) is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the logic Low node A is also maintained at the voltage level of V _TM23 ) , And the output of the second inverter (ie node B) is logic High (power supply voltage V _DD ). Please refer to the prior art in Figure 1b and the embodiment of the present invention in Figure 8 to illustrate the comparison between the static random access memory proposed by the present invention and the 6T SRAM in Figure 1b in terms of leakage current. The leakage current I _{1 of the} third NMOS transistor (M13) is due to the fact that the voltage level of node A is maintained at the voltage level of V _TM23 in the standby mode of the present invention, and it is assumed that the word line (WL) is in standby mode It is set to the ground voltage, and the bit line (BL) is set to the power supply voltage (V _DD ) when in standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention It is a negative value. In contrast, in the standby mode, the gate-source voltage (V _GS ) of the NMOS transistor (M3) of the previous art in Figure 1b is equal to 0, which causes the gate-induced drain leakage (GIDL) effect according to the gate. Or the results of Figures 3(A) and 3(B) of Patent No. US6865119 dated March 8, 2005 show that for NMOS transistors, when the gate-source voltage is -0.1 volts, the subcritical current is about The source voltage is 1% of the sub-critical current at 0 volts. Therefore, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention caused by the GIDL effect is much smaller than that of the previous art in Figure 1b. NMOS transistor (M3); further, the drain-source voltage (V _DS ) of the third NMOS transistor (M13) of the present invention is the voltage level of the power supply voltage (V _DD ) _minus the V _TM23 , In contrast, in the standby mode, the drain-source voltage (V _DS ) of the NMOS transistor (M3) of the traditional static random access memory in Figure 1b Figure 6T is equal to the power supply voltage (V _DD ), and the energy barrier drops according to the drain (Drain-Induced Barrier Lowering, referred to as DIBL) effect, due to the DIBL effect, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than that of the previous art NMOS transistor (M3) in Figure 1b As a result, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is much smaller than that of the NMOS transistor (M3) of the previous art in Figure 1b.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 , so the source and drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) deduct the voltage level of the V _TM23 . In contrast, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the previous art in Figure 1b in the standby mode is equal to the power supply voltage (V _DD ), according to Due to the DIBL effect, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention is smaller than that of the PMOS transistor (P1) of the prior art in Figure 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of V _TM23 in the standby mode, the node A The voltage level of the node B is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is the ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) of the invention is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) deduct the voltage level of V _TM23 . In contrast, in standby mode, the base-source voltage (V _BS ) of the NMOS transistor (M2) of the previous art in Figure 1b is equal to 0, and the drain of the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first Figure 1b shows the NMOS transistor (M2) of the previous art. It can be seen from the above analysis that the 5T SRAM proposed by the present invention has a lower leakage current than the prior art in Figure 1b.

(IV) Retension mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to ground voltage, the working principle is the same as that of the traditional 5T SRAM with a single bit line in Figure 3. The unit cell will not be repeated here.

【Efficacy of Invention】

The 5T single-port static random access memory with high writing speed proposed by the present invention has the following effects:

(1) Improve the speed of writing logic 0: When logic 0 is written from logic 1, the access transistor (that is, the third NMOS transistor M13) works in the saturation region, and the current in the saturation region is connected to its gate-source The voltage level of the voltage V _{GS (M13)} minus its threshold voltage is proportional to the square, so by designing the bit line (BL) in the first stage of writing logic 0 to be lower than the ground voltage The voltage level can effectively accelerate the speed of writing logic 0;

(2) High degree of design freedom: because the present invention pulls down the storage node (A) below the threshold voltage (V _TM12 ) of the second NMOS transistor (M12) when reading logic 0, there are two mechanisms, one is The word line voltage level conversion circuit (5) is used to pull down the word line voltage applied to the access transistor of the selected cell (ie the third NMOS transistor M13) to be lower than the power supply voltage (ie V _DD -V _TM51 ), the other is to pull down the storage node (A) by the accelerated read voltage (RGND) lower than the ground voltage, so it has the effect of high design freedom;

(3) Effectively reduce the half-selected cell interference during reading: The present invention can use the word line voltage level conversion circuit (5) to apply the access transistor ( That is, the word line voltage of the third NMOS transistor M13) is _pulled down to be lower than the power supply voltage (ie V _DD -V _TM51 ), which on the one hand can reduce the third NMOS transistor (M13) in the half-selected cell Reading interference, on the other hand, by reducing the accelerated reading voltage (RGND) required to satisfy equation (10), the reading interference of the first NMOS transistor (M11) in the half-selected cell can be reduced, so it has Effectively reduce the effect of half-selected cell interference during reading;

(4) High reading speed and avoiding unnecessary power consumption: The present invention adopts a two-stage reading operation. In the first stage of the reading operation, the first low voltage node (VL1) is set to be lower than the ground voltage. Low acceleration reading voltage (RGND), combined with high voltage level control circuit (6) to pull the high voltage node (VH) higher than the voltage level of the power supply voltage (V _DD ), so it is effective Improve the reading speed, and in the second stage of the reading operation, the first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power consumption;

(5) Quickly enter the standby mode: The present invention is provided with a standby start circuit (4) to prompt the SRAM to enter the standby mode quickly, and thereby seek to improve the standby performance of the single-port SRAM;

(6) Increase the speed of writing logic 1 and avoid the problem of difficulty in writing logic 1: The present invention can use the plurality of control circuits (2) and the plurality of write drive circuits (7) during the write operation. ) In order to effectively prevent the difficulty of writing logic 1, it also increases the speed of writing logic 1;

(7) Low standby current: When the present invention is in standby mode, the fifth NMOS transistor (M22) can be turned on to make the voltage level of the first low voltage node (VL1) equal to the first low voltage node (VL1). The voltage levels of the two low voltage nodes (VL2), and the voltage levels are all equal to the threshold voltage level of the sixth NMOS transistor (M23), so the present invention also has the effect of low standby current;

(8) Low number of transistors: For an SRAM array with 1024 columns and 1024 rows, the traditional static random access memory array in Figure 1b Figure 6T requires a total of 1024×1024×6=6,291,456 transistors, and the present invention proposes The static random access memory only needs 1024×1024×5+1024×37+6=5,280,774 transistors, which reduces the number of transistors by 16.1%.

(9) The write operation is completed with high stability: when the write control signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage, so that the write can be completed with high stability Input operation (because the voltage level of the node C is always the ground voltage during the write operation).

Although the present invention has specifically disclosed and described the selected preferred embodiments, those skilled in the art will understand that any possible changes in form or details do not depart from the spirit and scope of the present invention. Therefore, all changes in the relevant technical category are included in the scope of patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Pre-charge circuit

4‧‧‧Standby start circuit

5‧‧‧Character line voltage level conversion circuit

6‧‧‧High voltage level control circuit

7‧‧‧Write drive circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS Transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS Transistor

M13‧‧‧The third NMOS transistor

A‧‧‧Storage Node

B‧‧‧Inverted storage node

BL‧‧‧bit line

WLC‧‧‧Character line control signal

V _DD ‧‧‧Power supply voltage

VH‧‧‧High Voltage Node

VL1‧‧‧The first low voltage node

VL2‧‧‧The second low voltage node

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

M21‧‧‧Fourth NMOS Transistor

M22‧‧‧Fifth NMOS Transistor

M23‧‧‧The sixth NMOS transistor

M24‧‧‧The seventh NMOS transistor

M25‧‧‧Eighth NMOS Transistor

M26‧‧‧Ninth NMOS Transistor

M27‧‧‧Tenth NMOS Transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/RC‧‧‧Inverted reading control signal

/WC‧‧‧Inverted write control signal

INV‧‧‧Third inverter

D1‧‧‧First delay circuit

P31‧‧‧Fourth PMOS Transistor

P‧‧‧Precharge signal

M41‧‧‧Eleventh NMOS Transistor

P41‧‧‧Fifth PMOS Transistor

C‧‧‧node

D2‧‧‧Second delay circuit

WL‧‧‧character line

R‧‧‧Read signal

P51‧‧‧The sixth PMOS transistor

M51‧‧‧Twelfth NMOS Transistor

M52‧‧‧Thirteenth NMOS Transistor

P61‧‧‧The seventh PMOS transistor

P62‧‧‧Eighth PMOS Transistor

I63‧‧‧Fourth inverter

V _{DDH1 ‧‧‧The} highest power supply voltage

V _{DDH2 ‧‧‧The} second highest power supply voltage

P71‧‧‧Ninth PMOS Transistor

M71‧‧‧14th NMOS Transistor

M72‧‧‧Fifteenth NMOS Transistor

M73‧‧‧Sixteenth NMOS Transistor

I71‧‧‧Fifth inverter

I72‧‧‧Sixth inverter

Cap‧‧‧Capacitor

Din‧‧‧Enter data

D3‧‧‧The third delay circuit

D4‧‧‧The fourth delay circuit

Y‧‧‧Line decoder output signal

Claims (10)

A 5T single-port static random access memory with high writing speed, including: a memory array, the memory array is composed of a plurality of rows of memory cell and a plurality of rows of memory cell, each row of memory The unit cell and each row of memory unit cells include multiple memory unit cells (1); multiple control circuits (2), each column of memory unit cells is provided with a control circuit (2); multiple precharge circuits ( 3) Each row of memory cell is equipped with a precharge circuit (3); a standby activation circuit (4), the standby activation circuit (4) prompts the 5T single-port static random access memory to quickly enter the standby mode, In order to effectively improve the standby performance of the 5T single-port static random access memory; a plurality of word-line voltage level conversion circuits (5), each row of memory cell sets a word-line voltage level conversion circuit (5) , In order to effectively reduce the interference of the half-selected cell during reading; a plurality of high-voltage level control circuits (6), each column of memory cell is equipped with a high-voltage level control circuit (6), in order to read logic 0 Improve the reading speed; and a plurality of writing drive circuits (7), each row of memory cell is provided with a writing drive circuit (7) to increase the writing speed during the writing operation; wherein, each memory crystal The cell (1) further includes: a first inverter composed of a first PMOS transistor (P11) and a first NMOS transistor (M11), and the first inverter is connected to a power supply Voltage (V _DD ) and a first low-voltage node (VL1); a second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12), the The second inverter is connected between a high voltage node (VH) and a second low voltage node (VL2); a storage node (A) is formed by the output terminal of the first inverter; The inverting storage node (B) is formed by the output terminal of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and the bit line (BL) And the gate is connected to a word line control signal (WLC); wherein, the first inverter and the second inverter are alternately coupled, that is, the output terminal of the first inverter ( That is, the storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (ie, the inverting storage node B) is connected to the input terminal of the first inverter ; And each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24) ), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC) , A third inverter (INV), a first delay circuit (D1), an acceleration read voltage (RGND), a write control signal (WC), a standby mode Type control signal (S) and an inverted standby mode control signal (/S); wherein the source, gate, and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, and the inverted standby mode The mode control signal (/S) and the second low voltage node (VL2); the source, gate and drain of the fifth NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), The standby mode control signal (S) and the first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to The first low voltage node (VL1); the source, gate, and drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25) and the read control signal (RC) and the first low voltage node (VL1); the source, gate, and drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND) and the first delay circuit The output of (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV) and the eighth NMOS transistor (M25) ) Between the gates; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS The source, gate, and drain of the transistor (M26) are connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1), respectively; the tenth NMOS transistor The source, gate and drain of the crystal (M27) are respectively connected to the ground voltage, the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the third PMOS transistor ( The source, gate and drain of P21) are respectively connected to the inverted standby mode control signal (/S), the write control signal (WC) and the drain of the tenth NMOS transistor (M27); wherein , The drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C) , When the write control signal (WC) is at a logic low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/S), and when the write control signal When (WC) is the logic high level, the voltage level of the node (C) is the ground voltage, so as to stably complete the write operation (because the voltage level of the node C during the write operation is always the ground voltage ); Wherein, the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) in the non-read mode Leakage current during the period; in addition, the standby startup circuit (4) is designed to enter the standby mode During the initial period of the first formula, the parasitic capacitance at the first low voltage node (VL1) is quickly charged to the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23); in addition, each word The cell line voltage level conversion circuit (5) further includes: a sixth PMOS transistor (P51), a twelfth NMOS transistor (M51), a thirteenth NMOS transistor (M52), and the read control signal (RC), an inverted write control signal (/WC), an inverted read control signal (/RC), and the word line control signal (WLC); wherein the sixth PMOS transistor (P51) The source, gate and drain are respectively connected to a word line (WL), the inverted write control signal (/WC) and the word line control signal (WLC); the twelfth NMOS transistor ( The source, gate and drain of M51) are respectively connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL); and the thirteenth NMOS transistor The source, gate and drain of (M52) are respectively connected to the word line control signal (WLC), the inverted read control signal (/RC) and the word line (WL); wherein, each The word line voltage level conversion circuit (5) converts the word line (WL) of the selected unit cell from the power supply voltage (V _DD ) to the power supply voltage (V _DD ) during the read operation. The threshold voltage (V _TM51 ) (ie V _DD -V _TM51 ) of the twelfth NMOS transistor (M51) is then provided to the word line control signal (WLC); and during the write operation, the crystal is selected The power supply voltage (V _DD ) of the word line (WL) of the cell is provided to the word line control signal (WLC); in addition, each high voltage level control circuit (6) further includes: a first Seven PMOS transistors (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), the read control signal (RC), and a first high power supply voltage (V _DDH1 ), wherein the The source, gate and drain of the seventh PMOS transistor (P61) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), the eighth The source, gate and drain of the PMOS transistor (P62) are respectively connected to the first high power supply voltage (V _DDH1 ), the output of the fourth inverter (I63) and the high voltage node (VH) , And the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the eighth PMOS transistor (P62); finally, every write drive The circuit (7) further includes: a ninth PMOS transistor (P71), a fourteenth NMOS transistor (M71), a fifteenth NMOS transistor (M72), a sixteenth NMOS transistor (M73), One fifth inverter (I71), one Six inverters (I72), a capacitor (Cap), an input data (Din), a row of decoder output signals (Y), a third delay circuit (D3), a fourth delay circuit (D4) and a first Two high power supply voltage (V _DDH2 ); wherein, the source, gate and drain of the ninth PMOS transistor (P71) are respectively connected to the second high power supply voltage (V _DDH2 ) and the fifth _inverter The output of the phaser (I71) and the drain of the fourteenth NMOS transistor (M71); the source, gate and drain of the fourteenth NMOS transistor (M71) are respectively connected to the sixteenth NMOS The drain of the transistor (M73), the output of the fifth inverter (I71) and the drain of the ninth PMOS transistor (P71); the source and gate of the fifteenth NMOS transistor (M72) And the drain are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the drain of the ninth PMOS transistor (P71); the source and gate of the sixteenth NMOS transistor (M73) The pole and the drain are respectively connected to the ground voltage, the output of the sixth inverter (I72) and the source of the fourteenth NMOS transistor (M71); the input of the fifth inverter (I71) is For receiving the input data (Din), and the output is connected to the gate of the ninth PMOS transistor (P71), the gate of the fourteenth NMOS transistor (M71) and the third delay circuit (D3) Input; the input of the sixth inverter (I72) is for receiving the row decoder output signal (Y), and the output is connected to the input of the fourth delay circuit (D4) and the sixteenth NMOS transistor ( M73) gate; one end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), and the other end of the capacitor (Cap) is connected to the fourteenth NMOS transistor (M71) The source and the drain of the sixteenth NMOS transistor (M73); wherein the drain of the ninth PMOS transistor (P71), the drain of the fourteenth NMOS transistor (M71) and the fifteenth The drains of the NMOS transistor (M72) are commonly connected to the bit line (BL), and the bit line (BL) is designed to be lower than the ground voltage in the first stage of writing logic 0 , In order to accelerate the speed of writing logic 0, and when writing logic 1, it is designed to be higher than the power supply voltage (V _DD ) of the second highest power supply voltage (V _DDH2 ) level to accelerate writing The speed of logic 1. The 5T single-port static random access memory with high writing speed as described in the first item of the patent application, wherein each precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a pre The charging signal (P) is composed; wherein the source, gate and drain of the fourth PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the pre-charge signal (P) and the corresponding The bit line (BL) is used to precharge the corresponding bit line (BL) to the power supply voltage (V _DD ) by the precharge signal (P) at a logic low level during a precharge period. ) Level. For example, the 5T single-port static random access memory with high writing speed described in the second item of the scope of patent application, wherein the standby startup circuit (4) is composed of a fifth PMOS transistor (P41), a tenth An NMOS transistor (M41), a second delay circuit (D2) and the inverted standby mode control signal (/S) are composed; wherein the source, gate and drain of the fifth PMOS transistor (P41) The poles are respectively connected to the power supply voltage (VDD), the inverted standby mode control signal (/S) and the drain of the eleventh NMOS transistor (M41); the drain of the eleventh NMOS transistor (M41) The source, gate, and drain are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2), and the fifth PMOS The drain of the transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the first Eleven NMOS transistor (M41) gate. For example, the 5T single-port static random access memory with high writing speed described in item 3 of the scope of patent application, wherein the first stage of writing logic 0 in each writing drive circuit (7) satisfies the following equation: V _BL1 = -V _DD ×Cap/(Cap+C _BL ) where, V _BL1 represents the voltage level of the bit line (BL) in the first stage of writing logic 0, and the absolute value of V _BL1 is designed to be less than The threshold voltage of the third NMOS transistor (M13), V _{DD is} the voltage level of the power supply voltage (V _DD ), and Cap and C _BL represent the capacitance value of the capacitor (Cap) and the bit line, respectively (BL) Parasitic capacitance value. For example, the 5T single-port static random access memory with high write speed described in item 4 of the scope of patent application, wherein the storage node (A) is written from logic 0 to the initial instantaneous voltage of writing logic 1 (V _AWI1 ) Satisfies the following equation: V _AWI1 =V _DDH2 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 ) and V _AWI1 >V _TM12 where R _M11 , R _M13 and R _M23 represent the first The on-resistance of the NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23), and V _DDH2 and V _TM12 respectively represent the difference between the second high power supply voltage (V _DDH2 ) The voltage level and the threshold voltage of the second NMOS transistor (M12). For example, the 5T single-port static random access memory with high write speed as described in item 5 of the scope of patent application, wherein the storage node (A) is written with the initial instantaneous voltage (V _AWI0 ) of logic 1 written to logic 0 ) Satisfies the following equation: V _AWI0 =V _BL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) where R _M13 and R _P11 represent the third NMOS transistor respectively (M13) and the on-resistance of the first PMOS transistor (P11), and V _BL1 and V _DD respectively represent the voltage level of the bit line (BL) at the first stage of writing logic 0 and the power supply The voltage level of the voltage (V _DD ). For example, the 5T single-port static random access memory with high write speed as described in the first item of the patent application, wherein the initial instantaneous voltage (V _AR0I ) when the storage node A reads logic 0 satisfies the following equation ：V _AR0I =V _DD ×(R _M11 +(R _M24 +R _M25 )∥R _M26 )/(R _M13 +R _M11 +(R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 )∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 +R _M13 ) and V _AR0I <V _TM12 where R _M11 , R _M13 , R _M24 , R _M25 and R _M26 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25) and the Nine NMOS transistor (M26) on-resistance, and V _DD , RGND and V _TM12 respectively represent the power supply voltage (V _DD ), the accelerated read voltage (RGND) and the second NMOS transistor (M12) critical Voltage. For example, the 5T single-port static random access memory with high write speed described in the first item of the patent application, wherein the first low voltage node (VL1) reads the initial instantaneous voltage ( V _RVL1I ) satisfies the following equation: V _RVL1I =RGND×R _M26 /(R _M26 +R _M24 +R _M25 ) and V _RVL1I >-V _TM11 where RGND represents the accelerated reading voltage, R _M26 , R _M24 and R _M25 Respectively represent the on-resistance of the ninth NMOS transistor (M26), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25), and V _TM11 represents the criticality of the first NMOS transistor (M11) Voltage. For example, the 5T single-port static random access memory with high writing speed described in the first item of the patent application, wherein the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but lower than the sum of the absolute value of the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12) |V _TP12 |, that is, V _DD <V _DDH1 <V _DD +｜V _TP12 ｜ . For example, the 5T single-port static random access memory with high writing speed described in the first item of the patent application, wherein the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the sum of the absolute value of the power supply voltage (V _DD ) and the threshold voltage of the ninth PMOS transistor (P71)｜V _TP71 ｜, that is, V _DD <V _DDH2 <V _DD +｜V _TP71 ｜ .

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