TWI638355B - Five-transistor static random access memory with fast write speed - Google Patents

Abstract

The invention provides a 5t static random access memory with high write speed, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4). A plurality of word line voltage level conversion circuits (5), a plurality of high voltage level control circuits (6), and a plurality of write driving circuits (7), the memory array is composed of a plurality of columns of memory cell cells and A plurality of rows of memory cells are formed. Each column of memory cells is provided with a control circuit (2), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6). The memory cell is provided with a precharge circuit (3) and a write drive circuit (7), so that in the write mode, the plurality of control circuits (2) and the plurality of write drive circuits ( 7) In order to effectively prevent the difficulty of writing logic 1 and also increase the speed of writing logic 1, in the reading mode, on the one hand, the plurality of control circuits (2) and the plurality of high-voltage level control circuits are used. (6) To improve the reading speed and avoid unnecessary power loss On the other hand, the plurality of word line voltage level conversion circuits (5) are used to effectively reduce the half-selected cell interference during reading. In the standby mode, the plurality of control circuits (2) can be used to The leakage current is effectively reduced, and the standby start circuit (4) is designed to effectively promote the static current. State RAM quickly enters standby mode.

Description

5t static random access memory with high write speed

The invention relates to a 5t Static Random Access Memory (SRAM) with high writing speed, and particularly to an effective improvement of SRAM standby performance, and can effectively improve reading speed and writing speed. The SRAM can effectively reduce leakage current, reduce half-selected cell interference during reading, and avoid unnecessary power loss.

As shown in Figure 1a, the conventional 6T static random access memory (SRAM) mainly includes a memory array. The memory array is composed of a plurality of memory blocks (MB ₁ , MB ₂ and so on), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. A column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL ₂ etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to one in the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic circuit diagram of a 6T static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors, and the NMOS transistor (M1) ) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is the word line, and BL and BLB It is a bit line and a complementary bit line, respectively. Since this SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) The other driving transistor is turned on. The initial instantaneous voltage (V _AR ) of node A must satisfy the equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) <V _TM2 ( 1)

Among them, V _AR represents the initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply. Voltage and the threshold voltage of the NMOS transistor (M2), which results in the current driving capability ratio (ie, cell ratio) between the driving transistor and the access transistor is generally set between 2.2 and 3.5 (refer to 98 US Patent No. 60760B2 of October 20, 2014, column 2 lines 8-10).

Figure 1b shows the simulation results of the HSPICE transient analysis of the 6T SRAM cell during a write operation. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T SRAM cell with a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T SRAM cell The body cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width-to-length ratio of M2 and M3 (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM cell), there is a problem that it is quite difficult to write logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transmitted from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 And R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) and Equation (2), it can be seen that the initial instantaneous voltage (V _AW ) written is smaller than the NMOS transistor (M2) Threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.

So far, many methods have been proposed to solve the difficulty of writing logic 1 in the static random access memory cell of FIG. 4 above. The first method is to lower the voltage level supplied to the memory cell to Lower than the power supply voltage (V _DD ), so that when writing logic 1 (assuming that node A originally stores logic 0, but now wants to write logic 1), by increasing the on-resistance of the driving transistor NMOS transistor M1 to During the writing operation, the driving transistor NMOS transistor M2 can be turned on to complete the operation of writing logic 1. These methods are, for example, the "Memory System" proposed by Patent Document 1 (April 27, 1999, US 7706203B2). 5. Patent Literature 2 (TW I426514B of February 11, 103) "5T Static Random Access Memory Reducing Power Supply Voltage during Write Operation" and Patent Literature 3 (TW I534802B of May 21, 105 "Semiconductor memory", etc., can effectively solve the problem of writing logic 1, but because these methods need to set up dual power and / or discharge paths, and these methods must be supplied when writing The voltage level to the memory cell is lowered below the power supply It should voltage (V _DD) and was written after the completion of the voltage supplied to the bit memory cell reverts to a quasi power supply voltage (V _DD), and therefore will result in unnecessary power consumption.

The second method is to redesign the channel width-to-length ratio of PMOS transistors P1 and P2 and NMOS transistors M1, M2, and M3. For example, Non-Patent Document 4 (Satyanand Nalam et al., "5T SRAM with asymmetric sizing for improved read stability"", IEEE Journal of Solid-State Circuits ., Vol. 46. No. 10, pp 2431-2442, Oct. 2011.), but because the channel width-to-length ratios of PMOS transistors P1 and P2 are different and NMOS transistor M1 The channel width to length ratio of M2 is not the same, so the static noise margin (SNM) will be reduced.

The third method is to raise the voltage level of the word line (WL) of the access transistor M3 gate of the memory cell to a voltage higher than the power supply voltage (V _DD ) during writing to facilitate writing logic. At 1 (assuming that node A originally stores logic 0, but now wants to write logic 1), it is completed by reducing the on-resistance of the access transistor M3 so that the driving transistor NMOS transistor M2 is turned on at the initial moment of writing. An operation for writing a logic 1 is, for example, "Port static random access memory for increasing a word line voltage level during a write operation" proposed in Patent Document 5 (TW I404065B, August 1, 102), but During writing, the voltage level of the word line (WL) of the access transistor M3 gate to the memory cell is raised to a level higher than the power supply voltage (V _DD ), which results in an increase of half during writing. Selected cell disturbance (half-selected cell disturbance).

The fourth method is to raise the source voltage level of the driving transistor NMOS transistor M1 to higher than the ground voltage during writing, so as to write logic 1 (assuming that node A originally stores logic 0, but now wants to write Logic 1), by increasing the drain voltage level of the driving transistor NMOS transistor M1, so that the driving transistor NMOS transistor M2 can be turned on at the initial writing time, The operation of writing logic 1 is implemented, for example, "Port Static Random Access Memory (7)" proposed in Patent Document 6 (TW I536382B of June 1, 105), and Patent Document 7 (April 11, 105 Japanese Serial No. TW I529712B), "Port Static Random Access Memory (5)" and Patent Document 8 (TW I529712B, April 11, 105) proposed "Port Static Random Access Memory" (6) "and so on.

The fifth method is to use back gate bias technology to increase the threshold voltage of the driving transistor NMOS transistor M1 and reduce the threshold voltage of the access transistor M3 at the same time to facilitate writing logic. 1 (assuming that node A originally stores logic 0, but now wants to write logic 1), by increasing the drain voltage level of the driving transistor NMOS transistor M1, the driving transistor NMOS can be driven at the initial moment of writing. The crystal M2 is turned on, and the operation of writing the logic 1 is completed. However, this method requires the use of a split well, which increases the complexity of the process and is therefore less used.

The sixth method is to redesign the connection relationship between PMOS transistors P1 and P2 and NMOS transistors M1, M2, and M3. For example, non-patent document 9 (Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process ”, 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and Non-Patent Document 10 (Shyam Akashe et al.,“ High density and low leakage current based 5T SRAM cell using 45nm technology ", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.) and so on.

Although the above-mentioned technologies can effectively solve the problem of writing logic 1, the technologies do not take into account the word line voltage level conversion circuit and high voltage level control circuit to effectively reduce the read At the same time, half of the selected cell interference can also effectively improve the reading speed; furthermore, these technologies also do not take into account that when the logic 1 is written, the voltage level of the bit line is raised to higher than Power supply voltage write drive circuit to effectively prevent the difficulty of writing logic 1 At the same time, it can effectively improve the writing speed, so there is still room for improvement

In view of this, the main object of the present invention is to provide a 5t static random access memory with high write speed, which can effectively reduce the word line voltage level conversion circuit and high voltage level control circuit. At the same time that half-selected cell interference during reading can also effectively improve the reading speed.

A secondary object of the present invention is to provide a 5t static random access memory with high write speed, which can effectively prevent the write drive circuit by pulling the bit line voltage level higher than the power supply voltage. While writing logic 1 is difficult, it can also effectively improve the writing speed.

Another object of the present invention is to provide a 5t static random access memory with high write speed, which can effectively improve the reading speed by the control circuit, and can improve the reading by the two-stage read control. Take the speed while avoiding unnecessary power loss.

The invention provides a 5t static random access memory with high write speed, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4). A plurality of word line voltage level conversion circuits (5), a plurality of high voltage level control circuits (6), and a plurality of write driving circuits (7), the memory array is composed of a plurality of columns of memory cell cells and A plurality of rows of memory cells are formed. Each column of memory cells is provided with a control circuit (2), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6). The memory cell is provided with a precharge circuit (3) and a write drive circuit (7), so that in the write mode, the plurality of control circuits (2) and the plurality of write drive circuits ( 7) In order to effectively prevent the difficulty of writing logic 1 and also increase the speed of writing logic 1, in the reading mode, on the one hand, the plurality of control circuits (2) And the plurality of high voltage level control circuits (6) are used to improve the reading speed and avoid unnecessary power loss. On the other hand, the plurality of word line voltage level conversion circuits (5) are effective Reduce half-selected cell interference during reading. In standby mode, the control circuit (2) can be used to effectively reduce leakage current, and the standby start circuit (4) can be used to effectively promote Static random access memory quickly enters standby mode.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧Word line voltage level conversion circuit

6‧‧‧High voltage level control circuit

7‧‧‧write drive circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

BL‧‧‧bit line

WLC‧‧‧Word line control signal

V _DD ‧‧‧ Power supply voltage

VH‧‧‧High Voltage Node

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

S‧‧‧Standby mode control signal

/ S‧‧‧ Inverted standby mode control signal

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/ RC‧‧‧ Inverted read control signal

/ WC‧‧‧ Inverted write control signal

INV‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Fourth PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧11th NMOS transistor

P41‧‧‧Fifth PMOS transistor

C‧‧‧node

D2‧‧‧Second Delay Circuit

WL‧‧‧Character Line

R‧‧‧ Read signal

P51‧‧‧Sixth PMOS transistor

M51‧‧‧Twelfth NMOS Transistor

M52‧‧‧Thirteenth NMOS Transistor

P61‧‧‧Seventh PMOS transistor

P62‧‧‧eighth PMOS transistor

I63‧‧‧Fourth inverter

V _DDH1 ‧‧‧ Highest power supply voltage

V _DDH2 ‧‧‧ the second highest power supply voltage

P71‧‧‧9th PMOS transistor

P72‧‧‧Tenth PMOS transistor

P73‧‧‧11th PMOS transistor

P74‧‧‧The twelfth PMOS transistor

M71‧‧‧fourteenth NMOS transistor

M72‧‧‧15th NMOS Transistor

I73‧‧‧Fifth inverter

Din‧‧‧Enter data

BLB ₁ … BLB _m ‧‧‧ complementary bit line

BLB‧‧‧ Complementary Bit Line

MB ₁ … MB _k ‧‧‧Memory block

WL ₁ … WL _n ‧‧‧Character line

BL ₁ … BL _m ‧‧‧bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

M1… M4‧‧‧NMOS transistor

P1… P2‧‧‧PMOS transistor

WC‧‧‧ write control signal

Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a schematic circuit diagram of the preferred embodiment of the present invention; FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention during writing in FIG. 5; and FIG. 7 is a diagram of the fifth embodiment. The timing diagram of the write operation of the preferred embodiment of the invention; Figure 8 is a simplified circuit diagram showing the preferred embodiment of the invention during reading in Figure 5; Figure 9 is the preferred embodiment of the invention shown in Figure 5 Simplified circuit diagram during standby.

According to the above main object, the present invention proposes a 5t static random access memory with high write speed, which mainly includes a memory array. The memory array is composed of a plurality of memory cells and a plurality of memory cells. Each unit of memory cell and each row of memory cell includes a plurality of memory cells (1); a plurality of control circuits (2), each A column memory cell is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) It promotes the SRAM to quickly enter the standby mode to effectively improve the standby efficiency of the SRAM; a plurality of word line voltage level conversion circuits (5), each column of memory cells is provided with a word line voltage level conversion circuit (5); A plurality of high voltage level control circuits (6), each column of memory cell is provided with a high voltage level control circuit (6); and a plurality of write drive circuits (7), each row of memory cell is provided with a write Into the drive circuit (7).

For the convenience of description, the 5t static random access memory shown in FIG. 5 consists of only one memory cell (1), one word line (WL), one bit line (BL), and a control circuit ( 2), a precharge circuit (3), a standby start circuit (4), a word line voltage level conversion circuit (5), a high voltage level control circuit (6), and a write drive circuit (7 ) As an example. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) The crystal P12 is composed of a second NMOS transistor M12) and a third NMOS transistor (M13), wherein the first inverter and the second inverter are mutually coupled and connected, that is, the first inverter The output of the inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is connected to the input of the first inverter, and the first inverter The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It is worth noting here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel aspect ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also has the same channel width-to-length ratio.

Please refer to FIG. 5 again, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal (/ WC), a standby mode control signal (S) and an inverted standby mode control signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, the inverted standby mode control signal (/ S) and a second low voltage node (VL2); the fifth The source, gate, and drain of the NMOS transistor (M22) are connected to the second low voltage node (VL2), the standby mode control signal (S), and a first low voltage node (VL1); the first The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate, drain and drain are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor (M25) The source, gate, and drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the Read control signal ( RC), and the output is connected to the input of the first delay circuit (D1); the source, gate, and drain of the ninth NMOS transistor (M26) are connected to the ground voltage and the tenth NMOS transistor, respectively. The drain of (M27) and the first low voltage node (VL1); the tenth NMOS The source, gate and drain of the transistor (M27) are connected to the gate of the write control signal (WC), the standby mode control signal (S) and the ninth NMOS transistor (M26), respectively; and The source, gate and drain of the third PMOS transistor (P21) are connected to the inverted write control signal (/ WC), the standby mode control signal (S) and the tenth NMOS transistor ( M27). It is worth noting here that the inverted standby mode control signal (/ S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/ WC) is obtained by The write control signal (WC) is obtained via another inverter.

It is worth noting here that the source of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together and A node (C) is formed. When the standby mode control signal (S) is a logic low level, the voltage level of the node (C) is the logic level of the inverted write control signal (/ WC), and when When the standby mode control signal (S) is a logic high level, the voltage level of the node (C) is the logic level of the write control signal (WC).

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (i.e., the first low voltage node VL1) of the driving transistor (i.e., the first NMOS transistor M11) that is closer to the bit line (BL) is set to a predetermined voltage (i.e., the first low-voltage node VL1) that is higher than the ground voltage (i.e. The gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (i.e., the second NMOS transistor M12) in the selected unit cell (i.e., the second NMOS transistor M12) The low-voltage node VL2) is set to a ground voltage to prevent the problem of writing logic 1 from being difficult.

In the first stage of the read mode, the source voltage (that is, the first low voltage) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (BL) in the selected cell is selected. The node VL1) is set to the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed. In the second stage, the source voltage of the driving transistor (ie, the first NMOS transistor M11) which is closer to the bit line (BL) in the selected unit cell is set back to the ground voltage in order to reduce unnecessary power consumption. The time interval between the second phase and the first phase of the mode is equal to that when the read control signal (RC) changes from a logic low level to a logic high level and reaches the gate of the eighth NMOS transistor (M25). The voltage is enough for the time until the eighth NMOS transistor (M25) is turned off, and its value can be determined by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1). Adjustment.

In the standby mode, the source voltages of the driving transistors in all the memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current. In the hold mode, the driving voltages in the memory cells are set. The source voltage of the crystal is set to ground voltage in order to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal. At this time, only the write signal (W ) Signal and the word line (WL) signal are at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read signal (R) and the word The result of the AND operation of the element line (WL) signal. It is worth noting that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (M24). Current.

Please refer to Fig. 5. The precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so that during the precharge period, the precharge signal (P ) To pre-charge the bit line (BL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 5 again, the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (VDD), the inverting standby mode control signal (/ S), and the eleventh NMOS transistor ( M41); the source, gate, and drain of the eleventh NMOS transistor (M41) are connected to the first low voltage node (VL1), the output of the second delay circuit (D2), and The drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is connected To the gate of the eleventh NMOS transistor (M41).

Please refer to FIG. 5 again, the word line voltage level conversion circuit (5) is Six PMOS transistors (P51), a twelfth NMOS transistor (M51), a thirteenth NMOS transistor (M52), the read control signal (RC), the inverted write control signal (/ WC) , An inverted read control signal (/ RC) and a word line control signal (WLC). The source, gate, and drain of the sixth PMOS transistor (P51) are connected to the word line (WL), the inverted write control signal (/ WC), and the word line control signal (WLC), respectively. ); The source, gate and drain of the twelfth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL ); And the source, gate and drain of the thirteenth NMOS transistor (M52) are connected to the word line control signal (WLC), the inverted read control signal (/ RC) and the word, respectively Element line (WL).

The detailed working voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

V _TM51 represents the threshold voltage of the twelfth NMOS transistor (M51). It is worth noting here that on the one hand, the present invention uses a two-stage read control to improve the reading speed while avoiding unnecessary power loss, and on the other hand, the word line voltage level conversion circuit ( 5) During the reading operation, the word line voltage applied to the access transistor of the selected cell is _pulled down to a voltage lower than the power supply voltage (that is, V _DD -V _TM51 ) to effectively reduce the half of the reading time. Selected cell interference.

Please refer to FIG. 5 again. The high-voltage level control circuit (6) is composed of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), and the read It is composed of a control signal (RC) and a first high power supply voltage (V _DDH1 ). The source, gate and drain of the seventh PMOS transistor (P61) are connected to the power supply voltage (V _DD ), the read control signal (RC) and a high voltage node (VH), the source, gate and drain of the eighth PMOS transistor (P62) are connected to the first high power supply voltage ( V _DDH1 ), the output of the fourth inverter (I63) and the high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC) and output It is connected to the gate of the eighth PMOS transistor (P62). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to FIG. 5 again. The write driving circuit (7) is composed of a ninth PMOS transistor (P71), a tenth PMOS transistor (P72), an eleventh PMOS transistor (P73), and a first Twelve PMOS transistors (P74), a fourteenth NMOS transistor (M71), a fifteenth NMOS transistor (M72), a fifth inverter (I73), an input data (Din), and a first It consists of two high power supply voltages (V _DDH2 ). The source, gate and drain of the ninth PMOS transistor (P71) are connected to the second high power supply voltage (V _DDH2 ) and the input data. (Din) and the drain of the fourteenth NMOS transistor (M71), and the source, gate and drain of the tenth PMOS transistor (P72) are respectively connected to the second high power supply voltage (V _DDH2 ), The drain of the fifteenth NMOS transistor (M72) and the drain of the fourteenth NMOS transistor (M71), the source, gate, and drain of the eleventh PMOS transistor (P73) Connected to the second high power supply voltage (V _DDH2 ), the drain of the fourteenth NMOS transistor (M71) and the drain of the fifteenth NMOS transistor (M72), and the twelfth PMOS transistor (P74) The source, gate and drain are connected separately Connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (I73) and the drain of the fifteenth NMOS transistor (M72), and the fourteenth NMOS transistor (M71) The source, gate and drain are connected to the ground voltage, the input data (Din) and the drain of the ninth PMOS transistor (P71), and the source of the fifteenth NMOS transistor (M72). , The gate and the drain are connected to the ground voltage, the output of the fifth inverter (I73) and the drain of the twelfth PMOS transistor (P74), and the fifth inverter (I73) The input is for receiving the input data (Din), and the output is connected to the gate of the twelfth PMOS transistor (P74) and the gate of the fifteenth NMOS transistor (M72), where the tenth A drain of a PMOS transistor (P73), a drain of the twelfth PMOS transistor (P74), and a drain of the fifteenth NMOS transistor (M72) are connected to the bit line (BL), The bit line (BL) is the level of the ground voltage when a logic 0 is written, and the bit line (BL) is the level of the second high power supply voltage (V _DDH2 ) when a logic 1 is written. It is worth noting here that the voltage level of the second high power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ) to accelerate the speed of writing to logic one.

The working mode of the Ziyibu SRAM is described in Figure 5. The working principle of the preferred embodiment of the present invention is as follows:

(I) write mode

Before the write operation starts, the standby mode control signal (S) is at a logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth NMOS transistor (M27) is turned off (OFF) Because the inverted write control signal (/ WC) is at a logic high level at this time, The drain of the third PMOS transistor (P21) is at a logic high level. The drain of the third PMOS transistor (P21) at the logic high level will turn on the ninth NMOS transistor (M26) and make the first The low voltage node (VL1) is at ground voltage.

During the write operation, because the inverted write control signal (/ WC) is at a logic low level, the node C is at a logic low level, so that the ninth NMOS transistor (M26) is turned off, and the The first low voltage node (VL1) is equal to the gate-source voltage V _{GS (M23} ) of the sixth NMOS transistor _(M23) , thereby effectively preventing the problem of writing logic 1 from being difficult. FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during a writing period.

The following describes how the write operation of the preferred embodiment of the present invention shown in FIG. 6 is completed according to the four write states of the port SRAM.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on. Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) changes from OFF to OFF Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on. Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ). The node A The voltage of R is increased following the voltage of the word line control signal (WLC).

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, Because the bit line (BL) is the voltage level of the second high power supply voltage (V _DDH2 ), and because the first NMOS transistor (M11) is still ON and the node B is at a voltage level that is close to The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V _AWI ) written at the node A satisfies the equation ( 3): V _AWI = V _DDH2 × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 (3)

Among them, V _AWI represents the initial instantaneous voltage of node A, and R _M11 , R _M13, and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13), and the sixth NMOS transistor, respectively. (M23), and V _DDH2 and V _TM12 respectively represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12). Because the second high power supply voltage (V _DDH2 ) voltage level is designed to be higher than the voltage level of the power supply voltage (V _DD ), and a gate equal to the sixth NMOS transistor (M23) is provided at the first low voltage node (VL1) -The voltage level of the source voltage V _{GS (M23)} , so the voltage level of node A can be easily set to be higher than the voltage level of node A of the conventional 5T SRAM cell in Figure 4 The standard is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level, and the lower voltage level of the node B will make the first The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value. The higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A. The The higher voltage level of node A passes through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of B will pass through the first inverter (consisting of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A will obtain a higher voltage level, and so on. Then, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of the logic 1 is completed.

It is worth noting here that the first low voltage node (VL1) originally stores logic 0 in node A, and during the writing of logic 1, it has a gate-source voltage V equal to the sixth NMOS transistor (M23). The voltage level of _{GS (M23)} , and after the logic 1 is written, it will have the ground voltage level due to the discharge through the ninth NMOS transistor (M26).

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), since the node A is the voltage level of the power supply voltage (V _DD ), and the bit line (BL) is the voltage level of the second high power supply voltage (V _DDH2 ), so the third NMOS transistor (M13) will remain in the OFF state; at this time, because the first PMOS transistor (M13) P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At the threshold voltage, the third NMOS transistor (M13) changes from OFF to ON. At this time, because the bit line (BL) is Low (ground voltage), the node A and the The first low voltage node (VL1) is discharged to complete the logic 0 writing operation until the writing cycle ends.

The preferred embodiment of the present invention shown in FIG. 6 is the simulation result of HSPICE transient analysis during a write operation. As shown in FIG. 7, it is simulated using TSMC 90 nm CMOS process parameters. From the simulation result, It can be confirmed that the 5T static random access memory proposed by the present invention can effectively increase the voltage level of the first low voltage node (VL1) during writing to effectively avoid the 5T static with a single bit line. The random access memory cell suffers from the difficulty of writing logic 1.

(II) read mode

Before the read operation starts, the standby mode control signal (S) is at a logic low level, and the inverted write control signal (/ WC) is at a logic high level, so that the node C is at a logic high level, The node C will turn on the ninth NMOS transistor (M26), and make the first low voltage node (VL1) a ground voltage. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off, and the eighth NMOS transistor (M25) is turned on.

It is worth noting here that during the pre-charging period before the read operation starts, the pre-charging signal (P) is a logic low level, thereby pre-charging the corresponding bit line (BL) to the power supply. The voltage (V _DD ) level, but because, for example, the operating voltage of a process technology below 20 nanometers will fall below 1 volt will cause the reading speed to fall and fail to meet the specifications. Therefore, the present invention proposes a two-stage reading Take control to increase read speed and meet specifications while avoiding unnecessary power loss.

The preferred embodiment of the present invention shown in FIG. 5 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of a read operation, the read The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately The accelerated reading voltage (RGND) whose ground voltage is low, and the accelerated reading voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed.

In the second phase of one of the read operations, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor (M25) is turned off, so the first low voltage node (VL1) will be at a ground voltage through the ninth NMOS transistor (M26) that is turned on, thereby effectively reducing unnecessary power consumption. It is worth noting here that the time interval between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level. The gate voltage of the eight NMOS transistor (M25) is enough time to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit. (D1) Adjust the delay time provided. Furthermore, the ninth NMOS transistor (M26) is turned on regardless of whether the first stage or the second stage of the read operation (because the gate of the ninth NMOS transistor (M26) is at a logic high level) ). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during reading.

Next, the two read states of the port SRAM are used to explain how the preferred embodiment of the present invention in FIG. 8 uses the control circuit (2) and the high-voltage level control circuit (6) to improve the performance. At the same time of high reading speed, it also avoids unnecessary power consumption. On the other hand, the word line voltage level conversion circuit (5) is used to effectively reduce half-selected cell interference during reading.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON. The node A and the node B are the power supply voltages, respectively. (V _DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, the word line control signal (WLC) deducted the threshold voltage (ie, V _DD -V _TM51 ) of the twelfth NMOS transistor (M51) for the power supply voltage, and because the node A was The voltage level of the power supply voltage (V _DD ), so the third NMOS transistor (M13) is in an OFF state, thereby effectively maintaining the bit line (BL) as the power supply voltage until read At the end of the cycle, the operation of reading the logic 1 is successfully completed. It is worth noting here that during the read operation, the word line control signal (WLC) _deducts the threshold voltage of the twelfth NMOS transistor (M51) for the power supply voltage (that is, V _DD -V _TM51 ). Therefore, half-selected cell interference during reading can be effectively reduced. In addition, in the first stage of the read operation, the initial instant voltage (V _RVL1I ) of the first low-voltage node (VL1) when reading logic 1 must satisfy equation (4): V _RVL1I = RGND × R _M26 / (R _M26 + R _M24 + R _M25 )>-V _TM11 (4) to effectively prevent half-selected cell interference during reading, where V _RVL1I indicates that the first low voltage node (VL1) is in reading Read the initial instantaneous voltage at logic 1, RGND represents the accelerated read voltage, R _M26 represents the on-resistance of the ninth NMOS transistor (M26), and R _M24 represents the on-resistance of the seventh NMOS transistor (M24). R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM11 represents the critical voltage of the first NMOS transistor (M11); in the second stage of the read operation, the first low-voltage node The voltage (V _RVL1 ) of (VL1) can be expressed by equation (5): V _RVL1 = ground voltage (5). This can effectively reduce unnecessary power consumption.

Furthermore, in order to effectively reduce the half-selected cell interference and effectively reduce the leakage current during reading, the absolute value of the accelerated read voltage (RGND) can be set more conservatively than that of the first NMOS transistor (M11). The threshold voltage (V _TM11 ), that is, | RGND | <V _TM11 (6), | RGND | and V _TM11 respectively represent the absolute value of the accelerated read voltage and the threshold voltage of the first NMOS transistor (M11).

(2) Read logic 0 (node A stores logic 0):

Before the read operation occurs, the first NMOS transistor (M11) is ON and the second NMOS transistor (M12) is OFF. The node (A) and the node (B) are respectively The ground voltage and the first high power supply voltage (V _DDH1 ), and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). Because the first NMOS transistor (M11) is ON, when the read operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage deducts the twelfth NMOS Threshold voltage V _DD -V _{TM51 of} transistor M51). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, The initial instantaneous voltage (V _AR0I ) of this node A must satisfy equation (7): V _AR0I = V _DD × (R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) / (R _M13 + R _M11 + ( R _M24 + R _M25 ) ∥R _M26 ) + RGND × (R _M11 + R _M13 ) ∥R _M26 / (R _M24 + R _M25 + (R _M11 + R _M13 ) ∥R _M26 ) × R _M13 / (R _M11 + R _M13 ) <V _TM12 (7) to avoid turning on the second NMOS transistor (M12), where V _AR0I represents the initial instantaneous voltage when node A reads logic 0, R _M11 , R _M13, R _M24, R _M25 and R _M26 represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25), and the ninth NMOS The on-resistance of the transistor (M26), and V _DD , RGND and V _TM12 represent the _threshold voltages of the power supply voltage (V _DD ), the accelerated read voltage (RGND) and the second NMOS transistor (M12), respectively. It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (M11). Furthermore, the word line control signal (WLC) of the present invention during reading is set to the power supply voltage to _deduct the threshold voltage (V _DD -V _TM51 ) of the thirteenth NMOS transistor (M51), which On the one hand, it can effectively reduce the half-selected cell interference during reading, and on the other hand, it is easier to satisfy equation (7) by increasing the on-resistance (R _M13 ) of the third NMOS transistor (M13).

Moreover, during the reading of logic 0, since node B is the first high power supply voltage (V _DDH1 ), and the first low voltage node (VL1) is a voltage lower than the ground voltage, because the first high The power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ). Therefore, the read speed can be effectively improved by increasing the conduction degree of the first NMOS transistor (M11). It is worth noting here that the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor ( P12) the sum of the absolute value of the threshold voltage | V _TP12 |, that is, V _DD <V _DDH1 <V _DD + | V _TP12 | (8) where | V _TP12 | represents the threshold voltage of the second PMOS transistor (P12) The absolute value.

(III) Standby mode

First, explain how the standby start circuit (4) in Fig. 5 prompts 5t SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/ S) is Logic High, the inverting standby mode control signal (/ S) of the logic High turns off the fourth PMOS transistor (P41) and turns on the twelfth NMOS transistor (M41); then After entering the standby mode, the inverted standby mode control signal (/ S) is logic Low, and the inverted standby mode control signal (/ S) of logic low causes the fourth PMOS transistor (P41) to be turned on (ON). , But in the initial period of the standby mode (the initial period is equal to the inversion of the standby mode control signal (/ S) from logic High to logic Low counting from the gate voltage to the twelfth NMOS transistor (M41) The time until the twelfth NMOS transistor (M41) is turned off, which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor (M41) is still on (ON), so that the first low-voltage node (VL1) can be quickly charged to the sixth NMOS transistor The voltage level of the threshold voltage (V _TM23 ) of the body (M23), that is, the port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and stops supplying current.

Please refer to FIG. 5. In the standby mode, the standby mode control signal (S) is at a logic high level, and the inverted standby mode control signal (/ S) is at a logic low level, and the logic low level is at the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low-voltage node (VL1) is equal to the voltage level of the second low-voltage node (VL2), and the voltage levels will all be equal to the criticality of the sixth NMOS transistor (M23) The voltage level of the voltage (V _TM23 ). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during the standby period.

Next, how to reduce the leakage current in the standby mode of the present invention will be described. Please refer to FIG. 9. FIG. 9 describes the respective leakage currents I ₁ generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that because the second low voltage node (VL2 The voltage level of) is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of node A being logic Low is also maintained at the voltage level of V _TM23 ) , And the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9 to explain the comparison of the static random access memory proposed by the present invention with the 6T SRAM of FIG. 1b in terms of leakage current. The leakage current I _{1 of the} third NMOS transistor (M13), because the voltage level of the node A is maintained at the voltage level of the V _TM23 in the standby mode of the present invention, and it is assumed that the word line (WL) is in the standby mode Is set to ground voltage, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention It is a negative value. In contrast, in the standby mode, the gate-source voltage (V _GS ) of the NMOS transistor (M3) of the prior art in FIG. 1b is equal to 0. According to the gate-induced drain leakage (GIDL) effect Or according to the results of Figures 3 (A) and 3 (B) of Patent No. US6865119 on March 8, 2005, it can be known that for NMOS transistors, the sub-critical current when the gate-source voltage is -0.1 volt is about the gate The source voltage is 1% of the subcritical current at 0 volts, so the current flowing through the invention caused by the GIDL effect is caused by The leakage current I _{1 of} the third NMOS transistor (M13) is much smaller than that of the NMOS transistor (M3) of the prior art in FIG. 1b; further, the drain-source voltage of the third NMOS transistor (M13) of the present invention ( V _DS ) _deducts the voltage level of V _TM23 for the power supply voltage (V _DD ). In contrast, in the standby mode, the drain source voltage of the NMOS transistor (M3) of the traditional random access memory of FIG. (V _DS ) is equal to the power supply voltage (V _DD ). According to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor caused by the DIBL effect flows through the present invention. The leakage current I _{1 of} (M13) is also smaller than the NMOS transistor (M3) of the prior art in FIG. 1b; as a result, the leakage current I ₁ of the third NMOS transistor (M13) flowing through the present invention is much smaller than that of FIG. 1b. Those who are skilled in NMOS transistor (M3).

Then regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 . Therefore, the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) _deducts the voltage level of the V _TM23 . In contrast, in the standby mode, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the prior art in FIG. 1b is equal to the power supply voltage (V _DD ). DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, node A The voltage level of V _TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, in the standby mode, the base-source voltage (V _BS ) of the NMOS transistor (M2) of the prior art in FIG. The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and DIBL effect, it can be known that the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first Figure 1b shows the NMOS transistor (M2) of the prior art. It can be known from the above analysis that the 5T static random access memory proposed by the present invention has a lower leakage current than the prior art of FIG. 1b.

(IV) Retension mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as that of the traditional 5T SRAM cell with a single bit line in Figure 3. I won't go into details here.

[Effect of Invention]

The 5t static random access memory with high write speed proposed by the present invention has the following effects: (1) high design freedom: because the present invention pulls the storage node (A) to low when reading logic 0 There are two mechanisms for the threshold voltage (V _TM12 ) of the second NMOS transistor (M12). One is a word line voltage level conversion circuit (5) to apply an access transistor (5) to a selected cell ( That is, the word line voltage of the third NMOS transistor M13) is _pulled down below the power supply voltage (that is, V _DD -V _TM51 ), and the other is to pull down the storage node by accelerating the read voltage (RGND) below the ground voltage. (A) Therefore, it has the effect of high design freedom; (2) Effectively reduces half-selected cell interference during reading: The present invention can use the word line voltage level conversion circuit (5) for reading operations During the pull-down of the word line voltage applied to the access transistor (ie, the third NMOS transistor M13) to the selected unit cell to a voltage lower than the power supply voltage (ie, V _DD -V _TM51 ), it can reduce half selection The read interference of the third NMOS transistor (M13) in the unit cell, on the other hand, can reduce the need to satisfy equation (7) by mitigating Speed up the read voltage (RGND) to reduce the read interference of the first NMOS transistor (M11) in the half-selected cell, so it has the effect of effectively reducing the half-selected cell interference during reading; (3) high read Take the speed and avoid unnecessary power consumption: The present invention uses a two-stage read operation. In the first stage of the read operation, the first low-voltage node (VL1) is set to accelerate reading at a lower level than the ground voltage. Voltage (RGND) and cooperate with the high voltage level control circuit (6) to pull the high voltage node (VH) higher than the voltage level of the power supply voltage (V _DD ), so the reading speed can be effectively improved, In the second stage of the reading operation, the first low voltage node (VL1) is set back to the ground voltage in order to reduce unnecessary power consumption; (4) Quickly enter the standby mode: Since the present invention is provided with a standby start circuit ( 4) To prompt the SRAM to enter the standby mode quickly, and to improve the standby performance of the port SRAM; (5) To increase the speed of writing the logic 1 and avoid the problem of writing the logic 1 difficult: the invention is used for the writing operation Can be controlled by the plurality of control circuits (2) and The plurality of write driving circuits (7) can effectively prevent the difficulty of writing the logic 1 while also increasing the speed of writing the logic 1. (6) Low standby current: Since the present invention is in the standby mode, it can be turned on by The fifth NMOS transistor (M22), so that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to The threshold voltage level of the sixth NMOS transistor (M23), so the present invention also has the effect of low standby current; (7) Low transistor number: For SRAM arrays with 1024 columns and 1024 rows, the traditional 1b FIG. 6T The static random access memory array requires a total of 1024 × 1024 × 6 = 6,291,456 transistors, while the static random access memory proposed by the present invention only needs 1024 × 1024 × 5 + 1024 × 30 + 6 = 5,273,606 Transistor, which reduces the number of transistors by 16.2%.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.

Claims (10)

A 5t static random access memory with high write speed includes: a memory array, the memory array is composed of a plurality of rows of memory cell cells and a plurality of rows of memory cell cells, and each row of memory cell cells And each row of memory cell contains a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3) Each row of memory cell is provided with a pre-charge circuit (3); a standby start circuit (4), the standby start circuit (4) prompts the 5t static random access memory to quickly enter the standby mode to effectively improve the 5t static random access memory standby performance; multiple word line voltage level conversion circuits (5), each row of memory cell is provided with a word line voltage level conversion circuit (5) to effectively reduce reading Half-selected cell interference; a plurality of high-voltage level control circuits (6), each column of memory cells is provided with a high-voltage level control circuit (6) to increase the reading speed when logic 0 is read; and Multiple write drive circuits (7), each line of memory The body cell is provided with a write driving circuit (7) to increase the writing speed when the logic 1 is written; wherein each memory cell (1) further includes: a first inverter, A PMOS transistor (P11) and a first NMOS transistor (M11), the first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); A second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12). The second inverter is connected between a high voltage node (VH) and a first Between two low-voltage nodes (VL2); a storage node (A) formed by the output terminal of the first inverter; an inverting storage node (B) formed by the output of the second inverter A third NMOS transistor (M13) is connected between the storage node (A) and a bit line (BL), and the gate is connected to a word line control signal (WLC); The first inverter and the second inverter are connected in an interactive coupling, that is, the output terminal of the first inverter (that is, the storage node A) is connected to the input terminal of the second inverter. And the second inverter The output (ie, the inverting storage node B) is connected to the input of the first inverter; and each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor Crystal (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor Crystal (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND) ), A write control signal (WC), an inverted write control signal (/ WC), a standby mode control signal (S), and an inverted standby mode control signal (/ S); wherein the fourth NMOS The source, gate, and drain of the transistor (M21) are connected to the ground voltage, the inverted standby mode control signal (/ S), and the second low-voltage node (VL2); the fifth NMOS transistor ( M22) The source, gate and drain are connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1), respectively; the sixth NMOS transistor (M23) The source is connected to this connector And the gate and the drain are connected together and connected to the first low voltage node (VL1); the source, gate and drain of the seventh NMOS transistor (M24) are connected to the eighth NMOS, respectively. The drain of the transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the source, gate and drain of the eighth NMOS transistor (M25) are connected to The accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to the third inverter Between the output of (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the The input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the The first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are connected to the write control signal (WC), the standby mode control signal (S) and the Ninth NMOS transistor (M26) gate; the source, gate, and drain of the third PMOS transistor (P21) are connected to the inverted write control signal (/ WC), the standby mode control signal (S), and The drain of the tenth NMOS transistor (M27); among them, the source of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the ninth NMOS transistor (M26) The gates are connected together to form a node (C). When the standby mode control signal (S) is a logic low level, the voltage level of the node (C) is the inverted write control signal (/ WC). ), And when the standby mode control signal (S) is a logic high level, the voltage level of the node (C) is the logic level of the write control signal (WC); The read control signal (RC) during the fetch mode is set to the level of the accelerated read voltage (RGND) to prevent leakage current of the seventh NMOS transistor (M24) during non-read mode; in addition, The standby startup circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the sixth NMOS voltage during an initial period of entering the standby mode. Body (M23) of the threshold voltage (V _TM23) voltage level; In addition, each of the word line voltage level converting circuit (5) further comprises: a sixth PMOS transistor (P51), a twelfth NMOS power Crystal (M51), a thirteenth NMOS transistor (M52), the read control signal (RC), the inverted write control signal (/ WC), an inverted read control signal (/ RC), and the A word line control signal (WLC); wherein the source, gate, and drain of the sixth PMOS transistor (P51) are connected to a word line (WL), and the inverted write control signal (/ WC) and the word line control signal (WLC); the source, gate, and drain of the twelfth NMOS transistor (M51) are connected to the word line control signal (WLC), the read Take the control signal (RC) and the word line (WL); and the source, gate and drain of the thirteenth NMOS transistor (M52) are connected to the word line control signal (WLC), the The inversion read control signal (/ RC) and the word line (WL); wherein each word line voltage level conversion circuit (5) selects the word line ( WL) changes from the power supply voltage (V _DD) for the power supply After pressing (V _DD) deduct the twelfth NMOS transistor (M51) of the threshold voltage (V _TM51) (i.e., V _DD -V _TM51) supplied to the word line control signal (the WLC); and a write During operation, the power supply voltage (V _DD ) of the word line (WL) of the selected cell is provided to the word line control signal (WLC); further, each high voltage level control circuit ( 6) It further includes: a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), the read control signal (RC), and a first high power supply voltage (V _DDH1 ), wherein the source, gate, and drain of the seventh PMOS transistor (P61) are connected to the power supply voltage (V _DD ), the read control signal (RC), and the high-voltage node, respectively. (VH), the source, gate and drain of the eighth PMOS transistor (P62) are connected to the first high power supply voltage (V _DDH1 ), the output of the fourth inverter (I63) and The high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the eighth PMOS transistor (P62). The 5t static random access memory with high write speed as described in item 1 of the scope of patent application, wherein each precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P); wherein the source, gate, and drain of the fourth PMOS transistor (P31) are connected to the power supply voltage (V _DD ), the precharge signal (P), and the corresponding bit, respectively. Element line (BL), so that during a precharge period, the corresponding bit line (BL) is precharged to the power supply voltage (V _DD ) by a logic low level of the precharge signal (P). Level. The 5t static random access memory with high write speed as described in item 2 of the scope of patent application, wherein the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS The transistor (M41), a second delay circuit (D2), and the inverting standby mode control signal (/ S) are composed of the source, gate, and drain of the fifth PMOS transistor (P41). Connected to the power supply voltage (VDD), the inverting standby mode control signal (/ S), and the drain of the eleventh NMOS transistor (M41); the source of the eleventh NMOS transistor (M41) The gate, and drain are connected to the first low voltage node (VL1), the output of the second delay circuit (D2), and the drain of the fifth PMOS transistor (P41); the second delay circuit ( The input of D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41). 5t static random access memory with high write speed as described in item 3 of the scope of patent application, wherein each write drive circuit (7) is composed of a ninth PMOS transistor (P71), a tenth PMOS transistor (P72), an eleventh PMOS transistor (P73), a twelfth PMOS transistor (P74), a fourteenth NMOS transistor (M71), a fifteenth NMOS transistor (M72) , A fifth inverter (I73), an input data (Din), and a second high power supply voltage (V _DDH2 ), wherein the source, gate and sink of the ninth PMOS transistor (P71) The poles are connected to the _{drain of} the second high power supply voltage (V _DDH2 ), the input data (Din) and the fourteenth NMOS transistor (M71), and the source of the tenth PMOS transistor (P72). The gate and the drain are respectively connected to the second high power supply voltage (V _DDH2 ), the drain of the fifteenth NMOS transistor (M72) and the drain of the fourteenth NMOS transistor (M71). The source, gate and drain of the eleventh PMOS transistor (P73) are connected to the second high power supply voltage (V _DDH2 ), the drain of the fourteenth NMOS transistor (M71) and the Fifteenth NMOS Transistor (M72) Drain, the twelfth PMOS transistor (P74) of the source, gate and drain lines respectively connected to the second high power supply voltage _(V DDH2), which fifth inverter (I73) and the output The drain of the fifteenth NMOS transistor (M72), and the source, gate, and drain of the fourteenth NMOS transistor (M71) are respectively connected to the ground voltage, the input data (Din), and the first The drain of the nine PMOS transistor (P71), the source, gate, and drain of the fifteenth NMOS transistor (M72) are connected to the ground voltage, the output of the fifth inverter (I73), and The drain of the twelfth PMOS transistor (P74), and the input of the fifth inverter (I73) is for receiving the input data (Din), and the output is connected to the twelfth PMOS transistor (P74) ) And the gate of the fifteenth NMOS transistor (M72), wherein the drain of the eleventh PMOS transistor (P73), the drain of the twelfth PMOS transistor (P74) and the The drain of the fifteenth NMOS transistor (M72) is commonly connected to the corresponding bit line (BL), where the corresponding bit line (BL) is the level of the ground voltage when logic 0 is written , And when logic 1 is written The second highest power supply voltage (V _DDH2 ) level, the second high power supply voltage (V _DDH2 ) voltage level is designed to be higher than the voltage level of the power supply voltage (V _DD ) to accelerate writing Speed of entering logic 1. The 5t static random access memory with high write speed as described in item 4 of the scope of the patent application, wherein the first NMOS transistor (M11) and the first NMOS transistor (M11) in each memory cell (1) The two NMOS transistors (M12) have the same channel width-to-length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width-to-length ratio, and each control circuit The accelerated read voltage (RGND) in (2) is set to be lower than the ground voltage, and the absolute value of the accelerated read voltage (RGND) is set to make the first low voltage node (VL1) during reading The voltage level is lower than the threshold voltage (V _TM11 ) of the first NMOS transistor (M11). The 5t static random access memory with high write speed as described in item 5 of the scope of patent application, wherein the absolute value of the accelerated read voltage (RGND) is set to be smaller than the first NMOS transistor (M11) This threshold voltage (V _TM11 ). The 5t static random access memory with high write speed as described in item 1 of the scope of patent application, wherein the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) But it is lower than the sum of the absolute value | V _TP12 | of the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12), that is, V _DD <V _DDH1 <V _DD + | V _TP12 |. The 5t static random access memory with high write speed as described in item 4 of the scope of patent application, wherein the storage node (A) originally stores logic 0 and writes the initial instantaneous voltage of logic 1 (V _AWI ) satisfies the following equation: V _AWI = V _DDH2 × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12, where V _AWI indicates that the storage node (A) consists of storage logic 0. For the initial transient voltage of the write logic 1, R _M11 , R _M13 and R _M23 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23). ), And V _DDH2 and V _TM12 represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively. The 5t static random access memory with high write speed as described in item 1 of the scope of the patent application, wherein the read operation of each memory cell (1) can be further subdivided into two stages. One of the first stages of the read operation is to set the first low voltage node (VL1) to a voltage lower than the ground voltage to effectively improve the read speed, and in the second stage of one of the read operations By setting the first low voltage node (VL1) back to the ground voltage, in order to reduce unnecessary power consumption, the time interval between the second phase of the read operation and the first phase is equal to the read control The signal (RC) changes from a logic low level to a logic high level. The time until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by the first The falling delay time of the three inverters (INV) and one of the delay times provided by the first delay circuit (D1) are adjusted. The 5t static random access memory with high writing speed as described in the first item of the scope of the patent application, wherein the initial initial voltage (V _AR0I ) when the storage node A reads logic 0 satisfies the following equation: V _AR0I = V _DD × (R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) / (R _M13 + R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) + RGND × (R _M11 + R _M13 ) ∥ R _M26 / (R _M24 + R _M25 + (R _M11 + R _M13 ) ∥R _M26 ) × R _M13 / (R _M11 + R _M13 ) <V _TM12, where V _AR0I indicates when the storage node A reads logic 0 Initial instantaneous voltage, R _M11 , R _M13, R _M24, R _M25 and R _M26 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), On-resistance of the eighth NMOS transistor (M25) and the ninth NMOS transistor (M26), and V _DD , RGND and V _TM12 represent the power supply voltage (V _DD ) and the accelerated read voltage (RGND), respectively. And the threshold voltage of the second NMOS transistor (M12).