TWI676173B - Five-transistor single port static random access memory - Google Patents

Abstract

The present invention provides a 5T port static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), and a plurality of words. Element line voltage level control circuit (5) and a plurality of high voltage level control circuits (6). The memory array is composed of a plurality of rows of memory cell cells and a plurality of rows of memory cell cells. A control circuit (2), a word line voltage level control circuit (5), and a high voltage level control circuit (6) are provided in the cell, so that in the write mode, the plurality of control circuits ( 2) and the combination of the word line voltage level control circuit (5) to prevent writing logic 1 from being difficult, and also effectively improve the writing speed. In the reading mode, the control circuit ( 2). The combination of the word line voltage level control circuit (5) and the plurality of high voltage level control circuits (6) is effective for improving the reading speed and avoiding unnecessary power consumption.

Description

5T port static random access memory

The invention relates to a 5T port static random access memory (SRAM), in particular to an effective improvement of SRAM standby performance, and can effectively improve read speed and write speed, and can effectively reduce Leakage current (leakage current), SRAM that reduces half-selected cell interference during reading and avoids unnecessary power loss.

As shown in Figure 1a, the conventional 6T static random access memory (SRAM) mainly includes a memory array. The memory array is composed of a plurality of memory blocks (MB ₁ , MB ₂ and so on), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. A column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL ₂ etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to one in the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic circuit diagram of a 6T static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors, and the NMOS transistor (M1) ) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is the word line, and BL and BLB It is a bit line and a complementary bit line, respectively. Since this SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) The other driving transistor is turned on. The initial instantaneous voltage (V _AR ) of node A must satisfy the equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) <V _TM2 ( 1)

Among them, V _AR represents the initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply. Voltage and the threshold voltage of the NMOS transistor (M2), which results in the current driving capability ratio (ie, cell ratio) between the driving transistor and the access transistor is generally set between 2.2 and 3.5 (refer to 98 US Patent No. 60760B2 of October 20, 2014, column 2 lines 8-10).

Figure 1b shows the simulation results of the HSPICE transient analysis of the 6T SRAM cell during a write operation. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T SRAM cell with a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T SRAM cell The body cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width-to-length ratio of M2 and M3 (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM cell), there is a problem that it is quite difficult to write logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transmitted from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 And R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) and Equation (2), it can be seen that the initial instantaneous voltage (V _AW ) written is smaller than the NMOS transistor (M2) Threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.

So far, many methods have been proposed to solve the difficulty of writing logic 1 in the static random access memory cell of FIG. 4 above. The first method is to lower the voltage level supplied to the memory cell to Lower than the power supply voltage (V _DD ), so that when writing logic 1 (assuming that node A originally stores logic 0, but now wants to write logic 1), by increasing the on-resistance of the driving transistor NMOS transistor M1 to During the writing operation, the driving transistor NMOS transistor M2 can be turned on to complete the operation of writing logic 1. These methods are, for example, the "Memory System" proposed by Patent Document 1 (April 27, 1999, US 7706203B2). 5. Patent Literature 2 (TW I426514B of February 11, 103) "5T Static Random Access Memory Reducing Power Supply Voltage during Write Operation" and Patent Literature 3 (TW I534802B of May 21, 105 "Semiconductor memory", etc., can effectively solve the problem of writing logic 1, but because these methods need to set up dual power and / or discharge paths, and these methods must be supplied when writing The voltage level to the memory cell is lowered below the power supply It should voltage (V _DD) and was written after the completion of the voltage supplied to the bit memory cell reverts to a quasi power supply voltage (V _DD), and therefore will result in unnecessary power consumption.

The second method is to redesign the channel width-to-length ratio of PMOS transistors P1 and P2 and NMOS transistors M1, M2, and M3. For example, Non-Patent Document 4 (Satyanand Nalam et al., "5T SRAM with asymmetric sizing for improved read stability"", IEEE Journal of Solid-State Circuits. , Vol . 46. No. 10, pp 2431-2442, Oct. 2011.), but because the channel width-to-length ratios of PMOS transistors P1 and P2 are different and NMOS transistor M1 The channel width to length ratio of M2 is not the same, so the static noise margin (SNM) will be reduced.

The third method is to raise the voltage level of the word line (WL) of the access transistor M3 gate of the memory cell to a voltage higher than the power supply voltage (V _DD ) during writing to facilitate writing logic. At 1 (assuming that node A originally stores logic 0, but now wants to write logic 1), it is completed by reducing the on-resistance of the access transistor M3 so that the driving transistor NMOS transistor M2 is turned on at the initial moment of writing. An operation for writing a logic 1 is, for example, "Port static random access memory for increasing a word line voltage level during a write operation" proposed in Patent Document 5 (TW I404065B, August 1, 102), but During writing, the voltage level of the word line (WL) of the access transistor M3 gate to the memory cell is raised to a level higher than the power supply voltage (V _DD ), which results in an increase of half during writing. Selected cell disturbance (half-selected cell disturbance).

The fourth method is to raise the source voltage level of the driving transistor NMOS transistor M1 to higher than the ground voltage during writing, so as to write logic 1 (assuming that node A originally stores logic 0, but now wants to write Logic 1), by increasing the drain voltage level of the driving transistor NMOS transistor M1 so that the driving transistor NMOS transistor M2 is turned on at the initial writing time, and the operation of writing the logic 1 is completed, for example, patent document 6 (TW I566255B of January 11, 106) Proposed "5T Static Random Access Memory", Patent Document 7 (TW I570717B, February 11, 106) and "5T Static Random Access Memory", and Patent Document 8 (November 11, 106 No. TW I605435B) "5T Port Static Random Access Memory" and so on.

The fifth method is to use back gate bias technology to increase the threshold voltage of the driving transistor NMOS transistor M1 and reduce the threshold voltage of the access transistor M3 at the same time to facilitate writing logic. 1 (assuming that node A originally stores logic 0, but now wants to write logic 1), by increasing the drain voltage level of the driving transistor NMOS transistor M1, the driving transistor NMOS can be driven at the initial moment of writing. The crystal M2 is turned on, and the operation of writing the logic 1 is completed. However, this method requires the use of a split well, which increases the complexity of the process and is therefore less used.

The sixth method is to redesign the connection relationship between PMOS transistors P1 and P2 and NMOS transistors M1, M2, and M3. For example, non-patent document 9 (Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process ”, 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and Non-Patent Document 10 (Shyam Akashe et al.,“ High density and low leakage current based 5T SRAM cell using 45nm technology ", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.) and so on.

Although the above-mentioned technologies can effectively solve the problem of writing logic 1, the technologies do not take into account that the read time and write time cannot be caused when the operating voltage of the SRAM below 10nm drops below 0.9V. Satisfy the specification, so there is still room for improvement.

In view of this, the main purpose of the present invention is to propose a 5T port static random access memory, which can effectively solve the SRAM operating voltage below 10 nm by a two-stage word line voltage level control circuit (5). When the voltage drops below 0.9V, the read time and write time cannot meet the specifications (the word line voltage level control circuit (5) is in the first stage of the corresponding word line enabling, and the corresponding word The line control signal (WLC) is set to the first high power supply voltage (V _DDH1 ) which is higher than the power supply voltage (V _DD ) to effectively improve the writing and reading speed, and the second after the first stage In the phase, the corresponding word line control signal (WLC) is pulled back to the power supply voltage (V _DD ) to slow down write / read interference).

The secondary object of the present invention is to provide a 5T port static random access memory, which can further improve the reading speed by the control circuit (2) and the high voltage level control circuit (6).

The present invention provides a 5T port static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), and a plurality of words. Element line voltage level control circuit (5) and a plurality of high voltage level control circuits (6). The memory array is composed of a plurality of rows of memory cell cells and a plurality of rows of memory cell cells. A control circuit (2), a word line voltage level control circuit (5), and a high voltage level control circuit (6) are provided in the cell, so that in the write mode, the plurality of control circuits ( 2) and the combination of the word line voltage level control circuit (5) to prevent writing logic 1 from being difficult, and also effectively improve the writing speed. In the reading mode, the control circuit ( 2). The combination of the word line voltage level control circuit (5) and the plurality of high voltage level control circuits (6) is effective for improving the reading speed and avoiding unnecessary power consumption.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧Word line voltage level control circuit

6‧‧‧High voltage level control circuit

V _DD ‧‧‧ Power supply voltage

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

BL‧‧‧bit line

WLC‧‧‧Word line control signal

WL‧‧‧Character Line

VH‧‧‧High Voltage Node

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

S‧‧‧Standby mode control signal

/ S‧‧‧ Inverted standby mode control signal

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

GND‧‧‧ Ground

/ WC‧‧‧ Inverted write control signal

INV3‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Third PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧Twelfth NMOS transistor

P41‧‧‧Fourth PMOS transistor

C‧‧‧node

D2‧‧‧Second Delay Circuit

P51‧‧‧Fifth PMOS transistor

P52‧‧‧Sixth PMOS transistor

P53‧‧‧The seventh PMOS transistor

M51‧thirteenth NMOS transistor

INV4‧‧‧Fourth Inverter

INV5‧‧‧Fifth Inverter

V _DDH1 ‧‧‧ Highest power supply voltage

V _DDH2 ‧‧‧ the second highest power supply voltage

P61‧‧‧eighth PMOS transistor

P62‧‧‧9th PMOS transistor

INV6‧‧‧Sixth Inverter

WC‧‧‧ write control signal

BLB ₁ ^… BLB _m ‧‧‧ complementary bit line

BLB‧‧‧ Complementary Bit Line

MB ₁ ^… MB _k ‧‧‧Memory block

WL ₁ ^… WL _n ‧‧‧Character line

BL ₁ ^… BL _m ‧‧‧bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

M1 ^… M4‧‧‧NMOS transistor

P1 ^… P2‧‧‧PMOS transistor

Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a schematic circuit diagram of the preferred embodiment of the present invention; FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention during writing in FIG. 5; and FIG. 7 is a diagram of the fifth embodiment. The simplified circuit diagram of the preferred embodiment of the invention during reading; FIG. 8 is a simplified circuit diagram of the preferred embodiment of the invention shown in FIG. 5 during standby.

According to the above main object, the present invention provides a 5T port static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit ( 4). A plurality of word line voltage level control circuits (5) and a plurality of high voltage level control circuits (6). The memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory cell units. Each column of memory cells is provided with a control circuit (2), a word line voltage level control circuit (5), and a high voltage level control circuit (6), and each row of memory cells is provided with a precharge Circuit (3), so that in the write mode, the plurality of control circuits (2) and the word line voltage level control circuit (5) can be used to effectively prevent the difficulty of writing logic 1 while improving The speed of writing logic 1 and writing logic 0, in the reading mode, on the one hand, by the plurality of control circuits (2), the word line voltage level control circuit (5) And the plurality of high voltage level control circuits (6) are used to improve the reading speed and avoid unnecessary power consumption. In the standby mode, the plurality of control circuits (2) can be used to effectively reduce the leakage current. The design of the standby start circuit (4) can effectively promote the 5T port static random access memory to quickly enter the standby mode.

For the convenience of explanation, the 5T 單 static random access memory shown in Figure 5 only uses one memory cell (1), one word line (WL), one bit line (BL), and one control. The circuit (2), a precharge circuit (3), a standby start circuit (4), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6) are described as examples. . The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) The crystal P12 is composed of a second NMOS transistor M12) and a third NMOS transistor (M13), wherein the first inverter and the second inverter are mutually coupled and connected, that is, the first inverter The output of the inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is connected to the input of the first inverter, and the first inverter The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It is worth noting here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel aspect ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also has the same channel width-to-length ratio.

Please refer to FIG. 5 again, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS Transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV3), a first delay Circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal (/ WC), a standby mode control signal (S), and an inverted standby mode control Signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, the inverted standby mode control signal (/ S) and a second low voltage node (VL2); the fifth The source, gate, and drain of the NMOS transistor (M22) are connected to the second low voltage node (VL2), the standby mode control signal (S), and a first low voltage node (VL1); the first The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate, drain and drain are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor (M25) The source, gate, and drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving the Read control letter (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate, and drain of the ninth NMOS transistor (M26) are connected to the ground voltage and the tenth NMOS transistor, respectively. The drain of the crystal (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are connected to the standby mode control signal (S), the The write control signal (WC) and the gate of the ninth NMOS transistor (M26); and the source, gate and drain of the eleventh NMOS transistor (M28) are connected to the inverting standby mode respectively The control signal (/ S), the inverted write control signal (/ WC), and the drain of the tenth NMOS transistor (M27). The inverted standby mode control signal (/ S) is obtained by the standby mode control signal (S) through an inverter, and the inverted write control signal (/ WC) is obtained by the write control signal. (WC) Obtained via another inverter.

It is worth noting here that the drain of the eleventh NMOS transistor (M28), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together. A node (C) is formed. When the write control signal (WC) is at a logic high level, the voltage level of the node (C) is the standby mode control signal (S), and when the write control signal (S) When WC) is a logic low level, the voltage level of the node (C) is the logic level of the inverted standby mode control signal (/ S); because the logic high level of the node (C) is a power supply voltage (V _DD ) _deducts the voltage level of the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28). Therefore, when the 5T port static random access memory is in non-write mode (corresponding to this time) When the inverted write control signal (/ WC) is at a logic high level), the node (C) is the power supply voltage (V _DD ) minus the threshold voltage of the eleventh NMOS transistor (M28) ( V _TM28 ) voltage level, rather than the voltage level of the power supply voltage (V _DD ), so it can have lower power consumption; and then enter the write mode (which corresponds to the write at this time) When the control signal (WC) is at a logic high level), the charge stored in the node (C) can be quickly discharged through the tenth NMOS transistor (M27) to close the node (C) as the gate. The ninth NMOS transistor (M26) can enter the write mode more quickly.

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (i.e., the first low voltage node VL1) of the driving transistor (i.e., the first NMOS transistor M11) that is closer to the bit line (BL) is set to a predetermined voltage (i.e., the first low-voltage node VL1) that is higher than the ground voltage (i.e. The gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (i.e., the second NMOS transistor M12) in the selected unit cell (i.e., the second NMOS transistor M12) The low-voltage node VL2) is set to a ground voltage to prevent the problem of writing logic 1 from being difficult.

In the first stage of the read mode, the source voltage (that is, the first low-voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (BL) in the selected cell is selected. ) Is set to the accelerated reading voltage (RGND) which is lower than the ground voltage, and the accelerated reading voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed, and in the second stage of the reading mode When the source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the selected unit cell is set back to the ground voltage, so as to reduce unnecessary power consumption, in which the read mode The time interval between the second stage and the first stage is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the gate voltage of the eighth NMOS transistor (M25). The time sufficient to turn off the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV3) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltages of the driving transistors in all the memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current. In the hold mode, the driving voltages in the memory cells are set. The source voltage of the crystal is set to ground voltage in order to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The inverted write control signal (/ WC) in Table 1 is the inverted signal of the write control signal (WC), and the write control signal (WC) is a write signal (W) and the The result of the AND gate operation of the word line (WL) signal. At this time, only when the write signal (W) signal and the word line (WL) signal are at a logic high level, the write control signal ( WC) is a logic high level; the read control signal (RC) is the result of the AND operation of a read signal (R) and the word line (WL) signal. It is worth noting that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (M24). Current.

Please refer to Fig. 5. The precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so that during the precharge period, the precharge signal (P ) To pre-charge the bit line (BL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 5 again, the standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fourth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S), and the twelfth NMOS transistor. The drain of (M41); the source, gate and drain of the twelfth NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is Connected to the gate of the twelfth NMOS transistor (M41).

Please refer to FIG. 5 again. The word line voltage level control circuit (5) is composed of a fifth PMOS transistor (P51), a sixth PMOS transistor (P52), and a seventh PMOS transistor (P53). , A thirteenth NMOS transistor (M51), a fourth inverter (INV4), a fifth inverter (INV5), a first high power supply voltage (V _DDH1 ), a word line (WL ) And a word line control signal (WLC). The source, gate and drain of the fifth PMOS transistor (P51) are connected to the first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the sixth PMOS, respectively. The source of the transistor (P52); the source, gate, and drain of the sixth PMOS transistor (P52) are connected to the drain and the fifth inverter of the fifth PMOS transistor (P51), respectively. The output of (INV5) and the word line control signal (WLC); the source, gate, and drain of the seventh PMOS transistor (P53) are connected to the power supply voltage (V _DD ), the fourth The output of the inverter (INV4) and the word line control signal (WLC); the source, gate, and drain of the thirteenth NMOS transistor (M51) are connected to the word line control signal (WLC) ), The output of the fourth inverter (INV4) and the ground voltage; the input of the fourth inverter (INV4) is for receiving the word line (WL), and the fifth inverter (INV4) The input is connected to the output of the fourth inverter (INV4).

The word line voltage level control circuit (5) uses a two-stage operation when it is enabled to effectively solve the problem that the read time and write time cannot meet the specifications when the SRAM operating voltage drops below 0.9 nm to 0.9. In the first stage of enabling the word line (WL), the word line control signal (WLC) is set to the first high power supply voltage (V _DDH1 ) which is higher than the power supply voltage (V _DD ). ) Voltage level to effectively improve writing and reading speed, and in the second phase after the first phase, the word line control signal (WLC) is pulled back to the power supply voltage (V _DD ) To reduce write / read interference; wherein the time interval between the second phase and the first phase of the word line voltage level control circuit (5) is equal to the fourth inversion The time when the output of the inverter (INV4) is sufficient to turn on the fifth PMOS transistor (P51) and the time until the output of the fifth inverter (INV5) is sufficient to turn off the sixth PMOS transistor (P52), which The value can be adjusted by the rising delay time of the fifth inverter (INV5).

Please refer to FIG. 5 again, the high-voltage level control circuit (6) is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), a sixth inverter (INV6), and a _{Composed of the} second highest power supply voltage (V _DDH2 ), wherein the source, gate and drain of the eighth PMOS transistor (P61) are connected to the power supply voltage (V _DD ) and the read control signal respectively (RC) and a high voltage node (VH), the source, gate and drain of the ninth PMOS transistor (P62) are connected to the second high power supply voltage (V _DDH2 ), the sixth _inverter The output of the phase inverter (INV6) and the high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the ninth PMOS circuit. Gate of crystal (P62). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

The working mode of the 5T port static random access memory is described below. The working principle of the preferred embodiment of the present invention shown in FIG. 5 is as follows:

(I) write mode

Before the write operation starts, the write control signal (WC) is at a logic low level, so that the eleventh NMOS transistor (M28) is turned on, and the tenth NMOS transistor (M27) is turned off (OFF) ), Since the inverted standby mode control signal (/ S) is at a logic high level, the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic high level is at the eleventh NMOS The drain of the transistor (M28) will turn on the ninth NMOS transistor (M26) and make the first low voltage node (VL1) a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, so that the tenth NMOS transistor (M27) is turned on and the eleventh NMOS transistor (M28) is drained. The ground voltage (because the standby mode control signal (S) is the ground voltage at this time), the ground voltage makes the ninth NMOS transistor (M26) cut off, and makes the first low voltage node (VL1) equal to the first The gate-source voltage V _{GS (M23) of the} six NMOS transistor (M23) can effectively prevent the problem of writing logic 1 from being difficult. FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during a writing period.

The following describes how the write operation of the preferred embodiment of the present invention shown in FIG. 6 is completed according to the four write states of the 5T SRAM.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first The NMOS transistor (M11) is on. Because the first NMOS transistor (M11) is ON, the word line control signal (WLC) changes from Low (ground voltage) to High when a write operation starts. When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) changes from OFF to OFF Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on. Because the first NMOS transistor (M11) is ON, when the write operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High, and the voltage at the node A will follow the word line The voltage of the control signal (WLC) rises.

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, Because the bit line (BL) is the voltage level of the power supply voltage (V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is at a voltage level that is close to the power supply The initial state of the voltage level of the voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V _AWI ) written at the node A satisfies Equation (3): V _AWI = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 (3)

Among them, V _AWI represents the initial instantaneous voltage of node A, and R _M11 , R _M13, and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13), and the sixth NMOS transistor, respectively. (M23), and V _DD and V _TM12 denote the power supply voltage (V _DD ) and the threshold voltage of the second NMOS transistor (M12) respectively. Since a first low voltage node (VL1) provides a It is equal to the voltage level of the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23), so the voltage level of node A can be easily set to be 5T static random storage than the conventional one in FIG. 4 The voltage level of the node A from the memory cell is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level, and the lower voltage level of the node B will make the first The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value. The higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A. The The higher voltage level of node A passes through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of B will pass through the first inverter (consisting of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A will obtain a higher voltage level, and so on. Then, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of the logic 1 is completed.

The first low voltage node (VL1) originally stores logic 0 in node A, and during the writing of logic 1, has a voltage bit equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23). After the logic 1 is written, it will have a ground voltage level due to the discharge through the ninth NMOS transistor (M26).

It is worth noting here that the present invention uses a two-stage word line voltage level control circuit (5) to effectively solve the SRAM's operating voltage drop below 0.9nm, which can easily cause read time and write. When the time cannot meet the specifications, the word line voltage level control circuit (5) sets the word line control signal (WLC) to be lower than the power supply voltage (V) in the first stage of the word line enabling. _DD ) is still higher than the first high power supply voltage (V _DDH1 ), because the logic 0 was originally stored in node A and the initial writing of logic 1, the third NMOS transistor (M13) works in the saturation region, the saturation region The current is proportional to the square of the gate-source voltage V _{GS (M13) minus the} threshold voltage V _TM13 , so the word line control signal (WLC) is set to be greater than the power supply voltage (V _DD ) is still high during the first stage of the first high power supply voltage (V _DDH1 ), which can effectively accelerate the speed of writing logic 1; in addition, in order to slow down the interference phenomenon on the semi-selected cell during the writing, in During the second phase after the first phase, the word line control signal (WLC) The second phase of the power supply voltage keyed (V _DD) of the voltage level, wherein the word line voltage level control circuit (5) of the first stage of spaced apart time equal to the fourth inverter based The time when the output of the inverter (INV4) is sufficient to turn on the fifth PMOS transistor (P51) and the time until the output of the fifth inverter (INV5) is sufficient to turn off the sixth PMOS transistor (P52), which The value can be adjusted by the rising delay time of the fifth inverter (INV5).

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), since the node A is the voltage level of the power supply voltage (V _DD ), and the bit line (BL) is the voltage level of the power supply voltage (V _DD ), so the third NMOS transistor (M13) will remain in the OFF state; at this time, because the first PMOS transistor (P11) is still It is ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At the threshold voltage, the third NMOS transistor (M13) changes from OFF to ON. At this time, because the bit line (BL) is Low (ground voltage), the node A and the The first low voltage node (VL1) is discharged to complete the logic 0 writing operation until the writing cycle ends.

It is worth noting here that in the present invention, when the node A originally stores logic 1 and at the initial stage of writing logic 0, the third NMOS transistor (M13) operates in a saturation region. At this time, the word line control signal (WLC) The voltage level is higher than the power supply voltage (V _DD ), so it can effectively accelerate the speed of writing logic 0.

(II) read mode

Before the read operation starts, the read control signal (RC) and the write control signal (WC) are at a logic low level, and the inverted standby mode control signal (/ S) and the inverted write control signal (/ WC) are all logic high levels, so that the eleventh NMOS transistor (M28) is turned on and the tenth NMOS transistor (M27) is turned off, so the node C is at a logic high level, and the logic high level should be The node C turns on the ninth NMOS transistor (M26), and makes the first low-voltage node (VL1) a ground voltage. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off, and the eighth NMOS transistor (M25) is turned on.

It is worth noting here that during the pre-charging period before the read operation starts, the pre-charging signal (P) is a logic low level, thereby pre-charging the corresponding bit line (BL) to the power supply. The voltage (V _DD ) level, but because, for example, the operating voltage of process technology below 10 nanometers will drop to below 0.9 volts will cause the reading speed to drop and fail to meet the specifications. Therefore, the present invention proposes a two-stage reading Take control to increase read speed and meet specifications while avoiding unnecessary power loss.

The preferred embodiment of the present invention shown in FIG. 5 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of a read operation, the read The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately The accelerated reading voltage (RGND) whose ground voltage is low, and the accelerated reading voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed.

In the second phase of one of the read operations, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor (M25) is turned off, so the first low voltage node (VL1) will be at a ground voltage through the ninth NMOS transistor (M26) that is turned on, thereby effectively reducing unnecessary power consumption. The time interval between the second phase and the first phase of the read operation is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the eighth NMOS transistor ( The gate voltage of M25) is enough time to turn off the eighth NMOS transistor (M25). Its value can be provided by the falling delay time of the third inverter (INV3) and the first delay circuit (D1). Adjust the delay time. Furthermore, the ninth NMOS transistor (M26) is turned on regardless of whether the first stage or the second stage of the read operation (because the gate of the ninth NMOS transistor (M26) is at a logic high level) ). FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention shown in FIG. 5 during reading.

Next, according to the two read states of the 5T port static random access memory Figure 7 illustrates how the preferred embodiment of the present invention uses the control circuit (2), the word line voltage level control circuit (5), and the high voltage level control circuit (6) to increase the reading speed. Also avoid unnecessary power loss.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON. The node A and the node B are the power supply voltages, respectively. (V _DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, the word line control signal (WLC) is the first high power supply voltage (V _DDH1 ) in the first stage of the word line (WL) enabling, and after the first stage, The second stage is the power supply voltage (V _DD ), and because the node A is the voltage level of the power supply voltage (V _DD ), the third NMOS transistor (M13) is on regardless of whether it is ON In the OFF state, the bit line (BL) can be effectively maintained as the power supply voltage (V _DD ) until the end of the read cycle and the operation of reading the logic 1 can be successfully completed. It is worth noting here that in the first stage of the read operation, the initial instant voltage (V _RVL1I ) of the first low voltage node (VL1) when reading logic 1 must satisfy equation (4): V _RVL1I = RGND × R _M26 / (R _M26 + R _M24 + R _M25 )>-V _TM11 (4) to effectively prevent half-selected cell interference during reading, where V _RVL1I represents the first low voltage node (VL1 ) Read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated read voltage, R _M26 represents the on-resistance of the ninth NMOS transistor (M26), and R _M24 represents the seventh NMOS transistor (M24) R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM11 represents the threshold voltage of the first NMOS transistor (M11); in the second stage of the read operation, the first The voltage (V _RVL1 ) of a low voltage node (VL1) can be expressed by equation (5): V _RVL1 = ground voltage (5). This can effectively reduce unnecessary power consumption.

Furthermore, in order to effectively reduce the half-selected cell interference and effectively reduce the leakage current during reading, the absolute value of the accelerated read voltage (RGND) can be set more conservatively than that of the first NMOS transistor (M11). The threshold voltage (V _TM11 ), that is, | RGND | <V _TM11 (6), where | RGND | and V _TM11 represent the absolute value of the accelerated read voltage and the threshold voltage of the first NMOS transistor (M11), respectively.

(2) Read logic 0 (node A stores logic 0):

Before the read operation occurs, the first NMOS transistor (M11) is ON and the second NMOS transistor (M12) is OFF. The node (A) and the node (B) are respectively The ground voltage and the second high power supply voltage (V _DDH2 ), and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). Because the first NMOS transistor (M11) is ON, when the read operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage deducts the thirteenth NMOS Threshold voltage V _DD -V _{TM51 of} transistor M51). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, The initial instantaneous voltage (V _AR0I ) of this node A must satisfy equation (7): V _AR0I = V _DD × (R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) / (R _M13 + R _M11 + ( R _M24 + R _M25 ) ∥R _M26 ) + RGND × (R _M11 + R _M13 ) ∥R _M26 / (R _M24 + R _M25 + (R _M11 + R _M13 ) ∥R _M26 ) × R _M13 / (R _M11 + R _M13 ) <V _TM12 (7) to avoid turning on the second NMOS transistor (M12), where V _AR0I represents the initial instantaneous voltage when node A reads logic 0, R _M11 , R _M13, R _M24, R _M25 and R _M26 represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25), and the ninth NMOS The on-resistance of the transistor (M26), and V _DD , RGND and V _TM12 represent the _threshold voltage of the power supply voltage (V _DD ), the accelerated read voltage (RGND) and the second NMOS transistor (M12), The accelerated read voltage (RGND) is lower than the ground voltage.

Furthermore, since the node B is the second high power supply voltage (V _DDH2 ) at the initial stage of reading logic 0, the word line control signal (WLC) is the first high power supply voltage (V _DDH1 ) and the first A low voltage node (VL1) is a voltage lower than the ground voltage. Since the first high power supply voltage (V _DDH1 ) and the second high power supply voltage (V _DDH2 ) are set higher than the power supply voltage ( V _DD ). Therefore, by increasing the conduction between the first NMOS transistor (M11) and the third NMOS transistor (M13), the resistance of the read path can be effectively reduced and the read speed can be effectively improved.

It is worth noting here that the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor ( P12) the absolute value of the threshold voltage | the sum of V _TP12 |, that is, V _DD <V _DDH2 <V _DD + | V _TP12 | (8) where | V _TP12 | represents the second PMOS transistor (P12) threshold voltage The absolute value. The first high power supply voltage _(V DDH1) based set higher than the power supply voltage (V _DD) but lower than the power supply voltage (V _DD) and V the third NMOS transistor (M13) of the threshold voltage _TM13 The sum of V _DD <V _DDH1 <V _DD + V _TM13 (9) Of course, in order to simplify the circuit scale, the first high power supply voltage (V _DDH1 ) can be set to be equal to the second high power supply voltage ( V _DDH2 ) equipotential.

(III) Standby mode

First, explain how the standby startup circuit (4) in Figure 5 can prompt the 5T port's static random access memory to quickly enter the standby mode to effectively improve the standby performance of the SRAM: First, before entering the standby mode, the reverse standby mode The control signal (/ S) is logic High. The inverting standby mode control signal (/ S) of the logic High turns off the fourth PMOS transistor (P41) and turns off the twelfth NMOS transistor (M41). ) Is turned on (ON); then, after entering the standby mode, the inverting standby mode control signal (/ S) is logic Low, and the inverting standby mode control signal (/ S) of logic low makes the fourth PMOS transistor (P41) ON, but within the initial period of the standby mode (the initial period is equal to the inversion standby mode control signal (/ S) transition from logic High to logic Low, until the twelfth NMOS transistor The gate voltage of (M41) is enough time to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS The transistor (M41) is still on, so the first low voltage node (VL1) can be quickly charged. The voltage reaches the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), that is, the port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and stops supplying current.

Please refer to FIG. 5. In the standby mode, the standby mode control signal (S) is at a logic high level, and the inverted standby mode control signal (/ S) is at a logic low level, and the logic low level is at the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low-voltage node (VL1) is equal to the voltage level of the second low-voltage node (VL2), and the voltage levels will all be equal to the criticality of the sixth NMOS transistor (M23) The voltage level of the voltage (V _TM23 ). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during the standby period.

Next, how to reduce the leakage current in the standby mode of the present invention is described. Please refer to FIG. 8. FIG. 8 illustrates the respective leakage currents (I ₁ ) generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that because the second low voltage node (VL2 The voltage level of) is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of node A being logic Low is also maintained at the voltage level of V _TM23 ) , And the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 8 to explain the comparison of the static random access memory proposed by the present invention with the 6T SRAM of FIG. 1b in terms of leakage current. The leakage current I _{1 of the} third NMOS transistor (M13), because the voltage level of the node A is maintained at the voltage level of the V _TM23 in the standby mode of the present invention, and it is assumed that the word line (WL) is in the standby mode Is set to ground voltage, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention It is a negative value. In contrast, in the standby mode, the gate-source voltage (V _GS ) of the NMOS transistor (M3) of the prior art in FIG. 1b is equal to 0. According to the gate-induced drain leakage (GIDL) effect Or according to the results of Figures 3 (A) and 3 (B) of Patent No. US6865119 on March 8, 2005, it can be known that for NMOS transistors, the sub-critical current when the gate-source voltage is -0.1 volt is about the gate The source voltage is 1% of the subcritical current at 0 volts, so the current flowing through the invention caused by the GIDL effect is caused by The leakage current I _{1 of} the third NMOS transistor (M13) is much smaller than that of the NMOS transistor (M3) of the prior art in FIG. 1b; further, the drain-source voltage of the third NMOS transistor (M13) of the present invention ( V _DS ) _deducts the voltage level of V _TM23 for the power supply voltage (V _DD ). In contrast, in the standby mode, the drain source voltage of the NMOS transistor (M3) of the traditional random access memory of FIG. (V _DS ) is equal to the power supply voltage (V _DD ). According to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor caused by the DIBL effect flows through the present invention. The leakage current I _{1 of} (M13) is also smaller than the NMOS transistor (M3) of the prior art in FIG. 1b; as a result, the leakage current I ₁ of the third NMOS transistor (M13) flowing through the present invention is much smaller than that of FIG. 1b. Those who are skilled in NMOS transistor (M3).

Then regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 . Therefore, the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) _deducts the voltage level of the V _TM23 . In contrast, in the standby mode, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the prior art in FIG. 1b is equal to the power supply voltage (V _DD ). DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, node A The voltage level of V _TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, in the standby mode, the base source voltage (V _BS ) of the NMOS transistor (M2) of the prior art in FIG. 1b is equal to 0, and the drain of the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and DIBL effect, it can be known that the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first Figure 1b shows the NMOS transistor (M2) of the prior art. It can be known from the above analysis that the 5T static random access memory proposed by the present invention has a lower leakage current than the prior art of FIG. 1b.

(IV) Retension mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as the traditional 5T SRAM cell with a single bit line in Figure 3, I won't go into details here.

[Effect of Invention]

The 5T port static random access memory proposed by the present invention has the following effects: (1) high read / write speed: since logic 0 is written to logic 1, logic 1 is written to logic 0, and read logic During 0 and other operations, the access transistor (ie, the third NMOS transistor M13) works in the saturation region, and the current in the saturation region is reduced by its threshold voltage with its gate-source voltage V _{GS (M13)} after deducting its threshold voltage. The square of the voltage is proportional, so the word line control signal (WLC) is set to be higher than the power supply in the first stage of the word line enabled by the two-stage word line voltage level control circuit (5). The first highest power supply voltage (V _DDH1 ) _whose supply voltage (V _DD ) is still high can effectively speed up the operation of writing logic 1 from logic 0, writing logic 0 from logic 1, and reading logic 0, so it has Efficiency of high read / write speed; (2) High design freedom: Because the present invention pulls down the storage node (A) to a threshold voltage lower than the second NMOS transistor (M12) when the logic 0 is read ( V _TM12 ) has two mechanisms, one is to apply the driving transistor to the selected cell by the high voltage level control circuit (6). The gate of the body (ie, the first NMOS transistor M11) is pulled up to be higher than the power supply voltage (V _DD ), and the other is to pull down the storage node (A) by an accelerated read voltage (RGND) lower than the ground voltage, Therefore, it has the effect of high design freedom; (3) high read speed and avoid unnecessary power consumption: the present invention uses a two-stage read operation, and the first low-voltage node is (VL1) is set to an accelerated read voltage (RGND) which is lower than the ground voltage, and cooperates with the high voltage level control circuit (6) to pull the high voltage node (VH) higher than the power supply voltage (V _DD ) Voltage level, which can effectively improve the reading speed, and in the second stage of the reading operation, the first low voltage node (VL1) is set back to the ground voltage in order to reduce unnecessary power consumption; (4) Quickly enter standby mode: Because the present invention is provided with a standby startup circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the standby efficiency of the SRAM; (5) increase the speed of writing logic 1 and avoid writing Logic 1: Difficult problem: When the present invention is in a write operation, The combination of the plurality of control circuits (2) and the word line voltage level control circuit (5) can effectively prevent the difficulty of writing logic 1 and also increase the speed of writing logic 1; (6) low standby Current: Since the present invention is in a standby mode, the fifth NMOS transistor (M22) can be turned on to make the voltage level of the first low voltage node (VL1) equal to the second low voltage node ( VL2), and make these voltage levels equal to the threshold voltage level of the sixth NMOS transistor (M23), so the invention also has the effect of low standby current; (7) low number of transistors : For a SRAM array with 1024 columns and 1024 rows, the conventional static random access memory array of Figure 1b, Figure 6T requires a total of 1024 × 1024 × 6 = 6,291,456 transistors, and the static random access memory proposed by the present invention Only 1024 × 1024 × 5 + 1024 × 27 + 6 = 5,270,534 transistors are required, which reduces the number of transistors by 16.2%.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.

Claims (10)

A 5T port static random access memory includes: a memory array, the memory array is composed of a plurality of rows of memory cell cells and a plurality of rows of memory cell cells, each row of memory cells and each row of memory The unit cell contains a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory The unit cell is provided with a pre-charge circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) prompts the 5T port's static random access memory to quickly enter the standby mode to effectively improve the 5T unit The standby performance of the port's static random access memory; and a plurality of word line voltage level control circuits (5), each row of memory cells is provided with a word line voltage level control circuit (5) to effectively improve the The read / write speed of the RAM static random access memory; wherein each memory cell (1) further includes: a first inverter, which is composed of a first PMOS transistor (P11) and a The first NMOS transistor (M11) is composed of the first inverter Between the source supply voltage (V _DD ) and a first low voltage node (VL1); a second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12) The second inverter is connected between a high voltage node (VH) and a second low voltage node (VL2); a storage node (A) is formed by the output terminal of the first inverter ; An inverting storage node (B) is formed by the output terminal of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and a bit line (BL ), And the gate is connected to a word line control signal (WLC); wherein the first inverter and the second inverter are connected in an interactive coupling, that is, the output of the first inverter Terminal (that is, the storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (that is, the inverting storage node B) is connected to the first inverter Input terminal; and each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25) A ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV3), A first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal (/ WC), a standby mode control signal (S), and an inverted Phase standby mode control signal (/ S); wherein the source, gate, and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, the inverting standby mode control signal (/ S) and the The second low voltage node (VL2); the source, gate, and drain of the fifth NMOS transistor (M22) are connected to the second low voltage node (VL2), the standby mode control signal (S), and The first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and the drain are connected together and connected to the first low voltage node (VL1) ; The source, gate, and drain of the seventh NMOS transistor (M24) are connected to the drain, the read control signal (RC), and the first low voltage of the eighth NMOS transistor (M25), respectively; Node (VL1); The source, gate, and drain of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the seventh NMOS transistor (M24), respectively. The source; the first delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the third inverter (INV3 The input of) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are Connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low-voltage node (VL1); the source, gate, and drain of the tenth NMOS transistor (M27) are respectively Connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the source, gate and The drain is connected to the gate of the inverting standby mode control signal (/ S), the inverting write control signal (/ WC), and the ninth NMOS transistor (M26); wherein, the eleventh NMOS Drain of transistor (M28), The drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C). When the write control signal (WC) is at a logic high level, The voltage level of the node (C) is the standby mode control signal (S), and when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the inverting standby The logic level of the mode control signal (/ S); as the logic high level of the node (C) is the power supply voltage (V _DD ) _minus the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28) ) Voltage level, so when the 5T port's static random access memory is in non-write mode (the corresponding write control signal (/ WC) is logic high), the node (C ) Is the voltage level of the power supply voltage (V _DD ) _minus the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28), not the voltage level of the power supply voltage (V _DD ) , So it can have a lower power consumption; and when the write mode is subsequently entered (the corresponding write control signal (WC) is a logic high level at this time), because the storage can be quickly The charge at the node (C) is discharged through the tenth NMOS transistor (M27) enough to turn off the ninth NMOS transistor (M26) with the node (C) as the gate, so it can enter the write faster In addition, the standby start circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the sixth NMOS transistor (M23) during an initial period of entering the standby mode. ) Threshold voltage (V _TM23 ); wherein each word line voltage level control circuit (5) further includes: a fifth PMOS transistor (P51), a sixth PMOS transistor (P52) , A seventh PMOS transistor (P53), a thirteenth NMOS transistor (M51), a fourth inverter (INV4), a fifth inverter (INV5), a first high power supply voltage ( V _DDH1 ), a word line (WL), and the word line control signal (WLC); wherein the source, gate, and drain of the fifth PMOS transistor (P51) are connected to the first high voltage, respectively. Power supply voltage (V _DDH1 ), output of the fourth inverter (INV4) and source of the sixth PMOS transistor (P52); source, gate and sink of the sixth PMOS transistor (P52) Polar system Connected to the drain of the fifth PMOS transistor (P51), the output of the fifth inverter (INV5) and the word line control signal (WLC); the source of the seventh PMOS transistor (P53), The gate and the drain are respectively connected to the power supply voltage (V _DD ), the output of the fourth inverter (INV4) and the word line control signal (WLC); the thirteenth NMOS transistor (M51 ) 'S source, gate and drain are connected to the ground voltage, the output of the fourth inverter (INV4) and the word line control signal (WLC); the fourth inverter (INV4) The input is for receiving the word line (WL), and the input of the fifth inverter (INV5) is connected to the output of the fourth inverter (INV4). According to the 5T port static random access memory described in item 1 of the scope of patent application, the voltage level control circuit (5) of each word line can be further subdivided into two stages when enabled, and In the first stage of enabling the word line (WL), the word line control signal (WLC) is set to a voltage higher than the first high power supply voltage (V _DDH1 ) which is higher than the power supply voltage (V _DD ). Level to effectively improve the read / write speed, and in the second stage after the first stage, the word line control signal (WLC) is pulled back to the voltage of the power supply voltage (V _DD ) Level to reduce read / write interference; wherein the time interval between the second phase and the first phase of the word line voltage level control circuit (5) is equal to the fourth inverter The time when the output of (INV4) is enough to turn on the fifth PMOS transistor (P51) and the time until the output of the fifth inverter (INV5) is enough to turn off the sixth PMOS transistor (P52), its value It can be adjusted by the rising delay time of the fifth inverter (INV5). As described in item 2 of the patent application scope, the 5T port static random access memory, wherein each of the precharge circuits (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source, gate, and drain of the third PMOS transistor (P31) are connected to the power supply voltage (V _DD ), the precharge signal (P), and the bit line (BL ), So that during a precharge period, the precharge signal (P) at a logic low level is used to precharge the bit line (BL) to the level of the power supply voltage (V _DD ); The standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the inverted standby mode control signal (/ S ), The source, gate and drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S) and the tenth The drain of the two NMOS transistors (M41); the source, gate and drain of the twelfth NMOS transistor (M41) are connected to the first low voltage node (VL1) and the second delay circuit ( D2) Loss And the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) It is connected to the gate of the twelfth NMOS transistor (M41). The 5T port static random access memory according to item 3 of the patent application scope, further including a plurality of high-voltage level control circuits (6), and each column of memory cells is provided with a high-voltage level control circuit ( 6) In order to increase the reading speed when the logic 0 is read, each high voltage level control circuit (6) further includes: an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), A sixth inverter (INV6) and a second high power supply voltage (V _DDH2 ); wherein the source, gate, and drain of the eighth PMOS transistor (P61) are connected to the power supply voltage, respectively. (V _DD ), the read control signal (RC) and the high voltage node (VH); the source, gate and drain of the ninth PMOS transistor (P62) are connected to the second high power supply respectively. The voltage (V _DDH2 ), the output of the sixth inverter (INV6) and the high voltage node (VH); and the input of the sixth inverter (INV6) is for receiving the read control signal (RC), The output is connected to the gate of the ninth PMOS transistor (P62). As described in item 4 of the scope of patent application, the 5T port static random access memory, wherein the first NMOS transistor (M11) and the second NMOS transistor in each memory cell (1) (M12) has the same channel width-to-length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width-to-length ratio, and each control circuit (2) The accelerated read voltage (RGND) is set to be lower than the ground voltage, and is satisfied that the absolute value of the voltage level of the first low voltage node (VL1) is smaller than the first NMOS transistor (M11) when reading. ) Threshold voltage (V _TM11 ). As described in item 4 of the patent application scope, the 5T port static random access memory, wherein the absolute value of the accelerated read voltage (RGND) is set to be smaller than the threshold voltage of the first NMOS transistor (M11) (V _TM11 ). The 5T port static random access memory described in item 6 of the scope of patent application, wherein the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the The sum of the power supply voltage (V _DD ) and the threshold voltage (V _TM13 ) of the threshold voltage of the third NMOS transistor (M13), that is, V _DD <V _DDH1 <V _DD + V _TM13 and the second high power supply voltage (V _DDH2 ) is set to the sum of the absolute value of the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12) | V _TP12 | That is, V _DD <V _DDH2 <V _DD + | V _TP12 |. As described in item 7 of the scope of patent application, the 5T port static random access memory, wherein the storage node (A) originally stores logic 0, and writes the initial instantaneous voltage (V _AWI ) when writing to logic 1. The following equations are satisfied: V _AWI = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) and V _AWI > V _TM12, where V _AWI indicates that the storage node (A) consists of storage logic 0 and The initial initial voltage of the write logic 1, R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23), respectively. ), And V _DD and V _TM12 represent the threshold voltage of the power supply voltage (V _DD ) and the second NMOS transistor (M12), respectively. As described in item 8 of the patent application scope, the 5T port static random access memory, wherein the read operation of each memory cell (1) can be further subdivided into two stages, and the read operation One of the first stages is to effectively increase the reading speed by setting the first low voltage node (VL1) to a voltage lower than the ground voltage, and in the second stage of the reading operation, The first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power consumption. The time interval between the second phase and the first phase of the read operation is equal to the read control signal (RC). From the logic low level to the logic high level, the time until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be achieved by the third inverter The falling delay time of (INV) is adjusted with a delay time provided by the first delay circuit (D1). According to the 5T port static random access memory described in the first item of the scope of patent application, the initial instantaneous voltage (V _AR0I ) when the storage node A reads logic 0 satisfies the following equation: V _AR0I = V _DD × (R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) / (R _M13 + R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) + RGND × (R _M11 + R _M13 ) ∥R _M26 / ( R _M24 + R _M25 + (R _M11 + R _M13 ) ∥R _M26 ) × R _M13 / (R _M11 + R _M13 ) and V _AR01 <V _TM12 Among them, V _AR01 indicates that the storage node A should read the logic 0. Initial instantaneous voltage, R _M11 , R _M13, R _M24, R _M25 and R _M26 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), On-resistance of the eighth NMOS transistor (M25) and the ninth NMOS transistor (M26), and V _DD , RGND and V _TM12 represent the power supply voltage (V _DD ) and the accelerated read voltage (RGND), respectively. And the threshold voltage of the second NMOS transistor (M12).