TWI605453B - Five transistor single port static random access memory - Google Patents
Five transistor single port static random access memory Download PDFInfo
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本發明係有關於一種5T單埠靜態隨機存取記憶體(Static Random Access Memory，簡稱SRAM)，尤指一種有效提高SRAM待機效能，並能有效提高讀取速度，且能有效降低漏電流(leakage current)、降低讀取時之半選定晶胞干擾以及避免無謂的功率耗損之SRAM。 The invention relates to a 5T static random access memory (SRAM), in particular to an effective improvement of SRAM standby performance, and can effectively improve the reading speed, and can effectively reduce leakage current (leakage Current), SRAM that reduces half-selected cell interference during reading and avoids unnecessary power consumption.
習知之6T靜態隨機存取記憶體(SRAM)如第1a圖所示，其主要包括一記憶體陣列(memory array)，該記憶體陣列係由複數個記憶體區塊(memory block，MB1、MB2等)所組成，每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞；複數條字元線(word line，WL1、WL2等)，每一字元線對應至複數列記憶體晶胞中之一列；以及複數位元線對(bit line pairs，BL1、BLB1...BLm、BLBm等)，每一位元線對係對應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 The 6T conventional static random-access memory (SRAM) as shown on FIG. 1a, which includes a memory array (memory array), the memory array by a plurality of system memory blocks (memory block, MB 1, MB 2 and so on) is composed, for each block of memory is more of rows of memory cells) and a plurality of memory cell rows (a plurality of columns of memory cells ) is composed of a plurality of memory cell columns (a plurality, each A column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL 1 , WL 2 , etc.), each word line corresponding to a plurality of columns of memory One of the unit cells; and a plurality of bit line pairs (BL 1 , BLB 1 ... BL m , BLB m , etc.), each bit line pair corresponding to the plurality of line memory cells One row, and each bit line pair is composed of one bit line (BL 1 ... BL m ) and one complementary bit line (BLB 1 ... BLB m ).
第1b圖所示即是6T靜態隨機存取記憶體(SRAM)晶胞之電路示意圖，其中，PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor)， NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor)，NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor)，WL為字元線(word line)，而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line)，由於該單埠SRAM晶胞需要6個電晶體，且於讀取邏輯0時，為了避免讀取操作初始瞬間(initial instant)另一驅動電晶體導通，節點A之讀取初始瞬間電壓(VAR)必須滿足方程式(1)：VAR=VDD×(RM1)/(RM1+RM3)<VTM2 (1) Figure 1b shows the circuit diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors (P1) and (P2) are called load transistors, and NMOS transistors (M1). And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL and BLB They are a bit line and a complementary bit line, respectively. Since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial Instant) Another drive transistor is turned on. The initial instantaneous voltage (V AR ) of node A must satisfy equation (1): V AR = V DD × (R M1 ) / (R M1 + R M3 ) < V TM2 ( 1)
其中，VAR表示節點A之讀取初始瞬間電壓，RM1與RM3分別表示該NMOS電晶體(M1)與該NMOS電晶體(M3)之導通電阻，而VDD與VTM2分別表示電源供應電壓與該NMOS電晶體(M2)之臨界電壓，此導致驅動電晶體與存取電晶體之間的電流驅動能力比(即單元比率，cell ratio)通常設定在2.2至3.5之間(請參考98年10月20日第US76060B2號專利說明書第2欄第8-10行)。 Wherein, V AR represents the initial instantaneous voltage of the reading of the node A, R M1 and R M3 respectively represent the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3), and V DD and V TM2 respectively represent the power supply The voltage and the threshold voltage of the NMOS transistor (M2), which results in a current drive capability ratio (ie, cell ratio) between the drive transistor and the access transistor is usually set between 2.2 and 3.5 (refer to 98) US Patent No. US76060B2, No. 2, lines 8-10, October 20, 2008).
第1b圖所示6T靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬。 The HSPICE transient analysis simulation results of the 6T SRAM cell in the write operation shown in Figure 1b, as shown in Figure 2, are simulated using TSMC 90 nm CMOS process parameters.
用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T靜態隨機存取記憶體晶胞之電路示意圖，與第1b圖之6T靜態隨機存取記憶體晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線，惟該5T靜態隨機存取記憶體晶胞在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比(亦即保持與 6T SRAM晶胞相同之電晶體通道寬長比)的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶晶胞左側節點A原本儲存邏輯0的情況，由於節點A之電荷僅單獨自位元線(BL)傳送，因此在將節點A中先前寫入的邏輯0蓋寫成邏輯1之寫入初始瞬間電壓(VAW)等於方程式(2)：VAW=VDD×(RM1)/(RM1+RM3) (2)其中，VAW表示節點A之寫入初始瞬間電壓，RM1與RM3分別表示NMOS電晶體(M1)與NMOS電晶體(M3)之導通電阻，比較方程式(1)與方程式(2)可知，寫入初始瞬間電壓(VAW)小於NMOS電晶體(M2)之臨界電壓(VTM2)，因而無法完成寫入邏輯1之操作。第3圖所示之5T靜態隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果，如第4圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬，由該模擬結果可証實，具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line, compared to the 6T SRAM cell of Figure 1b, such a 5T SRAM. The bulk cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. The problem of writing logic 1 is quite difficult in the case of the channel width to length ratio of M2 and M3 (i.e., maintaining the same transistor channel width to length ratio as the 6T SRAM cell). Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. The initial instantaneous voltage (V AW ) is equal to equation (2): V AW = V DD × (R M1 ) / (R M1 + R M3 ) (2) where V AW represents the initial instantaneous voltage of the write of node A, R M1 And R M3 respectively indicate the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) with Equation (2), the initial transient voltage (V AW ) is smaller than the NMOS transistor (M2). The threshold voltage (V TM2 ), and thus the operation of writing logic 1 cannot be completed. The 5T SRAM cell shown in Figure 3, the HSPICE transient analysis simulation result during the write operation, as shown in Figure 4, is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that the 5T SRAM cell with a single bit line has a problem in writing logic 1 that is quite difficult.
至今，有許多解決上述5T靜態隨機存取記憶體晶胞寫入邏輯1困難之方法被提出，第一種方法為寫入時將供應至記憶體晶胞之電壓位準拉低至低於電源供應電壓(VDD)，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由提高驅動電晶體NMOS電晶體M1之導通電阻以於寫入操作期間能使驅動電晶體NMOS電晶體M2導通，而完成寫入邏輯1之操作，該等方法例如專利文獻1(99年4月27日第US 7706203B2號)所提出之「Memory System」、專利文獻2(103年2月11日第TW I426514B號)所提出之「寫入操作時降低電源電壓之5T靜態隨機存取記憶體」及專利文獻3(105年5月21日第TW I534802B號)所提出之「半導 體儲存器」等，其雖可有效解決寫入邏輯1困難之問題，惟由於該等方法需設置雙電源及/或放電路徑，且該等方法寫入時須將供應至記憶體晶胞之電壓位準拉低至低於電源供應電壓(VDD)並於寫入完成後將供應至記憶體晶胞之電壓位準回復為電源供應電壓(VDD)，因此均會造成無謂的功率耗損。 To date, many methods have been proposed to solve the above-mentioned 5T SRAM cell write logic 1 method. The first method is to lower the voltage level supplied to the memory cell lower than the power supply during writing. Supply voltage (V DD ) to facilitate writing to logic 1 (assuming node A originally stores logic 0, but now writes logic 1) by increasing the on-resistance of driving transistor NMOS transistor M1 for write operation The "Memory System" proposed in the patent document 1 (US Pat. 2 (5T static random access memory for reducing the power supply voltage during write operation) and Patent Document 3 (No. TW I534802B, May 21, 105) proposed in 2nd (No. TW I426514B, February 11, 103) The proposed "semiconductor storage", etc., can effectively solve the problem of writing logic 1 difficult, but since these methods need to set dual power and/or discharge paths, and these methods must be supplied to the memory when writing The voltage level of the unit cell is pulled low below the power supply The voltage (V DD ) returns the voltage level supplied to the memory cell to the power supply voltage (V DD ) after the writing is completed, thus causing unnecessary power consumption.
第二種方法為重新設計PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比，例如非專利文獻4(Satyanand Nalam et al.,”5T SRAM with asymmetric sizing for improved read stability”,IEEE Journal of Solid-State Circuits.,Vol.46.No.10,pp 2431-2442,Oct.2011.)，惟由於PMOS電晶體P1和P2的通道寬長比不相同且NMOS電晶體M1和M2的通道寬長比不相同，因此會使靜態雜訊邊際(SNM)降低。 The second method is to redesign the channel width to length ratio of the PMOS transistors P1 and P2 and the NMOS transistors M1, M2, and M3, for example, Non-Patent Document 4 (Satyan and Nalam et al., "5T SRAM with asymmetric sizing for improved read stability IEEE Journal of Solid-State Circuits. , Vol . 46. No. 10, pp 2431-2442, Oct. 2011.), except that the channel width to length ratios of the PMOS transistors P1 and P2 are different and the NMOS transistor M1 is used. The channel width to length ratio is not the same as M2, thus reducing the static noise margin (SNM).
第三種方法為寫入時將供應至記憶體晶胞之存取電晶體M3閘極之字元線(WL)電壓位準拉高至高於電源供應電壓(VDD)，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由降低存取電晶體M3之導通電阻以於寫入初始瞬間能使驅動電晶體NMOS電晶體M2導通，而完成寫入邏輯1之操作，例如專利文獻5(102年8月1日第TW I404065B號)所提出之「寫入操作時提高字元線電壓位準之單埠靜態隨機存取記憶體」，惟由於寫入時將供應至記憶體晶胞之存取電晶體M3閘極之字元線(WL)電壓位準拉高至高於電源供應電壓(VDD)，因此會導致增加寫入時之半選定晶胞干擾(half-selected cell disturbance)。 The third method is to raise the word line (WL) voltage level of the gate of the access transistor M3 supplied to the memory cell to be higher than the power supply voltage (V DD ) during writing to facilitate writing logic. 1 (suppose node A originally stores logic 0, but now wants to write logic 1), by reducing the on-resistance of access transistor M3 to enable the drive transistor NMOS transistor M2 to turn on during the initial write. The operation of writing logic 1 is as described in Patent Document 5 (No. TW I404065B, August 1, 102), "Serial Random Access Memory (Word), which improves the word line voltage level during a write operation, Since the word line (WL) voltage level of the gate of the access transistor M3 supplied to the memory cell is pulled up to be higher than the power supply voltage (V DD ), the half of the write is increased. Half-selected cell disturbance is selected.
第四種方法為寫入時將驅動電晶體NMOS電晶體M1之源極電壓位準拉高至高於接地電壓，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由提高驅動電晶體NMOS電晶體M1之汲極電壓位準，以於寫入初始瞬間能使驅動電晶體NMOS電晶體M2導通，而完成寫入邏輯1之操作，例如專利文獻6(105年6月1日第TW I536382B號)所 提出之「單埠靜態隨機存取記憶體(七)」、專利文獻7(105年4月11日第TW I529712B號)所提出之「單埠靜態隨機存取記憶體(五)」及專利文獻8(105年4月11日第TW I529712B號)所提出之「單埠靜態隨機存取記憶體(六)」等均屬之。 The fourth method is to raise the source voltage level of the driving transistor NMOS transistor M1 to be higher than the ground voltage during writing, so as to write logic 1 (assuming node A originally stores logic 0, but now wants to write Logic 1), by increasing the threshold voltage level of the driving transistor NMOS transistor M1, to enable the driving transistor NMOS transistor M2 to be turned on at the initial writing speed, and completing the operation of writing logic 1, for example, Patent Literature 6 (No. TW I536382B, June 1, 105) "單埠 Static Random Access Memory (7)", "Phase Static Random Access Memory (5)" and Patent Literature proposed in Patent Document 7 (TW 119 I529712B, April 11, 105) 8 (No. TW I529712B, April 11, 105), "單埠 Static Random Access Memory (VI)", etc.
第五種方法為寫入時藉由背閘極偏壓(back gate bias)技術以提高驅動電晶體NMOS電晶體M1之臨界電壓並同時降低存取電晶體M3之臨界電壓，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由提高驅動電晶體NMOS電晶體M1之汲極電壓位準，以於寫入初始瞬間能使驅動電晶體NMOS電晶體M2導通，而完成寫入邏輯1之操作，惟該方法須使用分離井(split well)會增加製程複雜度，因此較少使用。 The fifth method is to increase the threshold voltage of the driving transistor NMOS transistor M1 while reducing the threshold voltage of the access transistor M3 by writing with a back gate bias technique to facilitate writing logic. 1 (suppose node A originally stores logic 0, but now wants to write logic 1), by increasing the threshold voltage level of the driving transistor NMOS transistor M1, so that the initial phase of writing can drive the transistor NMOS Crystal M2 conducts and completes the operation of writing logic 1, but the method requires the use of a split well to increase process complexity and is therefore less useful.
第六種方法為重新設計PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3之間的連接關係，例如非專利文獻9(Chua-Chin Wang et al.,”A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process”,2014 International Symposium on Circuits and Systems,pp 1126-1129,June 2014.)及非專利文獻10(Shyam Akashe et al.,”High density and low leakage current based 5T SRAM cell using 45nm technology”,2011 International Conference on Nanoscience,Engineering and Technology(ICONSET),pp 346-350,Nov.2011.)等均屬之。 The sixth method is to redesign the connection relationship between the PMOS transistors P1 and P2 and the NMOS transistors M1, M2, and M3, for example, Non-Patent Document 9 (Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and Non-Patent Document 10 (Shyam Akashe et al., "High density and low leakage Current based 5T SRAM cell using 45nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.) and the like.
以上所述之該等技術雖可有效解決寫入邏輯1困難之問題，惟該等技術均未考慮到同時藉由字元線電壓位準轉換電路以及高電壓位準控制電路，以於有效降低讀取時之半選定晶胞干擾的同時，亦能有效提高讀取速度，因此仍有改進空間 Although the above-mentioned technologies can effectively solve the problem of writing logic 1 difficult, these technologies do not consider the simultaneous use of the word line voltage level conversion circuit and the high voltage level control circuit to effectively reduce The half-selected cell interference during reading can also effectively improve the reading speed, so there is still room for improvement.
有鑑於此，本發明之主要目的係提出一種5T單埠靜態隨機存取記憶體，其能藉由字元線電壓位準轉換電路以及高電壓位準控制電 路，以於有效降低讀取時之半選定晶胞干擾的同時，亦能有效提高讀取速度。 In view of this, the main object of the present invention is to provide a 5T單埠 static random access memory capable of controlling power by a word line voltage level conversion circuit and a high voltage level. The road is effective for reducing the half-selected cell interference during reading, and can also effectively improve the reading speed.
本發明之次要目的係提出一種5T單埠靜態隨機存取記憶體，其能藉由控制電路以有效提高讀取速度，且能藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損。 A secondary object of the present invention is to provide a 5T 單埠 static random access memory capable of effectively improving the reading speed by the control circuit and capable of improving the reading speed by the two-stage read control. Also avoid unnecessary power consumption.
本發明提出一種5T單埠靜態隨機存取記憶體，其主要包括一記憶體陣列、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個字元線電壓位準轉換電路(5)以及複數個高電壓位準控制電路(6)，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞設置一個控制電路(2)、一個字元線電壓位準轉換電路(5)以及一個高電壓位準控制電路(6)，且每一行記憶體晶胞設置一個預充電電路(3)，藉此於讀取模式時，一方面藉由該複數個控制電路(2)以及該複數個高電壓位準控制電路(6)以於提高讀取速度的同時，亦避免無謂的功率耗損，另一方面藉由該複數個字元線電壓位準轉換電路(5)以有效降低讀取時之半選定晶胞干擾，於寫入模式時，可藉由該複數個控制電路(2)以有效防止寫入邏輯1困難之問題，於待機模式時，可藉由該複數個控制電路(2)以有效降低漏電流，且可藉由該待機啟動電路(4)的設計，以有效促使靜態隨機存取記憶體快速進入待機模式。 The invention provides a 5T單埠 static random access memory, which mainly comprises a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), a plurality of words a line voltage level conversion circuit (5) and a plurality of high voltage level control circuits (6), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory crystals The cell is provided with a control circuit (2), a word line voltage level conversion circuit (5) and a high voltage level control circuit (6), and each row of memory cells is provided with a precharge circuit (3). In the read mode, on the one hand, the plurality of control circuits (2) and the plurality of high voltage level control circuits (6) are used to increase the reading speed while avoiding unnecessary power consumption, and the other The plurality of word line voltage level conversion circuits (5) are used to effectively reduce half-selected cell interference during reading. In the write mode, the plurality of control circuits (2) can be effectively prevented. The problem of writing logic 1 is difficult. In standby mode, this can be done by A plurality of control circuits (2) effective to reduce the leakage current, and may be designed by the standby start circuit (4), in order to effectively promote the fast static random-access memory into standby mode.
1‧‧‧記憶體晶胞 1‧‧‧ memory cell
2‧‧‧控制電路 2‧‧‧Control circuit
3‧‧‧預充電電路 3‧‧‧Precharge circuit
4‧‧‧待機啟動電路 4‧‧‧Standby start circuit
5‧‧‧字元線電壓位準轉換電路 5‧‧‧Word line voltage level conversion circuit
6‧‧‧高電壓位準控制電路 6‧‧‧High voltage level control circuit
P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor
P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor
M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor
M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor
M13‧‧‧第三NMOS電晶體 M13‧‧‧ Third NMOS transistor
A‧‧‧儲存節點 A‧‧‧ storage node
B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node
BL‧‧‧位元線 BL‧‧‧ bit line
WLC‧‧‧字元線控制信號 WLC‧‧‧ word line control signal
VDD‧‧‧電源供應電壓 VDD‧‧‧Power supply voltage
VH‧‧‧高電壓節點 VH‧‧‧ high voltage node
VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node
VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node
S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal
/S‧‧‧反相待機模式控制信號 /S‧‧‧Inverted standby mode control signal
M21‧‧‧第四NMOS電晶體 M21‧‧‧4th NMOS transistor
M22‧‧‧第五NMOS電晶體 M22‧‧‧ Fifth NMOS transistor
M23‧‧‧第六NMOS電晶體 M23‧‧‧ sixth NMOS transistor
M24‧‧‧第七NMOS電晶體 M24‧‧‧ seventh NMOS transistor
M25‧‧‧第八NMOS電晶體 M25‧‧‧8th NMOS transistor
M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor
M27‧‧‧第十NMOS電晶體 M27‧‧‧ tenth NMOS transistor
P21‧‧‧第三PMOS電晶體 P21‧‧‧ Third PMOS transistor
RC‧‧‧讀取控制信號 RC‧‧‧ read control signal
RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage
/RC‧‧‧反相讀取控制信號 /RC‧‧‧Inverted read control signal
/WC‧‧‧反相寫入控制信號 /WC‧‧‧Inverted write control signal
INV‧‧‧第三反相器 INV‧‧‧ third inverter
D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit
P31‧‧‧第四PMOS電晶體 P31‧‧‧4th PMOS transistor
P‧‧‧預充電信號 P‧‧‧Precharge signal
M41‧‧‧第十一NMOS電晶體 M41‧‧11 eleventh NMOS transistor
P41‧‧‧第五PMOS電晶體 P41‧‧‧ Fifth PMOS transistor
C‧‧‧節點 C‧‧‧ node
D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit
WL‧‧‧字元線 WL‧‧‧ character line
VDDH‧‧‧高電源供應電壓 VDDH‧‧‧High power supply voltage
P51‧‧‧第六PMOS電晶體 P51‧‧‧6th PMOS transistor
M51‧‧‧第十二NMOS電晶體 M51‧‧‧12th NMOS transistor
M52‧‧‧第十三NMOS電晶體 M52‧‧‧Thirteenth NMOS transistor
P61‧‧‧第七PMOS電晶體 P61‧‧‧ seventh PMOS transistor
P62‧‧‧第八PMOS電晶體 P62‧‧‧8th PMOS transistor
I63‧‧‧第四反相器 I63‧‧‧fourth inverter
WC‧‧‧寫入控制信號 WC‧‧‧ write control signal
BLB1 …BLBm‧‧‧互補位元線 BLB 1 ... BLB m ‧‧‧complementary bit line
BLB‧‧‧互補位元線 BLB‧‧‧complementary bit line
MB1 …MBk‧‧‧記憶體區塊 MB 1 ... MB k ‧‧‧ memory block
WL1 …WLn‧‧‧字元線 WL 1 ... WL n ‧‧‧ character line
BL1 …BLm‧‧‧位元線 BL 1 ... BL m ‧‧‧ bit line
I1、I2、I3‧‧‧漏電流 I 1 , I 2 , I 3 ‧‧‧ leakage current
M1…M4‧‧‧NMOS電晶體 M1 ... M4‧‧‧ NMOS transistor
P1…P2‧‧‧PMOS電晶體 P1 ... P2‧‧‧ PMOS transistor
第1a圖 係顯示習知之靜態隨機存取記憶體； 第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖；第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖；第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖；第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖；第5圖 係顯示本發明較佳實施例所提出之電路示意圖；第6圖 係顯示第5圖之本發明較佳實施例於寫入期間之簡化電路圖；第7圖 係顯示第5圖之本發明較佳實施例之寫入動作時序圖；第8圖 係顯示第5圖之本發明較佳實施例於讀取期間之簡化電路圖；第9圖 係顯示第5圖之本發明較佳實施例於待機期間之簡化電路圖。 Figure 1a shows a conventional static random access memory; 1b is a schematic circuit diagram showing a conventional 6T static random access memory cell; FIG. 2 is a timing chart showing a write operation of a conventional 6T static random access memory cell; and FIG. 3 is a conventional display Schematic diagram of a 5T static random access memory cell; Fig. 4 shows a write operation timing diagram of a conventional 5T static random access memory cell; Fig. 5 shows a preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; FIG. 7 is a timing chart showing the writing operation of the preferred embodiment of the present invention in FIG. 5; The figure shows a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during reading; and FIG. 9 is a simplified circuit diagram showing the preferred embodiment of the present invention in FIG. 5 during standby.
根據上述之主要目的，本發明提出一種5T單埠靜態隨機存取記憶體，其主要包括一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1)；複數個控制電路(2)，每一列記憶晶胞設置一個控制電路(2)；複數個預充電電路(3)，每一行記憶晶胞設置一個預充電電路(3)；一待機啟動電路(4)，該待機啟動電路(4)係促使SRAM快速進入待機模式，以有效提高SRAM之待機效能；複數個字元線電壓位準轉換電路(5)，每一列記憶體晶胞設置一個字元線電壓位準轉換電路(5)；以及複數個高電壓位準控制電路(6)，每一列記憶體晶胞設置一個高電壓位準控制電路(6)。 According to the above main object, the present invention provides a 5T單埠 static random access memory, which mainly includes a memory array composed of a plurality of column memory cells and a plurality of row memory cells. Each column of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); Charging circuit (3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompts the SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5); and a plurality of high voltage level control circuits (6), each column The memory cell is provided with a high voltage level control circuit (6).
為了便於說明起見，第5圖所示之靜態隨機存取記憶體僅以一個記憶體晶胞(1)、一條字元線(WL)、一條位元線(BL)、一控制電 路(2)、一預充電電路(3)、一待機啟動電路(4)以及一字元線電壓位準轉換電路(5)以及一高電壓位準控制電路(6)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)以及一第三NMOS電晶體(M13)，其中，該第一反相器及該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入，而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。在此值得注意的是，該第一NMOS電晶體(M11)與該第二NMOS電晶體(M12)具有相同之通道寬長比，該第一PMOS電晶體(P11)與該第二PMOS電晶體(P12)亦具有相同之通道寬長比。 For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control power. The circuit (2), a precharge circuit (3), a standby start circuit (4), and a word line voltage level conversion circuit (5) and a high voltage level control circuit (6) are described as an embodiment. . The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) The crystal P12 is formed by a second NMOS transistor M12 and a third NMOS transistor (M13), wherein the first inverter and the second inverter are coupled to each other, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It should be noted here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel width to length ratio, the first PMOS transistor (P11) and the second PMOS transistor. (P12) also has the same channel width to length ratio.
請再參考第5圖，該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一反相寫入控制信號(/WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與一第二低電壓節點(VL2)；該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第二低電壓 節點(VL2)、該待機模式控制信號(S)與一第一低電壓節點(VL1)；該第六NMOS電晶體(M23)之源極係連接至接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)；該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第一低電壓節點(VL1)；該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極；該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與該第八NMOS電晶體(M25)之閘極之間；該第三反相器(INV)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入；該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1)；該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該寫入控制信號(WC)、該待機模式控制信號(S)與該第九NMOS電晶體(M26)之閘極；而該第三PMOS電晶體(P21)之源極、閘極與汲極則分別連接至該反相寫入控制信號(/WC)、該待機模式控制信號(S)與該第九NMOS電晶體(M26)之閘極。在此值得注意的是，該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得，且該反相寫入控制信號(/WC)係由一寫入控制信號(WC)經另一反相器而獲得。 Referring again to FIG. 5, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), and an inverted write control signal (/) WC), a standby mode control signal (S) and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the second low voltage a node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to a ground voltage, and the gate is connected to the drain Connected to the first low voltage node (VL1) together; the source, the gate and the drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), Reading a control signal (RC) and the first low voltage node (VL1); a source, a gate and a drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND), An output of the first delay circuit (D1) and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) and the eighth NMOS Between the gates of the transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); a source, a gate and a drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, a drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); Ten NMOS transistor (M27) The source, the gate and the drain are respectively connected to the write control signal (WC), the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); and the third PMOS The source, the gate and the drain of the crystal (P21) are respectively connected to the inverted write control signal (/WC), the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26) . It should be noted here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/WC) is A write control signal (WC) is obtained via another inverter.
在此值得注意的是，該第三PMOS電晶體(P21)之源極、該第十NMOS電晶體(M27)之汲極及該第九NMOS電晶體(M26)之閘極係連接在一起並形成一節點(C)，當該待機模式控制信號(S)為邏輯低位 準時，該節點(C)之電壓位準係為該反相寫入控制信號(/WC)之邏輯位準，而當該待機模式控制信號(S)為邏輯高位準時，該節點(C)之電壓位準係為該寫入控制信號(WC)之邏輯位準。 It should be noted here that the source of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together. Forming a node (C) when the standby mode control signal (S) is a logic low On time, the voltage level of the node (C) is the logic level of the inverted write control signal (/WC), and when the standby mode control signal (S) is logic high level, the node (C) The voltage level is the logic level of the write control signal (WC).
該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準，於寫入模式時，將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓VGS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓，以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage (ie, the first low voltage node VL1) of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) is set to be a predetermined voltage higher than the ground voltage (ie, The gate-source voltage V GS(M23) of the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (ie, the second NMOS transistor M12) in the selected unit cell (ie, the second The low voltage node VL2) is set to the ground voltage to prevent the difficulty of writing logic 1.
於讀取模式之第一階段時，將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成呈較接地電壓為低之該加速讀取電壓(RGND)，該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度，而於讀取模式之第二階段時，將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓設定回接地電壓，以便減少無謂的功率消耗，其中該讀取模式之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間，其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first stage of the read mode, the source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the cell is selected (ie, the first low voltage node VL1) The acceleration read voltage (RGND) is set to be lower than the ground voltage, and the accelerated read voltage (RGND) is lower than the ground voltage to effectively increase the read speed, and in the second stage of the read mode And setting a source voltage of a driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the selected unit cell to a ground voltage to reduce unnecessary power consumption, wherein the reading mode The time between the second phase and the first phase is equal to the read control signal (RC) is changed from the logic low level to the logic high level, and the gate voltage of the eighth NMOS transistor (M25) is reached. The time until the eighth NMOS transistor (M25) is turned off, the value of which can be adjusted by the delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).
於待機模式時，將所有記憶體晶胞中之驅動電晶體的源極電 壓設定成較接地電壓為高之該預定電壓，以便降低漏電流；而於保持模式時則將記憶晶胞中之驅動電晶體的源極電壓設定成接地電壓，以便維持原來之保持特性，其詳細工作電壓位準如表1所示。 In the standby mode, the source of the driving transistor in all memory cells is electrically The voltage is set to be higher than the ground voltage to reduce the leakage current; and in the hold mode, the source voltage of the driving transistor in the memory cell is set to the ground voltage to maintain the original retention characteristic. The detailed working voltage level is shown in Table 1.
表1中之該寫入控制信號(WC)為一寫入信號(W)與該字元線(WL)信號的及閘(AND gate)運算結果，此時僅於該寫入信號(W)信號與該字元線(WL)信號均為邏輯高位準時，該寫入控制信號(WC)方為邏輯高位準；該讀取控制信號(RC)為一讀取信號(R)與該字元線(WL)信號的及閘運算結果。在此值得注意的是，對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal, and only the write signal (W) When the signal and the word line (WL) signal are both logic high, the write control signal (WC) is a logic high level; the read control signal (RC) is a read signal (R) and the character The result of the gate operation of the line (WL) signal. It is worth noting here that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (M24). Current.
請參考第5圖，該預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成，該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該預充電信號(P) 與該位元線(BL)，以便於預充電期間，藉由邏輯低位準之該預充電信號(P)，以將該位元線(BL)預充電至該電源供應電壓(VDD)之位準。 Referring to FIG. 5, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), and the source and gate of the fourth PMOS transistor (P31). Connected to the power supply voltage (VDD) and the precharge signal (P) respectively And the bit line (BL), in order to precharge the bit line (BL) to the power supply voltage (VDD) by the logic low level precharge signal (P) during precharge quasi.
請再參考第5圖，該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極；該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之汲極；該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 Referring to FIG. 5 again, the standby starting circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. a source, a gate and a drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (VDD), the reverse standby mode control signal (/S), and the eleventh NMOS transistor ( a drain of M41); a source, a gate and a drain of the eleventh NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) a drain of the fifth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and an output of the second delay circuit (D2) is connected To the gate of the eleventh NMOS transistor (M41).
請再參考第5圖，該字元線電壓位準轉換電路(5)係由一第六PMOS電晶體(P51)、一第十二NMOS電晶體(M51)、一第十三NMOS電晶體(M52)、該讀取控制信號(RC)、一反相寫入控制信號(/WC)、一反相讀取控制信號(/RC)以及一字元線控制信號(WLC)所組成。該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該字元線(WL)、該反相寫入控制信號(/WC)與該字元線控制信號(WLC)；該第十二NMOS電晶體(M51)之源極、閘極與汲極係分別連接至該字元線控制信號(WLC)、該讀取控制信號(RC)與該字元線(WL)；而該第十三NMOS電晶體(M52)之源極、閘極與汲極係分別連接至該字元線控制信號(WLC)、該反相讀取控制信號(/RC)與該字元線(WL)。 Referring to FIG. 5 again, the word line voltage level conversion circuit (5) is composed of a sixth PMOS transistor (P51), a twelfth NMOS transistor (M51), and a thirteenth NMOS transistor ( M52), the read control signal (RC), an inverted write control signal (/WC), an inverted read control signal (/RC), and a word line control signal (WLC). a source, a gate and a drain of the sixth PMOS transistor (P51) are respectively connected to the word line (WL), the inverted write control signal (/WC) and the word line control signal (WLC) The source, gate and drain of the twelfth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), the read control signal (RC) and the word line (WL) And the source, gate and drain of the thirteenth NMOS transistor (M52) are respectively connected to the word line control signal (WLC), the inverted read control signal (/RC) and the word Yuan line (WL).
該字元線電壓位準轉換電路(5)之詳細工作電壓位準如表2 所示。 The detailed operating voltage level of the word line voltage level conversion circuit (5) is shown in Table 2. Shown.
請再參考第5圖，該高電壓位準控制電路(6)係由一第七PMOS電晶體(P61)、一第八PMOS電晶體(P62)一第四反相器(I63)、該讀取控制信號(RC)以及一高電源供應電壓(VDDH)所組成，其中該第七PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該讀取控制信號(RC)與一高電壓節點(VH)，該第八PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該高電源供應電壓(VDDH)、該第四反相器(I63)之輸出與該高電壓節點(VH)，而該第四反相器(I63) 之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第八PMOS電晶體(P62)之閘極。在此值得注意的是，該第一反相器係連接在該電源供應電壓(VDD)與該第一低電壓節點(VL1)之間，而該第二反相器則連接在該高電壓節點(VH)與該第二低電壓節點(VL2)之間。 Referring again to FIG. 5, the high voltage level control circuit (6) is composed of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a fourth inverter (I63), and the read. Taking a control signal (RC) and a high power supply voltage (VDDH), wherein a source, a gate and a drain of the seventh PMOS transistor (P61) are respectively connected to the power supply voltage (VDD), Reading a control signal (RC) and a high voltage node (VH), the source, the gate and the drain of the eighth PMOS transistor (P62) are respectively connected to the high power supply voltage (VDDH), the fourth The output of the inverter (I63) is connected to the high voltage node (VH), and the fourth inverter (I63) The input is for receiving the read control signal (RC) and the output is connected to the gate of the eighth PMOS transistor (P62). It is worth noting here that the first inverter is connected between the power supply voltage (VDD) and the first low voltage node (VL1), and the second inverter is connected to the high voltage node. (VH) is between the second low voltage node (VL2).
茲依單埠SRAM之工作模式說明第5圖之本發明較佳實施例的工作原理如下： The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:
(I)寫入模式(write mode) (I) write mode
於寫入操作開始前，該待機模式控制信號(S)為邏輯低位準，使得該第三PMOS電晶體(P21)導通(ON)，並使得該第十NMOS電晶體(M27)截止(OFF)，由於此時該反相寫入控制信號(/WC)為邏輯高位準，於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準，該邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通該第九NMOS電晶體(M26)，並使得該第一低電壓節點(VL1)呈接地電壓。 Before the start of the write operation, the standby mode control signal (S) is at a logic low level, such that the third PMOS transistor (P21) is turned "ON", and the tenth NMOS transistor (M27) is turned off (OFF). Since the inverted write control signal (/WC) is at a logic high level at this time, the drain of the third PMOS transistor (P21) is at a logic high level, and the logic is at a high level of the third PMOS transistor ( The drain of P21) turns on the ninth NMOS transistor (M26) and causes the first low voltage node (VL1) to be at a ground voltage.
而於寫入操作期間內，由於該反相寫入控制信號(/WC)為邏輯低位準，使得該節點C呈邏輯低位準，於是使得該第九NMOS電晶體(M26)截止，並使得該第一低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M26)，藉此得以有效防止寫入邏輯1困難之問題。第6圖所示為第5圖之本發明較佳實施例於寫入期間之簡化電路圖。 During the write operation period, since the inverted write control signal (/WC) is at a logic low level, the node C is at a logic low level, so that the ninth NMOS transistor (M26) is turned off, and the The first low voltage node (VL1) is equal to the gate source voltage V GS (M26 ) of the sixth NMOS transistor (M23 ) , whereby the problem of difficulty in writing the logic 1 is effectively prevented. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.
接下來依單埠SRAM之4種寫入狀態來說明第6圖之本發明較佳實施例如何完成寫入動作。 Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.
(一)節點A原本儲存邏輯0，而現在欲寫入邏輯0： (1) Node A originally stores a logic 0, but now wants to write a logic 0:
在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一 NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON，所以當寫入動作開始時，該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)。當該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為位元線(BL)是接地電壓，所以該節點A會保持原本之接地電壓，直到寫入週期結束。 Before the write operation occurs (the word line control signal WLC is a ground voltage), the first The NMOS transistor (M11) is turned ON. Since the first NMOS transistor (M11) is ON, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD) when the write operation starts. When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned from OFF (OFF) to Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.
(二)節點A原本儲存邏輯0，而現在欲寫入邏輯1： (2) Node A originally stores logic 0, but now wants to write logic 1:
在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON，所以當寫入動作開始時，該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)，該節點A的電壓會跟隨該字元線控制信號(WLC)的電壓而上升。 Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD), the node A The voltage rises following the voltage of the word line control signal (WLC).
當該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該位元線(BL)為該電源供應電壓(VDD)之電壓位準，並且因為該第一NMOS電晶體(M11)仍為ON且該節點B處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態，所以該第一PMOS電晶體(P11)仍為截止(OFF)，而該節點A之寫入初始瞬間電壓(VAWI)滿足方程式(3)：VAWI=VDD×(RM11+RM23)/(RM13+RM11+RM23)>VTM12 (3) When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the bit line (BL) is the voltage level of the power supply voltage (VDD), and because the first NMOS transistor (M11) is still ON and the node B is at a voltage level close to the power supply voltage. The initial state of the voltage level of (VDD), so the first PMOS transistor (P11) is still OFF (OFF), and the initial transient voltage (V AWI ) of the node A satisfies the equation (3): V AWI =VDD × (R M11 + R M23 ) / (R M13 + R M11 + R M23 ) > V TM12 (3)
其中，VAWI表示節點A之寫入初始瞬間電壓，RM11、RM13與RM23分別表 示該第一NMOS電晶體(M11)、該第三NMOS電晶體(M13)與該第六NMOS電晶體(M23)之導通電阻，而VDD與VTM12分別表示該電源供應電壓(VDD)與該第二NMOS電晶體(M12)之臨界電壓，由於於該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓VGS(M23)之電壓位準，因此可輕易地將節點A之電壓位準設定成比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準足以使該第二NMOS電晶體(M12)導通，於是使得節點B放電至一較低電壓位準，該節點B之較低電壓位準會使得該第一NMOS電晶體(M11)之導通電阻(RM11)呈現較高的電阻值，該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準，該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成)，而使得該節點B呈現更低電壓位準，該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成)，而使得該節點A獲得更高電壓位準，依此循環，即可將該節點A充電至該電源供應電壓(VDD)，而完成邏輯1的寫入動作。 Wherein, V AWI represents the initial transient voltage of the node A, and R M11 , R M13 and R M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor, respectively. (M23) the on-resistance, and VDD and VTM12 respectively represent the power supply voltage (V DD ) and the threshold voltage of the second NMOS transistor (M12), since one is provided at the first low voltage node (VL1) It is equal to the voltage level of the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23), so the voltage level of the node A can be easily set to be less than the conventional 5T static random memory of FIG. The voltage level of the node A of the memory cell is much higher. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance (R M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again passed through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level, the node The lower voltage level of B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, and thus cycles The node A can be charged to the power supply voltage (VDD) to complete the logic 1 write operation.
在此值得注意的是，該第一低電壓節點(VL1)於節點A原本儲存邏輯0，而寫入邏輯1之期間，係具有等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M23)的電壓位準，而於寫入邏輯1後，又會因經由該第九NMOS電晶體(M26)放電而具有接地電壓之位準。 It should be noted here that the first low voltage node (VL1) originally stores a logic 0 at the node A, and has a gate-source voltage V equal to the sixth NMOS transistor (M23) during the writing of the logic 1. The voltage level of GS (M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).
(三)節點A原本儲存邏輯1，而現在欲寫入邏輯1： (3) Node A originally stores logic 1, but now wants to write logic 1:
在寫入動作發生前(字元線控制信號WLC為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該字元線控制信號(WLC)由Low(接 地電壓)轉High(該電源供應電壓VDD)，由於該節點A為該電源供應電壓(VDD)之電壓位準，且該位元線(BL)為該電源供應電壓(VDD)之電壓位準，因此會使該第三NMOS電晶體(M13)繼續保持截止(OFF)狀態；此時因為該第一PMOS電晶體(P11)仍為ON，所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準，直到寫入週期結束。 Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD), since the node A is the voltage level of the power supply voltage (V DD ), and the bit line ( BL) is the voltage level of the power supply voltage (VDD), thus keeping the third NMOS transistor (M13) in an OFF state; at this time, since the first PMOS transistor (P11) is still ON Therefore, the voltage of the node A is maintained at the voltage level of the power supply voltage (VDD) until the end of the write cycle.
(四)節點A原本儲存邏輯1，而現在欲寫入邏輯0： (4) Node A originally stores logic 1, but now wants to write logic 0:
在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)，且該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該位元線(BL)是Low(接地電壓)，所以會將該節點A以及該第一低電壓節點(VL1)放電而完成邏輯0的寫入動作，直到寫入週期結束。 Before the write operation occurs (the word line control signal WLC is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage VDD), and the voltage of the word line control signal (WLC) is greater than the critical value of the third NMOS transistor (M13) At the time of voltage, the third NMOS transistor (M13) is turned from off (OFF) to on (ON). At this time, since the bit line (BL) is Low (ground voltage), the node A and the first A low voltage node (VL1) discharges to complete the logic 0 write operation until the end of the write cycle.
第6圖所示之本發明較佳實施例，於寫入操作時之HSPICE暫態分析模擬結果，如第7圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬，由該模擬結果可証實，本發明所提出之5T靜態隨機存取記憶體，能藉由寫入期間提高該第一低電壓節點(VL1)之電壓位準，以有效避免習知具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the 5T static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the writing period, thereby effectively avoiding the 5T static with a single bit line. The presence of random access memory cells in writing logic 1 is quite difficult.
(II)讀取模式(read mode) (II) Read mode (read mode)
於讀取操作開始前，該待機模式控制信號(S)為邏輯低位準，而該反相寫入控制信號(/WC)為邏輯高位準，使得該節點C呈邏輯高位準，邏輯高 位準之該節點C會導通第九NMOS電晶體(M26)，並使得該第一低電壓節點(VL1)呈接地電壓。另一方面，由於該讀取控制信號(RC)為邏輯低位準，使得該第七NMOS電晶體(M24)截止(OFF)，並使得該第八NMOS電晶體(M25)導通(ON)。 Before the start of the read operation, the standby mode control signal (S) is a logic low level, and the inverted write control signal (/WC) is a logic high level, so that the node C is at a logic high level, and the logic height is high. The node C of the level turns on the ninth NMOS transistor (M26), and causes the first low voltage node (VL1) to be grounded. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".
在此值得注意的是，於讀取操作開始前之預充電期間，該預充電信號(P)係為邏輯低位準，藉此以將相對應之位元線(BL)預充電至該電源供應電壓(VDD)之位準，惟由於例如20奈米以下製程技術之操作電壓將降為1伏特以下時將造成讀取速度降低而無法滿足規範之問題，因此，本發明提出二階段的讀取控制以於提高讀取速度並滿足規範的同時，亦避免無謂的功率耗損。 It is worth noting here that during pre-charging before the start of the read operation, the pre-charge signal (P) is at a logic low level, whereby the corresponding bit line (BL) is precharged to the power supply. The voltage (V DD ) level, however, because the operating voltage of, for example, a process technology of 20 nm or less will fall below 1 volt, which will cause the reading speed to decrease and the specification cannot be satisfied. Therefore, the present invention proposes a two-stage reading. Control is taken to increase the reading speed and meet the specifications while avoiding unnecessary power consumption.
第5圖所示之本發明較佳實施例，係藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，於讀取操作之一第一階段，該讀取控制信號(RC)為邏輯高位準，使得該第七NMOS電晶體(M24)導通，由於此時該第八NMOS電晶體(M25)仍導通，於是該第一低電壓節點(VL1)大約呈較接地電壓為低之該加速讀取電壓(RGND)，該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in FIG. 5 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading Taking the control signal (RC) to a logic high level, the seventh NMOS transistor (M24) is turned on, and since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately The accelerated read voltage (RGND) is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively increase the read speed.
而於讀取操作之一第二階段，雖然該讀取控制信號(RC)仍為邏輯高位準，使得該第七NMOS電晶體(M24)仍為導通，惟由於此時該第八NMOS電晶體(M25)截止，於是該第一低電壓節點(VL1)會經由導通的該第九NMOS電晶體(M26)而呈接地電壓，藉此可有效減少無謂的功率消耗。在此值得注意的是，該讀取操作之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並 至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間，其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者，無論於讀取操作之該第一階段抑是該第二階段，該第九NMOS電晶體(M26)均呈導通狀態(由於該第九NMOS電晶體(M26)之閘極為邏輯高位準)。第8圖所示為第5圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor is at this time (M25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and The time until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), the value of which can be decreased by the delay time of the third inverter (INV) The delay time provided by a delay circuit (D1) is adjusted. Furthermore, regardless of the first phase of the read operation or the second phase, the ninth NMOS transistor (M26) is turned on (because the gate of the ninth NMOS transistor (M26) is extremely logic high. ). Figure 8 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during reading.
接下來依單埠SRAM之2種讀取狀態來說明第8圖之本發明較佳實施例如何藉由控制電路(2)以及高電壓位準控制電路(6)以於提高讀取速度的同時，亦避免無謂的功率耗損，另一方面藉由字元線電壓位準轉換電路(5)以有效降低讀取時之半選定晶胞干擾。 Next, how the preferred embodiment of the present invention in FIG. 8 is used to improve the reading speed by the control circuit (2) and the high voltage level control circuit (6) according to the two read states of the SRAM. It also avoids unnecessary power consumption, and on the other hand, the word line voltage level conversion circuit (5) is used to effectively reduce the half-selected cell interference during reading.
(一)讀取邏輯1(節點A儲存邏輯1)： (1) Read logic 1 (node A stores logic 1):
在讀取動作發生前，該第一NMOS電晶體(M11)為截止(OFF)且該第二NMOS電晶體(M12)為導通(ON)，該節點A與該節點B分別為該電源供應電壓(VDD)與接地電壓，而該位元線(BL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間，由於該字元線控制信號(WLC)為該電源供應電壓扣抵該第十三NMOS電晶體(M51)之臨界電壓(即VDD-VTM51)，且由於該節點A為該電源供應電壓(VDD)之電壓位準，因此該第三NMOS電晶體(M13)為截止(OFF)狀態，藉此可有效保持該位元線(BL)為該電源供應電壓直到讀取週期結束而順利完成讀取邏輯1之操作。在此值得注意的是，於讀取操作期間由於該字元線控制信號(WLC)為該電源供應電壓扣抵該第十三NMOS電晶體(M51)之臨界電壓(即VDD-VTM51)，因此可有效降低讀取時之半選定晶胞干擾。此外，於讀取操作之該 第一階段，該第一低電壓節點(VL1)於讀取邏輯1時之讀取初始瞬間電壓(VRVL1I)必須滿足方程式(4)：VRVL1I=RGND×RM26/(RM26+RM24+RM25)>-VTM11 (4)以有效地防止讀取時之半選定晶胞干擾，其中，VRVL1I表示該第一低電壓節點(VL1)於讀取邏輯1時之讀取初始瞬間電壓，RGND表示該加速讀取電壓，RM26表示該第九NMOS電晶體(M26)之導通電阻，RM24表示該第七NMOS電晶體(M24)之導通電阻，RM25表示該第八NMOS電晶體(M25)之導通電阻，而VTM11表示該第一NMOS電晶體(M11)之臨界電壓；於該讀取操作之該第二階段，該第一低電壓節點(VL1)之電壓(VRVL1)可由方程式(5)表示：VRVL1=接地電壓 (5)藉此，可有效地減少無謂的功率消耗。 Before the reading operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), and the node A and the node B are respectively the power supply voltage (VDD) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (VDD) due to the precharge circuit (3). During the reading, the word line control signal (WLC) is the threshold voltage of the thirteenth NMOS transistor (M51) (ie, V DD -V TM51 ) for the power supply voltage, and since the node A is The voltage level of the power supply voltage (VDD) is such that the third NMOS transistor (M13) is in an OFF state, thereby effectively maintaining the bit line (BL) as the power supply voltage until the read cycle Finish and successfully complete the operation of reading logic 1. It is worth noting here that during the read operation, the word line control signal (WLC) is the threshold voltage of the thirteenth NMOS transistor (M51) (ie, VDD-V TM51 ). Therefore, the half-selected cell interference at the time of reading can be effectively reduced. In addition, in the first stage of the read operation, the first initial voltage voltage (V RVL1I ) of the first low voltage node (VL1) when reading logic 1 must satisfy equation (4): V RVL1I = RGND × R M26 /(R M26 +R M24 +R M25 )>-V TM11 (4) to effectively prevent half-selected cell interference during reading, wherein V RVL1I indicates that the first low voltage node (VL1) is read The logic 1 reads the initial instantaneous voltage, RGND represents the accelerated read voltage, R M26 represents the on-resistance of the ninth NMOS transistor (M26), and R M24 represents the on-resistance of the seventh NMOS transistor (M24). R M25 represents the on-resistance of the eighth NMOS transistor (M25), and V TM11 represents the threshold voltage of the first NMOS transistor (M11); in the second phase of the read operation, the first low voltage node The voltage of (VL1) (V RVL1 ) can be expressed by equation (5): V RVL1 = ground voltage (5) Thereby, unnecessary power consumption can be effectively reduced.
再者，為了有效降低讀取時之半選定晶胞干擾與有效降低漏電流，可更保守地將該加速讀取電壓(RGND)之絕對值設定為小於該第一NMOS電晶體(M11)之臨界電壓(VTM11)，亦即｜RGND｜<VTM11 (6)其中，｜RGND｜與VTM11分別表示該加速讀取電壓之絕對值與該第一NMOS電晶體(M11)之臨界電壓。 Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the absolute value of the accelerated read voltage (RGND) can be set more conservatively than the first NMOS transistor (M11). The threshold voltage (V TM11 ), that is, |RGND|<V TM11 (6), where |RGND| and V TM11 respectively represent the absolute value of the accelerated read voltage and the threshold voltage of the first NMOS transistor (M11).
(二)讀取邏輯0(節點A儲存邏輯0)： (2) Read logic 0 (node A stores logic 0):
在讀取動作發生前，該第一NMOS電晶體(M11)為導通(ON)且該第二NMOS電晶體(M12)為截止(OFF)，該節點(A)與該節點(B)分別為接地電壓與該高電源供應電壓(VDDH)，而該位元線(BL)則因該預充 電電路(3)而等於該電源供應電壓(VDD)。因為該第一NMOS電晶體(M11)為ON，所以當讀取動作開始時，該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓扣抵該第十三NMOS電晶體M51之臨界電壓VDD-VTM51)。當該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時該節點A之讀取初始瞬間電壓(VAR0I)必須滿足方程式(7)：VAR0I=VDD×(RM11+(RM24+RM25)∥RM26)/(RM13+RM11+(RM24+RM25)∥RM26)+RGND×(RM11+RM13)∥RM26/(RM24+RM25+(RM11+RM13)∥RM26)×RM13/(RM11+RM13)<VTM12 (7)以避免使該第二NMOS電晶體(M12)導通，其中，VAR0I表示節點A讀取邏輯0時之初始瞬間電壓，RM11、RM13、RM24、RM25與RM26分別表示該第一NMOS電晶體(M11)、該第三NMOS電晶體(M13)、該第七NMOS電晶體(M24)、該第八NMOS電晶體(M25)與該第九NMOS電晶體(M26)之導通電阻，而VDD、RGND與VTM12分別表示該電源供應電壓(VDD)、該加速讀取電壓(RGND)與該第二NMOS電晶體(M12)之臨界電壓。在此值得注意的是，該加速讀取電壓(RGND)係設計成低於接地電壓且該加速讀取電壓之絕對值設計成小於該第一NMOS電晶體(M11)之臨界電壓。再者，本發明於讀取期間之該字元線控制信號(WLC)係設定為該電源供應電壓扣抵該第十三NMOS電晶體(M51)之臨界電壓(VDD-VTM51)，其一方面能有效降低讀取時之半選定晶胞干擾，另一方面可藉由增加該第三NMOS電晶體(M13)之導通電阻(RM13)以更容易滿足方程式(7)。 Before the reading operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), and the node (A) and the node (B) are respectively The ground voltage is the high power supply voltage (VDDH), and the bit line (BL) is equal to the power supply voltage (VDD) due to the precharge circuit (3). Because the first NMOS transistor (M11) is ON, when the reading operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage is applied to the thirteenth NMOS). The threshold voltage VDD-V TM51 of the transistor M51). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. The initial instantaneous voltage (V AR0I ) of this node A must satisfy equation (7): V AR0I = VDD × (R M11 + (R M24 + R M25 ) ∥ R M26 ) / (R M13 + R M11 + (R M24 +R M25 )∥R M26 )+RGND×(R M11 +R M13 )∥R M26 /(R M24 +R M25 +(R M11 +R M13 )∥R M26 )×R M13 /(R M11 +R M13 ) <V TM12 (7) to avoid turning on the second NMOS transistor (M12), wherein V AR0I represents the initial instantaneous voltage when node A reads logic 0, R M11 , R M13 , R M24 , R M25 And the first NMOS transistor (M11), the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25), and the ninth NMOS device are respectively represented by R M26 The on-resistance of the crystal (M26), and VDD, RGND, and VTM12 represent the power supply voltage (VDD), the accelerated read voltage (RGND), and the threshold voltage of the second NMOS transistor (M12), respectively. It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (M11). Furthermore, the word line control signal (WLC) of the present invention during reading is set such that the power supply voltage is biased against the threshold voltage (VDD-V TM51 ) of the thirteenth NMOS transistor (M51). The aspect can effectively reduce the half-selected cell interference at the time of reading, and on the other hand, it is easier to satisfy the equation (7) by increasing the on-resistance (R M13 ) of the third NMOS transistor (M13).
再者，於讀取邏輯0期間，由於節點B為該高電源供應電壓(VDDH)，且該第一低電壓節點(VL1)為較接地電壓為低之電壓，由於該高電源供應電壓(VDDH)係設定為高於該電源供應電壓(VDD)，因此，可藉由增加該第一NMOS電晶體(M11)之導通程度，以有效提高讀取速度。在此值得注意的是，該高電源供應電壓(VDDH)係設定為高於該電源供應電壓(VDD)但低於該高電源供應電壓(VDDH)與該第二PMOS電晶體(P12)臨界電壓之絕對值｜VTP12｜的總和，亦即VDD<VDDH<VDD+｜VTP12｜ (8)其中，｜VTP12｜表示該第二PMOS電晶體(P12)臨界電壓之絕對值。 Moreover, during the read logic 0, since the node B is the high power supply voltage (VDDH), and the first low voltage node (VL1) is a voltage lower than the ground voltage, due to the high power supply voltage (VDDH) The system is set higher than the power supply voltage (VDD), and therefore, the reading speed can be effectively increased by increasing the conduction degree of the first NMOS transistor (M11). It is worth noting here that the high power supply voltage (VDDH) is set higher than the power supply voltage (VDD) but lower than the high power supply voltage (VDDH) and the second PMOS transistor (P12) threshold voltage. The sum of the absolute values |V TP12 |, that is, VDD < VDDH < VDD + | V TP12 | (8) where |V TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12).
(III)待機模式(standby mode) (III) Standby mode
首先，說明第5圖之待機啟動電路(4)如何促使5T單埠靜態隨機存取記憶體快速進入待機模式，以有效提高SRAM之待機效能：首先，於進入待機模式之前，該反相待機模式控制信號(/S)為邏輯High，該邏輯High之反相待機模式控制信號(/S)使得該第四PMOS電晶體(P41)截止(OFF)，並使得該第十二NMOS電晶體(M41)導通(ON)；接著，於進入待機模式後，該反相待機模式控制信號(/S)為邏輯Low，該邏輯Low之反相待機模式控制信號(/S)使得該第四PMOS電晶體(P41)導通(ON)，惟於待機模式之初始期間內(該初始期間係等於該反相待機模式控制信號(/S)由邏輯High轉變為邏輯Low起算，至該第十一NMOS電晶體(M41)之閘極電壓足以關閉該第十一NMOS電晶體(M41)為止之時間，其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整)，該第十一NMOS電晶體(M41)仍導通(ON)，於是可對該第一低電壓節點(VL1)快速充電到達該第六NMOS 電晶體(M23)之臨界電壓(VTM23)的電壓位準，亦即單埠SRAM可快速進入待機模式。在此值得注意的是，於待機模式之初始期間後，該第十一NMOS電晶體(M41)關閉並停止供應電流。 First, how the standby start circuit (4) of FIG. 5 causes the 5T 單埠 static random access memory to quickly enter the standby mode to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the reverse standby mode The control signal (/S) is logic High, and the inverted high standby mode control signal (/S) of the logic High causes the fourth PMOS transistor (P41) to be turned off (OFF), and the twelfth NMOS transistor (M41) Turning on (ON); then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the logic low reverse standby mode control signal (/S) causes the fourth PMOS transistor (P41) is turned ON, but is in the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low, to the eleventh NMOS transistor The gate voltage of (M41) is sufficient to turn off the eleventh NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), the eleventh NMOS The transistor (M41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged. The voltage reaches the voltage level of the threshold voltage (V TM23 ) of the sixth NMOS transistor (M23), that is, the 單埠 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the eleventh NMOS transistor (M41) is turned off and the supply current is stopped.
請參考第5圖，於待機模式時，該待機模式控制信號(S)為邏輯高位準，而該反相待機模式控制信號(/S)為邏輯低位準，該邏輯低位準之該反相待機模式控制信號(/S)可使得該控制電路(2)中之該第四NMOS電晶體(M21)截止(OFF)，而該邏輯高位準之該待機模式控制信號(S)則使得該第五NMOS電晶體(M22)導通(ON)，此時該第五NMOS電晶體(M22)係作為等化器(equalizer)使用，因此可藉由呈導通狀態之該第五NMOS電晶體(M22)，使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準，且該等電壓位準均會等於該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準。第9圖所示為第5圖之本發明較佳實施例於待機期間之簡化電路圖。 Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. The voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the critical value of the sixth NMOS transistor (M23) Voltage level of voltage (V TM23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.
接下來說明本發明於待機模式(standby mode)時如何減少漏電流，請參考第9圖，第9圖描述有本發明實施例處於待機模式時所產生之各漏電流(subthreshold leakage current)I1、I2、I3，其中假設SRAM晶胞中之該第一反相器之輸出(即節點A)為邏輯Low(在此值得注意的是，由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準，因此節點A為邏輯Low之電壓位準亦維持在該VTM23的電壓位準)，而該第二反相器之輸出(即節點B)為邏輯High(電源供應電壓VDD)。請參考第1b圖之先前技藝與第9圖之本發明實施例，來說明本發明所提出之靜態隨機存取記憶體與第1b圖 之6T SRAM於漏電流方面之比較，首先關於流經該第三NMOS電晶體(M13)之漏電流I1，由於本發明於待機模式時節點A之電壓位準係維持在該VTM23的電壓位準，且假設字元線(WL)於待機模式時係設定成接地電壓，而位元線(BL)於待機模式時則設定為該電源供應電壓(VDD)，因此本發明之第三NMOS電晶體(M13)的閘源極電壓(VGS)為負值，反觀於待機模式時第1b圖先前技藝之NMOS電晶體(M3)的閘源極電壓(VGS)等於0，根據閘極引發汲極洩漏(Gate Induced Drain Leakage，簡稱GIDL)效應或2005年3月8日第US6865119號專利案第3(A)及3(B)圖之結果可知，對於NMOS電晶體而言，閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為0伏特時之次臨界電流的1%，因此導因於GIDL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第1b圖先前技藝之NMOS電晶體(M3)者；再者，本發明該第三NMOS電晶體(M13)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準，反觀於待機模式時傳統第1b圖6T靜態隨機存取記憶體之NMOS電晶體(M3)之汲源極電壓(VDS)係等於該電源供應電壓(VDD)，根據汲極引發能障下跌(Drain-Induced Barrier Lowering，簡稱DIBL)效應，由於DIBL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1亦小於第1b圖先前技藝之NMOS電晶體(M3)者；結果，流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第1b圖先前技藝之NMOS電晶體(M3)者。 Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I 1 generated when the embodiment of the present invention is in the standby mode. I 2 , I 3 , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the node A is the logic Low and is maintained at the voltage level of the V TM23 ) And the output of the second inverter (ie, node B) is logic High (power supply voltage VDD). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. Leakage current I 1 of the third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V TM 23 in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (VDD) in the standby mode, so the gate-source voltage (V GS ) of the third NMOS transistor (M13) of the present invention is Negative value, in contrast to the standby mode, the gate-source voltage (V GS ) of the prior art NMOS transistor (M3) of Figure 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or As can be seen from the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, filed on Mar. 8, 2005, the sub-critical current of the gate-source voltage of -0.1 volt is approximately the gate source for the NMOS transistor. The pole voltage is 1% of the subcritical current at 0 volts, and thus is caused by the GIDL effect and flows through the present invention. A third NMOS transistor (M13) of the drain current I 1 is much smaller than the prior art of FIG. 1b of the NMOS transistor (M3) are; Furthermore, the present invention is the third NMOS transistor (M13) of the drain-source voltage (V DS ) deducts the voltage level of the V TM23 for the power supply voltage (VDD), and the source voltage of the NMOS transistor (M3) of the conventional 1b to 6T static random access memory (V3) in the standby mode (V) DS ) is equal to the power supply voltage (VDD), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor (M13) flowing through the present invention due to the DIBL effect The leakage current I 1 is also smaller than that of the prior art NMOS transistor (M3) of FIG. 1b; as a result, the leakage current I 1 flowing through the third NMOS transistor (M13) of the present invention is much smaller than that of the prior art of FIG. Transistor (M3).
接著關於流經該第一PMOS電晶體(P11)之漏電流I2，由於待機模式時該第一PMOS電晶體(P11)之源極係為該電源供應電壓(VDD)，而該第一PMOS電晶體(P11)之汲極係維持在該該VTM23的電壓 位準，因此本發明之該第一PMOS電晶體(P11)之源汲極電壓(VSD)為該電源供應電壓(VDD)扣減該VTM23的電壓位準，反觀於待機模式時第1b圖先前技藝之PMOS電晶體(P1)之源汲極電壓(VSD)係等於該電源供應電壓(VDD)，根據DIBL效應，因此流經本發明之該第一PMOS電晶體(P11)之漏電流I2會小於第1b圖先前技藝之PMOS電晶體(P1)者。 Next, regarding the leakage current I 2 flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (VDD) due to the standby mode, and the first PMOS The drain of the transistor (P11) is maintained at the voltage level of the VTM23 , so the source drain voltage (V SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (VDD). Deducting the voltage level of the VTM23 , in contrast to the standby mode, the source drain voltage (V SD ) of the prior art PMOS transistor (P1) of FIG. 1b is equal to the power supply voltage (VDD), according to the DIBL effect, Therefore, the leakage current I 2 flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of FIG.
最後，關於流經該第二NMOS電晶體(M12)之漏電流I3，由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該VTM23的電壓位準，節點A之電壓位準亦維持在該VTM23的電壓位準，而節點B之電壓位準係等於該電源供應電壓(VDD)且該第二NMOS電晶體(M12)之基底為接地電壓，因此本發明之該第二NMOS電晶體(M12)的基源極電壓(VBS)為負值，且該第二NMOS電晶體(M12)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準，反觀於待機模式時第1b圖先前技藝之NMOS電晶體(M2)的基源極電壓(VBS)等於0，且NMOS電晶體(M2)之汲源極電壓(VDS)等於該電源供應電壓(VDD)，根據本體效應(body effect)及DIBL效應可知，流經本發明之該第二NMOS電晶體(M12)之漏電流I3遠小於第1b圖先前技藝之NMOS電晶體(M2)者。由上述分析可知，本發明所提出之5T靜態隨機存取記憶體與第1b圖先前技藝相較具有較低之漏電流。 Finally, regarding the leakage current I 3 flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the VTM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V TM23 , and the voltage level of the node B is equal to the power supply voltage (VDD) and the base of the second NMOS transistor (M12) is the ground voltage, so the present invention The base-source voltage (V BS ) of the second NMOS transistor (M12) is a negative value, and the 汲 source voltage (V DS ) of the second NMOS transistor (M12) is the power supply voltage (VDD). Deducting the voltage level of the V TM23 , in contrast to the standby mode, the base-source voltage (V BS ) of the prior art NMOS transistor (M2) of FIG. 1b is equal to 0, and the source of the NMOS transistor (M2) The voltage (V DS ) is equal to the power supply voltage (VDD). According to the body effect and the DIBL effect, the leakage current I 3 flowing through the second NMOS transistor (M12) of the present invention is much smaller than that of the first FIG. The NMOS transistor (M2) of the art. It can be seen from the above analysis that the 5T static random access memory proposed by the present invention has a lower leakage current than the prior art of FIG. 1b.
(IV)保持模式(retention mode) (IV) retention mode
保持模式時，由於該第一低電壓節點(VL1)與該第二低電壓節點(VL2)均設定成接地電壓，其工作原理相同於第3圖傳統具單一位元線之5T SRAM 晶胞，於此不再累述。 In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to ground voltage, the working principle is the same as that of the conventional 5T SRAM with a single bit line in FIG. The unit cell is not described here.
本發明所提出之5T單埠靜態隨機存取記憶體，具如下功效：(1)高設計自由度：由於本發明於讀取邏輯0時，將儲存節點(A)下拉至低於第二NMOS電晶體(M12)之臨界電壓(VTM12)共有二個機制，一個為藉由字元線電壓位準轉換電路(5)以將施加至選定晶胞之存取電晶體(即第三NMOS電晶體M13)的字元線電壓下拉至低於電源供應電壓(即VDD-VTM51)，另一個為藉由低於接地電壓之加速讀取電壓(RGND)以下拉儲存節點(A)，因此具備高設計自由度之功效；(2)有效降低讀取時之半選定晶胞干擾：本發明可藉由字元線電壓位準轉換電路(5)，以於讀取操作期間將施加至選定晶胞之存取電晶體(即第三NMOS電晶體M13)的字元線電壓下拉至低於該電源供應電壓(即VDD-VTM51)，其一方面可降低半選定晶胞中之第三NMOS電晶體(M13)的讀取干擾，另一方面可藉由減輕滿足方程式(7)所需之加速讀取電壓(RGND)，以降低半選定晶胞中之第一NMOS電晶體(M11)的讀取干擾，因此具備有效降低讀取時之半選定晶胞干擾之功效；(3)高讀取速度並避免無謂的功率消耗：本發明係採用二階段讀取操作，於讀取操作之第一階段藉由將該第一低電壓節點(VL1)設定成較接地電壓為低之加速讀取電壓(RGND)，並配合高電壓位準控制電路(6)以將該高電壓節點(VH)拉高至高於該電源供應電壓(VDD)之電壓位準，因此可有效提高讀取速度，而於讀取操作之第二階段則藉由將第一低電壓節點(VL1)設定回接地電壓，以便減少無謂的功率消耗；(4)快速進入待機模式：由於本發明設置有待機啟動電路(4)以促使SRAM快速進入待機模式，並藉此以謀求提高靜態隨機存取記憶體之待機效能；(5)避免寫入邏輯1困難之問題：本發明於寫入操作時，可藉由該複數個控制電路(2)以有效防止寫入邏輯1困難之問題；(6)低待機電流：由於本發明於待機模式時，可藉由呈導通狀態之第五 NMOS電晶體(M22)，以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準，並使得該等電壓位準均等於該第六NMOS電晶體(M23)之臨界電壓的位準，因此本發明亦具備低待機電流之功效；(7)低電晶體數：對於具有1024列1024行之SRAM陣列而言，傳統第1b圖6T靜態隨機存取記憶體陣列共需1024×1024×6=6,291,456顆電晶體，而本發明所提出之靜態隨機存取記憶體僅需1024×1024×5+1024×24+6=5,257,462顆電晶體，其減少16.3%之電晶體數。 The 5T單埠 static random access memory proposed by the invention has the following effects: (1) high design freedom: since the present invention reads the logic 0, the storage node (A) is pulled down to be lower than the second NMOS. The threshold voltage (V TM12 ) of the transistor (M12) has two mechanisms, one is by the word line voltage level conversion circuit (5) to be applied to the access cell of the selected cell (ie, the third NMOS) The word line voltage of the crystal M13) is pulled down below the power supply voltage (ie VDD-V TM51 ), and the other is the pull-down storage node (A) by the accelerated read voltage (RGND) below the ground voltage, thus having High design freedom; (2) Effectively reduce half-selected cell interference during reading: The present invention can be applied to selected crystals by a word line voltage level conversion circuit (5) during a read operation The word line voltage of the cell access transistor (ie, the third NMOS transistor M13) is pulled down below the power supply voltage (ie, VDD-V TM51 ), which on the one hand reduces the third NMOS in the half selected cell. Read disturb of the transistor (M13), on the other hand, by reducing the accelerated read voltage (RGND) required to satisfy equation (7) ), to reduce the read interference of the first NMOS transistor (M11) in the semi-selected unit cell, thus having the effect of effectively reducing the half-selected cell interference during reading; (3) high reading speed and avoiding unnecessary Power consumption: The present invention employs a two-stage read operation in which the first low voltage node (VL1) is set to an accelerated read voltage (RGND) that is lower than the ground voltage during the first phase of the read operation, and Cooperating with the high voltage level control circuit (6) to raise the high voltage node (VH) to a voltage level higher than the power supply voltage (V DD ), thereby effectively improving the reading speed, and in the read operation The second stage is to reduce the unnecessary power consumption by setting the first low voltage node (VL1) back to the ground voltage; (4) quickly entering the standby mode: since the present invention is provided with a standby start circuit (4) to prompt the SRAM quickly Entering the standby mode, and thereby seeking to improve the standby performance of the static random access memory; (5) avoiding the problem of writing logic 1: the present invention can be used in the write operation by the plurality of control circuits (2) ) to effectively prevent the difficulty of writing logic 1; (6) Low standby current: since the present invention is in the standby mode, the fifth NMOS transistor (M22) in an on state can be used, so that the voltage level of the first low voltage node (VL1) is equal to the second low voltage. The voltage level of the node (VL2) is such that the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23), so the present invention also has the effect of low standby current; (7) low power Number of crystals: For an SRAM array with 1024 columns and 1024 rows, the conventional 1b 6T static random access memory array requires a total of 1024 × 1024 × 6 = 6,291,456 transistors, and the static random access proposed by the present invention The memory only needs 1024×1024×5+1024×24+6=5,257,462 transistors, which reduces the number of transistors by 16.3%.
雖然本發明特別揭露並描述了所選之較佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本發明的精神與範圍。因此，所有相關技術範疇內之改變都包括在本發明之申請專利範圍內。 While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.
1‧‧‧記憶體晶胞 1‧‧‧ memory cell
2‧‧‧控制電路 2‧‧‧Control circuit
3‧‧‧預充電電路 3‧‧‧Precharge circuit
4‧‧‧待機啟動電路 4‧‧‧Standby start circuit
5‧‧‧字元線電壓位準轉換電路 5‧‧‧Word line voltage level conversion circuit
6‧‧‧高電壓位準控制電路 6‧‧‧High voltage level control circuit
P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor
P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor
M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor
M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor
M13‧‧‧第三NMOS電晶體 M13‧‧‧ Third NMOS transistor
A‧‧‧儲存節點 A‧‧‧ storage node
B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node
BL‧‧‧位元線 BL‧‧‧ bit line
WLC‧‧‧字元線控制信號 WLC‧‧‧ word line control signal
VDD‧‧‧電源供應電壓 VDD‧‧‧Power supply voltage
VH‧‧‧高電壓節點 VH‧‧‧ high voltage node
VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node
VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node
S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal
/S‧‧‧反相待機模式控制信號 /S‧‧‧Inverted standby mode control signal
M21‧‧‧第四NMOS電晶體 M21‧‧‧4th NMOS transistor
M22‧‧‧第五NMOS電晶體 M22‧‧‧ Fifth NMOS transistor
M23‧‧‧第六NMOS電晶體 M23‧‧‧ sixth NMOS transistor
M24‧‧‧第七NMOS電晶體 M24‧‧‧ seventh NMOS transistor
M25‧‧‧第八NMOS電晶體 M25‧‧‧8th NMOS transistor
M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor
M27‧‧‧第十NMOS電晶體 M27‧‧‧ tenth NMOS transistor
P21‧‧‧第三PMOS電晶體 P21‧‧‧ Third PMOS transistor
RC‧‧‧讀取控制信號 RC‧‧‧ read control signal
RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage
/RC‧‧‧反相讀取控制信號 /RC‧‧‧Inverted read control signal
/WC‧‧‧反相寫入控制信號 /WC‧‧‧Inverted write control signal
INV‧‧‧第三反相器 INV‧‧‧ third inverter
D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit
P31‧‧‧第四PMOS電晶體 P31‧‧‧4th PMOS transistor
P‧‧‧預充電信號 P‧‧‧Precharge signal
M41‧‧‧第十一NMOS電晶體 M41‧‧11 eleventh NMOS transistor
P41‧‧‧第五PMOS電晶體 P41‧‧‧ Fifth PMOS transistor
C‧‧‧節點 C‧‧‧ node
D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit
WL‧‧‧字元線 WL‧‧‧ character line
VDDH‧‧‧高電源供應電壓 VDDH‧‧‧High power supply voltage
P51‧‧‧第六PMOS電晶體 P51‧‧‧6th PMOS transistor
M51‧‧‧第十二NMOS電晶體 M51‧‧‧12th NMOS transistor
M52‧‧‧第十三NMOS電晶體 M52‧‧‧Thirteenth NMOS transistor
P61‧‧‧第七PMOS電晶體 P61‧‧‧ seventh PMOS transistor
P62‧‧‧第八PMOS電晶體 P62‧‧‧8th PMOS transistor
I63‧‧‧第四反相器 I63‧‧‧fourth inverter
WC‧‧‧寫入控制信號 WC‧‧‧ write control signal
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| TWI676173B (en) * | 2018-07-18 | 2019-11-01 | 修平學校財團法人修平科技大學 | Five-transistor single port static random access memory |
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