CN101557224A - Output buffer for an electronic device - Google Patents
Output buffer for an electronic device Download PDFInfo
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- CN101557224A CN101557224A CNA2008100911339A CN200810091133A CN101557224A CN 101557224 A CN101557224 A CN 101557224A CN A2008100911339 A CNA2008100911339 A CN A2008100911339A CN 200810091133 A CN200810091133 A CN 200810091133A CN 101557224 A CN101557224 A CN 101557224A
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Abstract
The invention relates to an output buffer for an electronic device, which comprises a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit, wherein the first logic unit and the second logic unit are coupled with an input end to be used for controlling the conducting states of the first logic unit and the second logic unit according to an input signal received by the input end, and used for respectively outputting the grid control signals of the first transistor and the second transistor to control the conducting states of the first transistor and the second transistor; and the control unit is coupled to an output end of the first logic unit and an output end of the second logic unit and between the first transistor and the second transistor to be used for controlling the conduction of the first transistor and the second transistor in different times.
Description
Technical field
The present invention relates to a kind of output buffer that is used for an electronic installation, particularly a kind of output buffer of saving production cost.
Background technology
Output buffer (Output Buffer) is usually used in the various electronic installation, is used for isolation signals input and output, is subjected to load effect to avoid signal input part, and strengthens the ability that promotes load.Please refer to Fig. 1, Fig. 1 is the schematic diagram of an existing output buffer 10.Output buffer 10 includes an input 100, an OR gate 102, an AND gate 104, delay element 106,108, a p type metal oxide semiconductor transistor 110, a n-type metal oxide semiconductor transistor 112 and an output 114.OR gate 102 is used for the grid control signal VN that an input signal SI that input 100 is received and delay element 108 exported and carries out the OR computing, and export operation result to delay element 106, then delay element 106 can postpone the sequential of OR operation result, to produce a grid control signal VP.Similarly, AND gate 104 is used for the grid control signal VP that input signal SI and delay element 106 are exported is carried out the AND computing, and export operation result to delay element 108, then delay element 108 can postpone the sequential of AND operation result, to produce grid control signal VN.The conducting state of grid control signal VP and VN may command p type metal oxide semiconductor transistor 110 and n-type metal oxide semiconductor transistor 112 is to export an output signal SO to load by output 114.
Sequential chart about input signal SI, output signal SO, grid control signal VP and VN please refer to Fig. 2.By time point T2, T3 among Fig. 2, T5, T6 as can be known, output buffer 10 is by OR gate 102 and delay element 106, make p type metal oxide semiconductor transistor 110 in the conducting of time point T2 elder generation, then, make n-type metal oxide semiconductor transistor 112 in time point T 3 conductings by AND gate 104 and delay element 108.In other words, the p type metal oxide semiconductor transistor 110 and the n-type metal oxide semiconductor transistor 112 of output buffer 10 can and be closed in the different time conducting, thereby have realized the function of non-overlapping (Non-overlap) output.Yet, if on circuit, realize OR gate 102, AND gate 104, delay element 106 and 108, need a large amount of transistors just can finish, cause production cost effectively to reduce.
Summary of the invention
Therefore, main purpose of the present invention promptly is to provide a kind of output buffer that is used for an electronic installation, in order to reduce production costs.
The present invention discloses a kind of output buffer that is used for an electronic installation, include one first logical block, include one first end, one second end, be coupled to a power end and one the 3rd end, be used for a input signal according to this first end, control this second end to the conducting state between the 3rd end; One second logical block includes one first end, is coupled to this first end of this first logical block, one second end is coupled to a ground end, and one the 3rd end, be used for this input signal according to this first end, control the 3rd end to the conducting state between this second end; One the first transistor includes the 3rd end that one first end is coupled to this first logical block, and one second end is coupled to a power end, and one the 3rd end, is used for signal according to this first end, controls this second end to the conducting state between the 3rd end; One transistor seconds includes one first end, is coupled to the 3rd end of this second logical block, and one second end is coupled to this ground end, and one the 3rd end, is used for signal according to this first end, controls the 3rd end to the conducting state between this second end; An and control unit, be coupled to the 3rd end of this first logical block, the 3rd end of this second logical block, this first end of this first transistor and this first end of this transistor seconds, be used for controlling the conducting sequential of this first transistor and this transistor seconds.
Description of drawings
Fig. 1 is the schematic diagram of an existing output buffer.
Fig. 2 is the sequential chart of coherent signal of the output buffer of Fig. 1.
Fig. 3 to Fig. 6 is the schematic diagram of the embodiment of the invention one output buffer.
Fig. 7 is the sequential chart of coherent signal of the output buffer of Fig. 6.
The figure elements symbol description
10,30,40,50 output buffers
100,300 inputs
114,312 outputs
102 OR gates
104 AND gates
106,108 delay elements
110,306,502,504,600 p type metal oxide semiconductor transistors
112,308,506,508,602 n-type metal oxide semiconductor transistor
302 first logical blocks
304 second logical blocks
310,400,500 control units
402 resistance
404,406 electric capacity
510 first voltage generators
512 second voltage generators
The SI input signal
The SO output signal
The Vc power end
VP, VN grid control signal
V1 first control signal
V2 second control signal
TP1-TP3, TN1-TN3 end points.
Embodiment
Please refer to Fig. 3, Fig. 3 is the schematic diagram of the embodiment of the invention one output buffer 30.Output buffer 30 includes an input 300, one first logical block 302, one second logical block 304, a p type metal oxide semiconductor transistor 306, a n-type metal oxide semiconductor transistor 308, a control unit 310 and an output 312.Output buffer 30 receives an input signal SI by input 300, after relevant treatment, by output 312 outputs one output signal SO.First logical block 302 is a three-terminal element, one end points TP1 is coupled to input 300, one end points TP2 is coupled to a power end Vc, and an end points TP3 is coupled between the grid and control unit 310 of p type metal oxide semiconductor transistor 306, be used for according to input signal SI, control end points TP2 to the conducting state between the end points TP3, and then export the grid of grid control signal VP to a p type metal oxide semiconductor transistor 306.Second logical block 304 also is a three-terminal element, one end points TN1 is coupled to input 300, one end points TN2 is coupled to a ground end, and an end points TN3 is coupled between the grid and control unit 310 of n-type metal oxide semiconductor transistor 308, be used for according to input signal SI, control end points TN3 to the conducting state between the end points TN2, and then export the grid of a grid control signal VN to n-type metal oxide semiconductor transistor 308.The grid of p type metal oxide semiconductor transistor 306 is coupled to end points TP3, and source electrode is coupled to power end Vc, and drain electrode is coupled to output 312, is used for according to grid control signal VP the conducting state between the drain electrode of Controlling Source best.The grid of n-type metal oxide semiconductor transistor 308 is coupled to end points TN3, and source electrode is held with being coupled to, and drain electrode is coupled to output 312, is used for according to grid control signal VN, controls the conducting state that drains between source electrode.On the other hand, control unit 310 is coupled between end points TP3 and the end points TN3, be used for controlling the conducting sequential of p type metal oxide semiconductor transistor 306 and n-type metal oxide semiconductor transistor 308, it preferably makes the not conducting simultaneously of p type metal oxide semiconductor transistor 306 and n-type metal oxide semiconductor transistor 308, and then the size of the output signal SO that exported of control output end 312.Therefore, output buffer 30 is a non-overlapping output buffer (Non-overlap Output Buffer).
The below running of explanation output buffer 30.In embodiments of the present invention, the current potential of power end Vc is represented high potential, and the current potential of ground end is represented electronegative potential.Preferably, when input signal SI was positioned at high potential, the end points TP2 of first logical block 302 was to not conducting between the end points TP3, and the end points TN3 of second logical block 304 is to conducting between the end points TN2; At this moment, grid control signal VN is that electronegative potential (being the current potential of end points TN3) and grid control signal VP are electronegative potential (being the current potential of end points TP3), therefore n-type metal oxide semiconductor transistor 308 not conductings, and 306 conductings of p type metal oxide semiconductor transistor, output signal SO is positioned at high potential.
Next, SI is converted to electronegative potential by high potential when input signal, and the end points TP2 of first logical block 302 is to conducting between the end points TP3, and the end points TN3 of second logical block 304 is to not conducting between the end points TN2; At this moment, grid control signal VP is converted to high potential by electronegative potential, so the 306 not conductings of p type metal oxide semiconductor transistor; And control unit 310 makes grid control signal VN after delay a period of time, be converted to high potential by electronegative potential than grid control signal VP, so n-type metal oxide semiconductor transistor 308 conductings, and output signal SO is converted to electronegative potential by high potential.Then, SI is converted to high potential by electronegative potential when input signal, and the end points TP2 of first logical block 302 is to not conducting between the end points TP3, and the end points TN3 of second logical block 304 is to conducting between the end points TN2; At this moment, grid control signal VN is converted to electronegative potential by high potential, so n-type metal oxide semiconductor transistor 308 not conductings; And control unit 310 makes grid control signal VP after delay a period of time, be converted to electronegative potential by high potential than grid control signal VN, so 306 conductings of p type metal oxide semiconductor transistor, and output signal SO is converted to high potential by electronegative potential.
Therefore, the present invention is p type metal oxide semiconductor transistor 306 and the not conducting simultaneously of n-type metal oxide semiconductor transistor 308 that is coupled to output 312 by control unit 310 controls, to reach the function of non-overlapping output.It should be noted that existing output buffer 10 needs a large amount of transistors could realize, and the control unit 310 of the embodiment of the invention can be by different implementations with the saving element, and then the production cost of saving output buffer 30.For instance, please refer to Fig. 4.Fig. 4 is the schematic diagram of the embodiment of the invention one output buffer 40.Output buffer 40 is similar to output buffer 30, and difference is that control unit 310 is replaced into control unit 400.Control unit 400 includes resistance 402 and electric capacity 404,406.Resistance 402 is coupled between end points TP3 and the end points TN3; Electric capacity 404 is coupled between end points TP3 and the ground end; Electric capacity 406 is coupled between end points TN3 and the ground end.Output buffer 40 utilizes the effect that discharges and recharges of resistance 402 and electric capacity 404,406, and generation time postpones, and makes grid control signal VP and grid control signal VN not change current potential at one time.Thus, the not conducting simultaneously of p type metal oxide semiconductor transistor 306 and n-type metal oxide semiconductor transistor 308 is to reach the function of non-overlapping output.
On the other hand, please refer to Fig. 5.Fig. 5 is the schematic diagram of the embodiment of the invention one output buffer 50.Output buffer 50 is similar to output buffer 30, and difference is that control unit 310 is replaced into control unit 500.Control unit 500 includes p type metal oxide semiconductor transistor 502,504 and n-type metal oxide semiconductor transistor 506,508.P type metal oxide semiconductor transistor 502 is connected with 504, the source electrode of p type metal oxide semiconductor transistor 502 is coupled to end points TP3, the drain electrode of p type metal oxide semiconductor transistor 504 is coupled to end points TN3, and the grid of p type metal oxide semiconductor transistor 504 is coupled to one first voltage generator 510.Similarly, n-type metal oxide semiconductor transistor 506 is connected with 508, the drain electrode of n-type metal oxide semiconductor transistor 506 is coupled to end points TP3, the source electrode of n-type metal oxide semiconductor transistor 508 is coupled to end points TN3, and the grid of n-type metal oxide semiconductor transistor 506 is coupled to one second voltage generator 512.In addition, the grid of p type metal oxide semiconductor transistor 502 is coupled to the source electrode of n-type metal oxide semiconductor transistor 506, and the grid of n-type metal oxide semiconductor transistor 508 is coupled to the source electrode of p type metal oxide semiconductor transistor 504.
It should be noted that, the one first control signal V1 that first voltage generator 510 is produced is used to control the conducting state of p type metal oxide semiconductor transistor 504, and the one second control signal V2 that second voltage generator 512 is produced is used to control the conducting state of n-type metal oxide semiconductor transistor 506.The first control signal V1 and the second control signal V2 are positioned at two different voltage levels, and it can have different designs as required.For instance, if the first control signal V1 is positioned at electronegative potential and the second control signal V2 is positioned at high potential, then p type metal oxide semiconductor transistor 504 and n-type metal oxide semiconductor transistor 506 permanent conductings, its connected mode is as shown in Figure 6; At this moment, output buffer 30 is general output buffer.On the contrary, if the first control signal V1 is positioned at high potential and the second control signal V2 is positioned at electronegative potential, then p type metal oxide semiconductor transistor 504 and n-type metal oxide semiconductor transistor 506 perseverances are closed; At this moment, output buffer 50 is ternary (Tri-state) output buffer, can produce high impedance output.
In Fig. 6, first logical block 302 is realized by a p type metal oxide semiconductor transistor 600, and second logical block 304 is realized by a n-type metal oxide semiconductor transistor 602.Further specify the function mode of output buffer 50 among Fig. 6.Please refer to Fig. 7, Fig. 7 is the sequential chart of input signal SI, output signal SO, grid control signal VP and the VN of the output buffer 50 of Fig. 6, and details are as follows in the action of each signal when current potential is changed.In time, input signal SI is positioned at a high potential at the T1 of Fig. 7, and this moment, p type metal oxide semiconductor transistor 600 was closed, n-type metal oxide semiconductor transistor 602 conductings, and grid control signal VN and VP are all electronegative potential.Then, input signal SI is converted to electronegative potential by high potential at T2 in the time, and this moment, n-type metal oxide semiconductor transistor 602 was closed, and 600 conductings of p type metal oxide semiconductor transistor make grid control signal VP be converted to high potential by electronegative potential earlier.On the other hand, control unit 500 control grid control signal VN make the time point of its current potential conversion delay than the time point of the current potential conversion of grid control signal VP.Therefore, p type metal oxide semiconductor transistor 306 is closed at time point TA, and n-type metal oxide semiconductor transistor 308 is in time point TB conducting, and output signal SO begins to be converted to electronegative potential at time point TB.
Then, in the time, input signal SI is an electronegative potential at T3, p type metal oxide semiconductor transistor 600 conductings and n-type metal oxide semiconductor transistor 602 is closed this moment, and grid control signal VN and VP are all high potential.Then, input signal SI is converted to high potential by electronegative potential at T4 in the time, n-type metal oxide semiconductor transistor 602 conductings this moment, and p type metal oxide semiconductor transistor 600 is closed, and makes grid control signal VN be converted to electronegative potential by high potential earlier.On the other hand, control unit 500 control grid control signal VP make the time point of its current potential conversion delay than the time point of the current potential conversion of grid control signal VN.Therefore, n-type metal oxide semiconductor transistor 308 is closed at time point TC, and p type metal oxide semiconductor transistor 306 is in time point TD conducting, and output signal SO begins to be converted to high potential at time point TD.
In sum, the present invention is by different control units, and control is coupled to the p type metal oxide semiconductor transistor and the not conducting simultaneously of n-type metal oxide semiconductor transistor of output, to reach the function of non-overlapping output.Further, control unit can be realized by the circuit element of simplifying most, therefore reduces the production cost of output buffer.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. output buffer that is used for an electronic installation includes:
First logical block includes one first end, and one second end is coupled to a power end, and one the 3rd end, is used for a input signal according to this first end, controls this second end to the conducting state between the 3rd end;
Second logical block includes one first end, is coupled to this first end of this first logical block, and one second end is coupled to a ground end and one the 3rd end, is used for this input signal according to this first end, controls the 3rd end to the conducting state between this second end;
The first transistor includes one first end, is coupled to the 3rd end of this first logical block, and one second end is coupled to a power end and one the 3rd end, is used for signal according to this first end, controls this second end to the conducting state between the 3rd end;
Transistor seconds includes one first end, is coupled to the 3rd end of this second logical block, and one second end is coupled to this ground end and one the 3rd end, is used for signal according to this first end, controls the 3rd end to the conducting state between this second end; And
Control unit, be coupled to the 3rd end of this first logical block, the 3rd end of this second logical block, this first end of this first transistor and this first end of this transistor seconds, be used for controlling the conducting sequential of this first transistor and this transistor seconds.
2. output buffer as claimed in claim 1, it comprises an input in addition, is coupled to this first end of this first logical block and this first end of this second logical block, is used for producing this input signal.
3. output buffer as claimed in claim 1, it comprises an output in addition, is coupled to the 3rd end of this first transistor and the 3rd end of this transistor seconds, is used for producing an output signal.
4. output buffer as claimed in claim 1, wherein, this first logical block is a p type metal oxide semiconductor transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
5. output buffer as claimed in claim 1, wherein, this second logical block is a n-type metal oxide semiconductor transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
6. output buffer as claimed in claim 1, wherein, this first transistor is a p type metal oxide semiconductor transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
7. output buffer as claimed in claim 1, wherein, this transistor seconds is a n-type metal oxide semiconductor transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
8. output buffer as claimed in claim 1, wherein, this control unit is used to control this first transistor and the not conducting simultaneously of this transistor seconds.
9. output buffer as claimed in claim 1, wherein, this control unit includes:
Resistance includes one first end, is coupled to the 3rd end of this first logical block, and one second end, is coupled to the 3rd end of this second logical block;
First electric capacity, one end are coupled to the 3rd end of this first logical block and this first end of this resistance, and the other end is coupled to this ground end; And
Second electric capacity, one end are coupled to the 3rd end of this second logical block and this second end of this resistance, and the other end is coupled to this ground end.
10. output buffer as claimed in claim 1, wherein, this control unit includes;
The one p type metal oxide semiconductor transistor includes source electrode, is coupled to the 3rd end, drain electrode and the grid of this first logical block;
The 2nd p type metal oxide semiconductor transistor, include source electrode, be coupled to transistorized this drain electrode of a p type metal oxide semiconductor, drain electrode is coupled to the 3rd end and the grid of this second logical block, be used for according to one first control signal, control the conducting state of transistorized this source electrode of the 2nd p type metal oxide semiconductor to this drain electrode;
First n-type metal oxide semiconductor transistor, include source electrode, drain electrode is coupled to the 3rd end and the grid of this first logical block, be used for according to one second control signal, control the conducting state of this drain electrode of this first n-type metal oxide semiconductor transistor to this source electrode; And
Second n-type metal oxide semiconductor transistor, include source electrode, be coupled to the 3rd end, the drain electrode of this second logical block, be coupled to this first n-type metal oxide semiconductor transistor this source electrode, with grid be coupled to transistorized this drain electrode of a p type metal oxide semiconductor.
11. output buffer as claimed in claim 10, wherein, this first control signal is produced by a voltage generator.
12. output buffer as claimed in claim 10, wherein, this second control signal is produced by a voltage generator.
13. output buffer as claimed in claim 10, wherein, this first control signal and this second control signal are to be positioned at two different voltage levels.
14. output buffer as claimed in claim 13, wherein, when this first control signal is positioned at a high-voltage level and this second control signal and is positioned at a low voltage level, this output buffer output high impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100911339A CN101557224B (en) | 2008-04-07 | 2008-04-07 | Output buffer for an electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100911339A CN101557224B (en) | 2008-04-07 | 2008-04-07 | Output buffer for an electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101557224A true CN101557224A (en) | 2009-10-14 |
| CN101557224B CN101557224B (en) | 2011-11-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100911339A Expired - Fee Related CN101557224B (en) | 2008-04-07 | 2008-04-07 | Output buffer for an electronic device |
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| Country | Link |
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| CN (1) | CN101557224B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751974A (en) * | 2011-04-22 | 2012-10-24 | 联咏科技股份有限公司 | Output buffer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1377139A (en) * | 2001-03-28 | 2002-10-30 | 华邦电子股份有限公司 | Output buffer |
| ITTO20020811A1 (en) * | 2002-09-18 | 2004-03-19 | Atmel Corp | OUTPUT BUFFER WITH QUICK CONTROL. |
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2008
- 2008-04-07 CN CN2008100911339A patent/CN101557224B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751974A (en) * | 2011-04-22 | 2012-10-24 | 联咏科技股份有限公司 | Output buffer |
| CN102751974B (en) * | 2011-04-22 | 2015-02-25 | 联咏科技股份有限公司 | Output buffer |
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| Publication number | Publication date |
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| CN101557224B (en) | 2011-11-02 |
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