CN110535459A - A kind of digital level conversion circuit based on low voltage CMOS process - Google Patents
A kind of digital level conversion circuit based on low voltage CMOS process Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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Abstract
The invention discloses a kind of digital level conversion circuit based on low voltage CMOS process, including the first PMOS tube group, the first NMOS switch pipe, the second NMOS switch pipe and phase inverter, the digital level conversion circuit based on low voltage CMOS process has the first DC supply input, the second DC supply input, digital signal input end, the first digital signal output end and the second digital signal output end.The breakdown risk that the present invention can be exported based on more level in the case of low voltage CMOS process realization high input voltage, can be effectively reduced chip area and power consumption and can effectively avoid circuit.
Description
Technical field
The present invention relates to electronic circuit technology fields, and in particular to digital level conversion art.
Background technique
As MOS size is smaller and smaller, the voltage that can bear is lower and lower.Only pass through suitable level shifting circuit
Just it is able to achieve effective control of the low pressure digital circuit to high-tension circuit module.Metal-oxide-semiconductor needs to bear in traditional level shifting circuit
Maximum voltage be equal to supply voltage, so supply voltage not above metal-oxide-semiconductor safe voltage, otherwise will lead to metal-oxide-semiconductor breakdown.
In the prior art, patent No. CN108233917A discloses a kind of level shifting circuit, can be based on bi-cmos
Low pressure process realizes high voltage level conversion.But it has the disadvantage in that
1, output high level can only be supply voltage.
2, external offer reference voltage is needed to adjust output low level value.
3, bi-cmos technique is only limitted to using triode decompression, is not suitable for CMOS technology, and triode dimensions are much larger than
Metal-oxide-semiconductor occupies biggish chip area.
4, as shown in Figure 1, moment is connected in M2, the electric current for flowing through triode Q1 and Q3 is very big, then gradually smaller, works as M9
When grid voltage is less than Q1 and Q3 conduction threshold twice, voltage decline is very slow, but still remains electric leakage, between M8 mistake herein
End always in journey, so M9 grid voltage is final or can become 0, so that M9 is made finally to be broken down by high-voltage, therefore the circuit is not
It is able to achieve the holding of long-time current potential.In addition, being inserted into USB when IN is high level, M9 grid voltage is 0V at this time, and there are USB by M9
It is inserted into instantaneous pressure and punctures risk.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of digital level conversion electricity based on low voltage CMOS process
Road, the output of more level can be realized based on low voltage CMOS process, can effectively reduce chip area and power consumption and can be effective
Avoid the breakdown risk of circuit.
In order to solve the above-mentioned technical problems, the present invention provides a kind of, and the digital level based on low voltage CMOS process converts electricity
Road, including the first PMOS tube group, the first NMOS switch pipe, the second NMOS switch pipe and phase inverter, it is described to be based on low voltage CMOS work
The digital level conversion circuit of skill have the first DC supply input, the second DC supply input, digital signal input end,
First digital signal output end and the second digital signal output end；
The first PMOS tube group includes the first PMOS switch pipe, the second PMOS switch pipe and M to PMOS tube, each PMOS
The source electrode of pipe is shorted with the substrate of itself, and the grid of each PMOS tube is shorted with the drain electrode of itself；Wherein, M be greater than or
Integer equal to 1；
The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first source electrode to PMOS tube with
The first DC supply input connection；The grid of the first PMOS tube of the grid and the first side of the first PMOS switch pipe
It is connected, the drain electrode of the first PMOS switch pipe is connect with the grid of second side most end PMOS tube；2nd PMOS is opened
The grid for closing pipe is connected with the grid of the first PMOS tube of second side, and the drain electrode of the second PMOS switch pipe and the first side are most
The grid connection of last PMOS tube；The two neighboring PMOS tube of the same side is to be connected by series diode mode；
The drain electrode of the most end PMOS tube of first side, the drain electrode of the first NMOS switch pipe are counted with described first
Word signal output end connection, the drain electrode of the most end PMOS tube of described second side, the drain electrode of the second NMOS switch pipe with
The second digital signal output end connection；The grid of the first NMOS switch pipe, the phase inverter input terminal and institute
State digital signal input end connection；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；It is described anti-
The power end of phase device is connect with second DC supply input；The source electrode of the first NMOS switch pipe, described second
The source electrode of NMOS switch pipe is grounded with the ground terminal of the phase inverter altogether.
Further, first side most end PMOS tube drain electrode and the drain electrode of the first NMOS switch pipe it
Between further include PMOS tube that J series diode mode connects, described second side most end PMOS tube drain electrode with it is described
It further include the PMOS tube that J series diode mode connects, the source electrode of each PMOS tube between the drain electrode of second NMOS switch pipe
It is shorted with the substrate of itself, the grid of each PMOS tube is shorted with the drain electrode of itself；Wherein, J is whole more than or equal to 0
Number.
It further, further include N number of connect between the first PMOS tube group and first DC supply input
The PMOS tube of diode fashion connection；Wherein, N is the integer more than or equal to 0.
Digital level in order to solve identical technical problem, the present invention also provides another kind based on low voltage CMOS process
Conversion circuit, including first resistor group, the first NMOS switch pipe, the second NMOS switch pipe and phase inverter, it is described to be based on low pressure
The digital level conversion circuit of CMOS technology has the first DC supply input, the second DC supply input, digital signal
Input terminal, the first digital signal output end and the second digital signal output end；
The first resistor group includes the first PMOS switch pipe, the second PMOS switch pipe and M to resistance；Wherein, M be greater than
Or the integer equal to 1；
The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first first end to resistance with
The first DC supply input connection；The second end of the first resistance of the grid and the first side of the first PMOS switch pipe
It is connected, the drain electrode of the first PMOS switch pipe is connect with the second end of second side most end resistance；2nd PMOS is opened
The grid for closing pipe is connected with the second end of the first resistance of second side, and the drain electrode of the second PMOS switch pipe and the first side are most
The second end connection of last resistance；The two neighboring resistance of the same side is to be connected in series；
The drain electrode of the second end of the most end resistance of first side, the first NMOS switch pipe is counted with described first
Word signal output end connection, the second end of the most end resistance of described second side, the second NMOS switch pipe drain electrode with
The second digital signal output end connection；The grid of the first NMOS switch pipe, the phase inverter input terminal and institute
State digital signal input end connection；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；It is described anti-
The power end of phase device is connect with second DC supply input；The source electrode of the first NMOS switch pipe, described second
The source electrode of NMOS switch pipe is grounded with the ground terminal of the phase inverter altogether.
Compared with the prior art, the invention has the following beneficial effects:
1, the present invention can realize more level outputs based on low voltage CMOS process.
2, the present invention only needs lesser chip area and lower power consumption.
3, the present invention does not need any external reference voltage.
4, breakdown risk is not present when input is any level in the present invention.
5, the present invention is suitable for KHz or less rank level conversion function, need to properly increase static state when conversion rate improves
Power consumption.Metal-oxide-semiconductor high-voltage breakdown risk is not present when inputting constant.
Detailed description of the invention
Fig. 1 is level shifting circuit schematic diagram in the prior art；
Fig. 2 is the circuit signal for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides
Figure；
Fig. 3 is another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides
Schematic diagram；
Fig. 4 is the another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides
Schematic diagram；
Fig. 5 is the another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides
Schematic diagram；
Fig. 6 is the another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides
Schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Embodiment one:
Fig. 2 is referred to, the embodiment of the invention provides a kind of digital level conversion circuit based on low voltage CMOS process, packet
The first PMOS tube group, the first NMOS switch pipe MNSWA, the second NMOS switch pipe MNSWB and phase inverter are included, it is described to be based on low pressure
The digital level conversion circuit of CMOS technology has the first DC supply input VH, the second DC supply input VL, number
Signal input part VI, the first digital signal output end VON and the second digital signal output end VOP；
The first PMOS tube group includes the first PMOS switch pipe MPSWA, the second PMOS switch pipe MPSWB and M to PMOS
Pipe, the source electrode of each PMOS tube are shorted with the substrate of itself, and the grid of each PMOS tube is shorted with the drain electrode of itself；Its
In, M is the integer more than or equal to 1；
The source electrode of the first PMOS switch pipe MPSWA, the source electrode of the second PMOS switch pipe MPSWB and first to PMOS tube
Source electrode connect with the first DC supply input VH；The grid of the first PMOS switch pipe MPSWA and the first side
The grid of first PMOS tube be connected, the drain electrode of the first PMOS switch pipe MPSWA and second side most end PMOS tube
Grid connection；The grid of the second PMOS switch pipe MPSWB is connected with the grid of the first PMOS tube of second side, and described
The drain electrode of two PMOS switch pipe MPSWB is connect with the grid of the first side most end PMOS tube；The two neighboring PMOS tube of the same side
To be connected by series diode mode；
The drain electrode of the most end PMOS tube of first side, the drain electrode of the first NMOS switch pipe MNSWA with it is described
First digital signal output end VON connection, the drain electrode of the most end PMOS tube of described second side, the second NMOS switch pipe
The drain electrode of MNSWB is connect with the second digital signal output end VOP；The grid of the first NMOS switch pipe MNSWA, institute
The input terminal for stating phase inverter is connect with the digital signal input end VI；The output end of the phase inverter and the 2nd NMOS
The grid of switching tube MNSWB connects；The power end of the phase inverter is connect with the second DC supply input VL；Described
The source electrode of one NMOS switch pipe MNSWA, the source electrode of the second NMOS switch pipe MNSWB are total with the ground terminal of the phase inverter
Ground connection.
In a particular embodiment, further, first side most end PMOS tube drain electrode and described first
Further include the PMOS tube that J series diode mode connects between the drain electrode of NMOS switch pipe MNSWA, described second side most
It further include that J series diode mode connects between the drain electrode and the drain electrode of the second NMOS switch pipe MNSWB of last PMOS tube
The PMOS tube (area J referring to fig. 2) connect, the source electrode of each PMOS tube are shorted with the substrate of itself, the grid of each PMOS tube
It is shorted with the drain electrode of itself；Wherein, J is the integer more than or equal to 0.
In a particular embodiment, further, in the first PMOS tube group and the first DC supply input VH
Between further include PMOS tube (area N referring to fig. 2) that N number of series diode mode connects；Wherein, N is whole more than or equal to 0
Number.
The following are the preferred embodiment of the present invention:
Continuing with referring to fig. 2, the area N includes the PMOS that N number of series diode mode connects, and the area M includes M series diode
The area the PMOS that mode connects, J includes the PMOS that J series diode mode connects.Wherein, N and J desirable appointing more than or equal to zero
Meaning integer, the desirable arbitrary integer more than or equal to 1 of M, but it should be recognized that ensure that VH/ (N+M+J) not be far below MOS
Pipe threshold voltage causes level conversion response speed very slow or is unable to normal response in order to avoid metal-oxide-semiconductor works in cut-off region.
MPSWA and MPSWB is PMOS switch pipe.MNSWA and MNSWB is NMOS switch pipe.
First DC supply input VH is high-voltage DC power supply, and the second DC supply input VL is low-voltage DC
Source.INV unit is phase inverter of the work in VL power domain.Digital signal input end VI is the Any Digit signal of VL power domain.
First digital signal output end VON is the digital signal with VI same-phase, and high level is (M+J)/(N+M+J),
Low level is J/ (N+M+J).
Second digital signal output end VOP is the digital signal with VI antiphase, and high level is (M+J)/(N+M+J),
Low level is J/ (N+M+J).
The following are working principle descriptions:
N1~NN, MA1~MAM, MB1~MBM, JA1~JAM, JB1~JBM constitute potential-divider network, the source of each PMOS tube
Pole is all shorted with substrate, and grid is all shorted with drain electrode, therefore does not have high-voltage breakdown risk.MPSWA and MPSWB constitutes positive feedback
The charging of network acceleration VOP and VON node.It analyzes known to circuit:
When VI is equal to 0, VOP is equal to VH × J/ (N+M+J), and VON is equal to VH × (M+J)/(N+M+J)；
When VI is equal to VL, VOP is equal to VH × (M+J)/(N+M+J), and VON is equal to VH × J/ (N+M+J).
Fig. 3 is referred to, application examples 1: being powered using the USB interface of 3.3V MOS technology controlling and process 5V to chip system.Such as Fig. 3
It is shown, circuit design in two steps: step 1: setting N=0, M=J=2；Metal-oxide-semiconductor is set to exist step 2: suitable breadth length ratio is arranged
Conducting electric current is 0.1uA under 1.25V pressure drop, then system power dissipation is 0.1uA.
Initial time: input VI=3.3V, according to VOP=5V illustrated above, the cut-off of SW1 switching tube, USB stops being system
Power supply.
Second moment: when input becomes 0V, MNSWA and MPSWA cut-off, MNSWB and MPSWB are connected.MPSWB accelerates VON
Node voltage rises, VOP=2.5V, and SW1 switching tube conducting, USB starts as system power supply.
The third moment: when input becomes 3.3V, MNSWA and MPSWA conducting, MNSWB and MPSWB end.MPSWA accelerates
VOP node voltage rises, VOP=5V, the cut-off of SW1 switching tube, and USB stops being system power supply.
Fig. 4 is referred to, application examples 2: providing the adjustable economize on electricity of 1 bit digital using the USB interface of 3.3V MOS technology controlling and process 5V
Stream.As shown in figure 4, circuit design is in two steps: step 1: setting N=1, M=J=2；Step 2: suitable breadth length ratio, which is arranged, to be made
Metal-oxide-semiconductor conducting electric current under 1V pressure drop is 0.1uA, then system power dissipation is 0.1uA.
Initial time: input VI=3.3V, providing electric current according to VOP=4V illustrated above, USB is (1-VTH)/R1,
(note: it is assumed that the breadth length ratio of SW1 is sufficiently large.VTH is the absolute value of the threshold voltage of SW1).
Second moment: when input becomes VI=0V, MNSWA and MPSWA cut-off, MNSWB and MPSWB are connected.MPSWB accelerates
VON node voltage rises, and it is (4-VTH)/R1 that VOP=1V, USB, which provide electric current,.
The third moment: when input becomes VI=3.3V, MNSWA and MPSWA conducting, MNSWB and MPSWB end.MPSWA adds
Fast VOP node voltage rises, and it is (1-VTH)/R1 that VOP=4V, USB, which provide electric current,.Supply current is by K parallel outputs, and
One is R1 using resistance value, and K are 2 using resistanceK-1R1, then 2 can be realized by exporting electric currentKA regulation stall.
In a particular embodiment, M can be set as to 1, as shown in Figure 6.
Compared with the prior art, the invention has the following beneficial effects:
1, the high/low level of number for being higher than its pressure voltage can be obtained based on low pressure metal-oxide-semiconductor, on condition that the difference of low and high level
Lower than metal-oxide-semiconductor pressure voltage.
2, the breadth length ratio of each metal-oxide-semiconductor is set as β, and single metal-oxide-semiconductor gate source voltage and drain-source voltage are all VH/ (N+M+J).In
In the case that VH is determined, N+M+J can be increased or reduce β and realize low-power consumption.
3, output low and high level can be set as needed arbitrarily to have score greater than 0 with less than VH, but ensure VH/ (N
+ M+J) should not be far below metal-oxide-semiconductor threshold value in case metal-oxide-semiconductor work in cut-off region.Such as setting VH=5V, N=1, M=J=2.Then
Exporting high level isLow level is
Embodiment two:
Refer to Fig. 5, it should be noted that N1~NN in above-described embodiment one, MA1~MAM, MB1~MBM, JA1~
JAM, JB1~JBM can also realize same design effect using resistance substitution.Physical circuit is as shown in figure 5, include first resistor
Group, the first NMOS switch pipe MNSWA, the second NMOS switch pipe MNSWB and phase inverter, the number based on low voltage CMOS process
Level shifting circuit has the first DC supply input VH, the second DC supply input VL, digital signal input end VI, the
One digital signal output end VON and the second digital signal output end VOP；
The first resistor group includes the first PMOS switch pipe MPSWA, the second PMOS switch pipe MPSWB and M to resistance；Its
In, M is the integer more than or equal to 1；
The source electrode of the first PMOS switch pipe MPSWA, the source electrode of the second PMOS switch pipe MPSWB and first to resistance
First end is connect with the first DC supply input VH；The grid of the first PMOS switch pipe MPSWA and the first side
The second end of first resistance be connected, the of the drain electrode of the first PMOS switch pipe MPSWA and second side most end resistance
The connection of two ends；The grid of the second PMOS switch pipe MPSWB is connected with the second end of the first resistance of second side, and described
The drain electrode of two PMOS switch pipe MPSWB is connect with the second end of the first side most end resistance；The two neighboring resistance of the same side is
It is connected in series；
The second end of the most end resistance of first side, the first NMOS switch pipe MNSWA drain electrode with it is described
First digital signal output end VON connection, the second end of the most end resistance of described second side, the second NMOS switch pipe
The drain electrode of MNSWB is connect with the second digital signal output end VOP；The grid of the first NMOS switch pipe MNSWA, institute
The input terminal for stating phase inverter is connect with the digital signal input end VI；The output end of the phase inverter and the 2nd NMOS
The grid of switching tube MNSWB connects；The power end of the phase inverter is connect with the second DC supply input VL；Described
The source electrode of one NMOS switch pipe MNSWA, the source electrode of the second NMOS switch pipe MNSWB are total with the ground terminal of the phase inverter
Ground connection.
Further, first side most end resistance second end and the first NMOS switch pipe MNSWA
It further include the resistance of J series connection between drain electrode, in the second end and described second of the most end resistance of described second side
It further include the resistance of J series connection between the drain electrode of NMOS switch pipe MNSWB；Wherein, J is the integer more than or equal to 0.
It further, further include N number of connect between the first resistor group and the first DC supply input VH
The resistance of connection；Wherein, N is the integer more than or equal to 0.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (6)
1. a kind of digital level conversion circuit based on low voltage CMOS process, which is characterized in that including the first PMOS tube group, first
NMOS switch pipe, the second NMOS switch pipe and phase inverter, the digital level conversion circuit based on low voltage CMOS process have
First DC supply input, the second DC supply input, digital signal input end, the first digital signal output end and second
Digital signal output end；
The first PMOS tube group includes the first PMOS switch pipe, the second PMOS switch pipe and M to PMOS tube, each PMOS tube
Source electrode is shorted with the substrate of itself, and the grid of each PMOS tube is shorted with the drain electrode of itself；Wherein, M is more than or equal to 1
Integer；
The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first source electrode to PMOS tube with it is described
The connection of first DC supply input；The grid of the first PMOS tube of the grid and the first side of the first PMOS switch pipe is connected
It connects, the drain electrode of the first PMOS switch pipe is connect with the grid of second side most end PMOS tube；The second PMOS switch pipe
Grid be connected with the grid of the first PMOS tube of second side, the drain electrode of the second PMOS switch pipe and the first side most end
The grid of PMOS tube connects；The two neighboring PMOS tube of the same side is to be connected by series diode mode；
The drain electrode of the most end PMOS tube of first side, the drain electrode of the first NMOS switch pipe are believed with first number
The connection of number output end, the drain electrode of the most end PMOS tube of described second side, the drain electrode of the second NMOS switch pipe with it is described
The connection of second digital signal output end；The grid of the first NMOS switch pipe, the phase inverter input terminal with the number
The connection of word signal input part；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；The phase inverter
Power end connect with second DC supply input；The source electrode of the first NMOS switch pipe, the 2nd NMOS are opened
The source electrode for closing pipe is grounded with the ground terminal of the phase inverter altogether.
2. the digital level conversion circuit according to claim 1 based on low voltage CMOS process, which is characterized in that described
It further include J series diode side between the drain electrode and the drain electrode of the first NMOS switch pipe of the most end PMOS tube of first side
The PMOS tube of formula connection, between the drain electrode and the drain electrode of the second NMOS switch pipe of the most end PMOS tube of described second side
It further include the PMOS tube that J series diode mode connects, the source electrode of each PMOS tube is shorted with the substrate of itself, each
The grid of PMOS tube is shorted with the drain electrode of itself；Wherein, J is the integer more than or equal to 0.
3. the digital level conversion circuit according to claim 1 based on low voltage CMOS process, which is characterized in that described
It further include the PMOS tube that N number of series diode mode connects between first PMOS tube group and first DC supply input；
Wherein, N is the integer more than or equal to 0.
4. a kind of digital level conversion circuit based on low voltage CMOS process, which is characterized in that including first resistor group, first
NMOS switch pipe, the second NMOS switch pipe and phase inverter, the digital level conversion circuit based on low voltage CMOS process have
First DC supply input, the second DC supply input, digital signal input end, the first digital signal output end and second
Digital signal output end；
The first resistor group includes the first PMOS switch pipe, the second PMOS switch pipe and M to resistance；Wherein, M is to be greater than or wait
In 1 integer；
The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first first end to resistance with it is described
The connection of first DC supply input；The second end of the first resistance of the grid and the first side of the first PMOS switch pipe is connected
It connects, the drain electrode of the first PMOS switch pipe is connect with the second end of second side most end resistance；The second PMOS switch pipe
Grid be connected with the second end of the first resistance of second side, the drain electrode of the second PMOS switch pipe and the first side most end
The second end of resistance connects；The two neighboring resistance of the same side is to be connected in series；
The drain electrode of the second end of the most end resistance of first side, the first NMOS switch pipe is believed with first number
The connection of number output end, the second end of the most end resistance of described second side, the second NMOS switch pipe drain electrode with it is described
The connection of second digital signal output end；The grid of the first NMOS switch pipe, the phase inverter input terminal with the number
The connection of word signal input part；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；The phase inverter
Power end connect with second DC supply input；The source electrode of the first NMOS switch pipe, the 2nd NMOS are opened
The source electrode for closing pipe is grounded with the ground terminal of the phase inverter altogether.
5. the digital level conversion circuit according to claim 4 based on low voltage CMOS process, which is characterized in that described
It further include the electricity of J series connection between the second end of the most end resistance of first side and the drain electrode of the first NMOS switch pipe
Resistance further includes J string between the second end of the most end resistance of described second side and the drain electrode of the second NMOS switch pipe
Join the resistance of connection；Wherein, J is the integer more than or equal to 0.
6. the digital level conversion circuit according to claim 4 based on low voltage CMOS process, which is characterized in that described
It further include the resistance of N number of series connection between first resistor group and first DC supply input；Wherein, N be greater than or
Integer equal to 0.
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| CN201910948050.5A CN110535459A (en) | 2019-09-30 | 2019-09-30 | A kind of digital level conversion circuit based on low voltage CMOS process |
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| CN201910948050.5A CN110535459A (en) | 2019-09-30 | 2019-09-30 | A kind of digital level conversion circuit based on low voltage CMOS process |
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| CN (1) | CN110535459A (en) |
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