CN105811960A - Level shifting circuit using thin gate oxide MOS tubes - Google Patents

Abstract

The invention relates to the technology of electric circuits, more particularly to a level shifting circuit using thin gate oxide MOS tubes. The circuit provided in the invention distinguishes itself from others in that thin gate oxide MOS tubes are used to constitute its driving stage rather than thick gate oxide MOS tubes seen in traditional high-voltage level shifting circuits. The adoption of thin gate oxide MOS tubes reduces the power consumption of the level shifting circuit while increasing the work frequency of a high voltage supply converter. Compared to available level shifting circuits, the level shifting circuit provided by the invention uses capacitance as its load, and utilizes the second capacitance and the third capacitance to protect the gates of the first PMOS tube and the first power PMOS tube so that the voltage at the gates remains to be within 5V and that thin gate oxide MOS tubes can be compatible with the circuit. In this manner, the performances of the circuit improve.

Description

A Level Shift Circuit for Thin Gate Oxide MOS Transistor

technical field

The invention relates to electronic circuit technology, in particular to a level shift circuit for thin gate oxide MOS transistors.

Background technique

Level shifting circuit is one of the typical circuits of HVIC (High Voltage Integrated Circuit). Due to its high reliability, small area, and high energy efficiency, it is widely used in smart vehicle electronics, renewable energy systems, and high-brightness LED lighting systems. In order to improve its power density, the level shift circuit has to work at a high switching frequency to reduce the size of the passive device part; in order to improve its power efficiency, it is necessary to realize zero voltage switching to reduce the switching loss of the level shift circuit. Compared with thick gate oxide high voltage power MOS transistors, thin gate oxide high voltage power MOS transistors have low on-resistance and low sub-threshold voltage. Therefore, the thin gate oxide high voltage power MOS transistor can reduce the power loss of the level shift circuit and increase the operating frequency of the high voltage power converter.

Although the source and drain of the thin gate oxide high-voltage power MOS can withstand high voltage, the result of the thin gate oxide is that the gate-source voltage it can withstand is very small, generally around 5V. However, the current level-shifting circuits require high-voltage power MOS transistors to withstand high gate-source voltage values, which hinders the application of thin gate oxide high-voltage power MOS.

A relatively classic high-voltage level shift circuit is shown in Figure 1, including a Schmitt trigger connected to the input signal, 4 MOS transistors and an inverter forming the level shift function, and a voltage divider BJT tube, capacitor, resistor, and Zener diode. This circuit has a simple structure and can well realize the level shift function. However, the power PMOS tube needs to withstand a high gate voltage, and it is impossible to apply the thin gate oxide power MOS tube to this circuit. In this way, the circuit performance cannot be further improved.

Contents of the invention

Aiming at the above problems, the present invention proposes a level shift circuit for a thin gate oxide MOS transistor.

Technical solution of the present invention: a level shift circuit for thin gate oxide MOS transistors, including a first capacitor C1, a second capacitor C2, a third capacitor C3, a first Zener diode D1, and a second Zener diode D2 , a first resistor R1, a second resistor R2, an NPN transistor NPN1, a PMOS transistor MP1, a power PMOS transistor PMP1, an NMOS transistor MN1, an inverter and a Schmitt trigger; the input end of the Schmitt trigger is an electric The input end of the level displacement circuit; the collector of the NPN transistor NPN1 is connected to the power supply, the base is connected to the power supply after passing through the first resistor R1, and its emitter is grounded after passing through the first capacitor C1; the base of the NPN transistor NPN1 is connected to the first resistor R1 The connection point of the first Zener diode D1 is connected to the cathode of the first Zener diode D1, and the anode of the first Zener diode D1 is grounded; the connection point between the emitter of the NPN transistor NPN1 and the first capacitor C1 is connected to the power supply input end of the Schmitt trigger; The negative input terminal of the special trigger is grounded, and its output terminal is connected to the gate of NMOS transistor MN1; the source of PMOS transistor MP1 is connected to the power supply, and its gate is connected to the power supply after passing through the second resistor R2; the gate of PMOS transistor MP1 is connected to the second resistor The connection point of R2 is connected to the output terminal of the Schmitt trigger after passing through the second capacitor C2; the drain of the PMOS transistor MP1 is connected to the anode of the second Zener diode D2; the source of the power PMOS transistor PMP1 is connected to the power supply, and its gate is connected to The connection point between the drain of the PMOS transistor MP1 and the anode of the second zener diode D2; the connection point between the gate of the power PMOS transistor PMP1, the drain of the PMOS transistor MP1 and the anode of the second zener diode D2 is connected to the NMOS transistor MN1 after passing through the third capacitor C3 The drain of the NMOS transistor MN1 is grounded; the input terminal of the inverter is connected to the output terminal of the Schmitt trigger, and the output terminal of the inverter is connected to the gate of the power NMOS transistor PMN1; the source of the power NMOS transistor PMN1 It is grounded, and its drain is connected to the drain of the power PMOS transistor PMP1; the connection point between the source of the NMOS transistor PMN1 and the drain of the power PMOS transistor PMP1 is the output end of the level shift circuit.

The beneficial effect of the present invention is that, compared with the original level shift circuit structure, the level shift circuit of the present invention uses a capacitor as a load, and uses the second capacitor and the third capacitor to protect the first PMOS transistor and the first power PMOS transistor The gate makes the floating range of the gate voltage within 5V, and the thin gate oxide MOS tube can be applied to this circuit, thereby improving the circuit performance.

Description of drawings

Fig. 1 is an existing classic level shift circuit diagram;

Fig. 2 is the functional block diagram of embodiment;

Fig. 3 is the schematic diagram of the circuit structure of embodiment;

Fig. 4 is the logic schematic diagram of the simulation result of embodiment;

Fig. 5 is a schematic diagram of the simulation results of the embodiment.

detailed description

Below in conjunction with accompanying drawing and embodiment the present invention is described in detail

Example

As shown in Figure 3, the level shift circuit suitable for thin gate oxide MOS transistors in this embodiment includes two resistors, two Zener diodes, a Schmitt trigger, three capacitors, and an inverter, One NMOS transistor, one PMOS transistor, one thin gate oxide power NMOS transistor, one thin gate oxide power PMOS transistor, the withstand voltage value of the first Zener diode is 5.7V, and the first Zener diode D1 provides the first NPN transistor NPN1 Forward bias, so that the first NPN transistor NPN1 is in the open state, the first resistor R1 provides the bias voltage between the base and the collector of the first NPN transistor NPN1, and the first capacitor C1 is used to provide a divided voltage value of 5V for the application The Mitte trigger is used as the power supply voltage, and the Schmitt trigger is used to shape the input signal. The input signal is a 3.3V or 5V TTL signal or a CMOS level signal, and the output terminal of the Schmitt trigger is connected to the cathode of the second capacitor C2 The anode of the second capacitor C2 is connected to the cathode of the second resistor R2, the anode of the second capacitor C2 is connected to the gate of the first PMOS transistor MP1, the anode of the second resistor is connected to the power supply VCC, and the source of the first PMOS transistor MP1 is connected to The power supply VCC, the drain of the first PMOS transistor MP1 is connected to the anode of the second Zener diode D2, the drain of the first PMOS transistor MP1 is connected to the anode of the third capacitor C3, and the drain of the first PMOS transistor MP1 is connected to the first thin The gate of the gate oxide PMOS transistor PMP1, the cathode of the second Zener diode D2 is connected to the power supply VCC, the source of the first thin gate oxide PMOS transistor PMP1 is connected to the power supply VCC, and the output stage of the Schmitt trigger is connected to the first NMOS The gate of the transistor MN1, the output stage of the Schmitt trigger is connected to the input stage of the first inverter INV1, the drain of the first NMOS transistor MN1 is connected to the cathode of the third capacitor C3, and the source of the first NMOS transistor MN1 is grounded , the output stage of the first inverter INV1 is connected to the gate of the first thin gate oxide NMOS transistor PMN1, the source of the first thin gate oxide NMOS transistor PMN1 is grounded, and the drain of the first thin gate oxide NMOS transistor PMN1 is connected to the first The drain of the thin gate oxide PMOS transistor PMP1, the drain of the first thin gate oxide PMOS transistor PMP1 and the drain of the first thin gate oxide NMOS transistor PMN1 are the output terminals.

Taking this embodiment as an example to illustrate the working principle of the overall circuit of the present invention:

In this embodiment, the power supply VCC of the circuit is 15V, the power supply of the Schmitt trigger is 5V, the withstand voltage of the Zener diode is 5.7V, the first capacitor C1 is 1pF, the second capacitor C2 is 1pF, and the third capacitor C3 The output stage of this circuit uses a thin gate oxide MOS tube. The function of the level shift circuit is to transmit the output of the low voltage part of the high-end circuit to the high voltage part. In this circuit, the load capacitor controls the control part of the thin gate oxide MOS tube. It is a key part of the drive circuit.

When the output signal is at a high level, the output signal of the Schmitt trigger is at a high level, at this time the gate of the first PMOS transistor MP1 is at a high level, the first PMOS transistor MP1 is turned off, and the third capacitor C3 will not be Charging and discharging, the gate of the first NMOS transistor MN1 is at a high level, the first NMOS transistor MN1 is turned on, the cathode of the third capacitor C3 is grounded, the voltage at both ends of the third capacitor C3 remains unchanged, and the level of the anode of the third capacitor C3 is Pull down 5V, the difference between the anode level of the third capacitor C3 and the power supply VCC is 5V, the first thin gate oxide PMOS transistor PMP1 is turned on, the input stage of the first inverter INV1 is connected to a high level, and the output is a low level flat, the gate of the first thin-gate oxide PMOS transistor PMN1 is at low level, the first thin-gate oxide MOS transistor PMN1 is turned off, and the output signal OUT is at low level; when the input signal changes from high to low, the Schmitt trigger Output low level, the cathode level of the second capacitor C2 is 0V, the anode level of the second capacitor C2 is pulled down, the first PMOS transistor MP1 is turned on and charges the third capacitor C3, the gate of the first NMOS transistor MN1 is Low level, the first NMOS transistor MN1 is turned off, the level of the anode of the third capacitor jumps high and is equal to the power supply voltage VCC, the first thin gate oxide PMOS transistor PMP1 is turned off, and the input stage of the first inverter INV1 is low level, The output terminal is at a high level, the gate of the first thin gate oxide NMOS transistor PMN1 is at a high level, the first thin gate oxide NMOS transistor PMN1 is turned on, and the output signal OUT is at a low level, thereby successfully completing the transition of the level signal from low to to high conversion.

Figure 4 shows the logic diagram of the simulation results of this embodiment. The potential of the anode of the third capacitor C3 jumps with the jump of the input signal, and the floating level of the gate of the first thin gate oxide PMOS transistor is 10V-15V. The level is within the safe withstand voltage value.

The simulation conditions of the present embodiment are: power supply VCC=15V; the withstand voltage of the first zener diode D1 is 5.7V; the supply voltage of the Schmitt trigger is 5V; the circuit input signal range: 0V～5V (3.3V), the output signal Range: 0V-15V. The simulation result is shown in Fig. 5, and the purpose of high and low level displacement is achieved.

In summary, a level shift circuit suitable for thin gate oxide MOS transistors according to the present invention can be used as a basic circuit in a semiconductor integrated circuit power electronic chip or a driver chip, and can improve the energy efficiency of HVIC.

Claims (1)

1. A level shift circuit for thin gate oxide MOS transistors, comprising a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first zener diode (D1), a second Zener diode (D2), first resistor (R1), second resistor (R2), NPN transistor (NPN1), PMOS transistor (MP1), power PMOS transistor (PMP1), NMOS transistor (MN1), inverter and Schmitt trigger; the input of the Schmitt trigger is the input of the level shift circuit; the collector of the NPN triode (NPN1) is connected to the power supply, and the base is connected to the power supply after passing through the first resistor (R1). Its emitter is grounded after passing through the first capacitor (C1); the connection point between the base of the NPN transistor (NPN1) and the first resistor (R1) is connected to the cathode of the first Zener diode (D1), and the first Zener diode (D1) ) of the anode is grounded; the connection point between the emitter of the NPN transistor (NPN1) and the first capacitor (C1) is connected to the power input terminal of the Schmitt trigger; the negative input terminal of the Schmitt trigger is grounded, and its output terminal is connected to the NMOS The gate of the tube (MN1); the source of the PMOS tube (MP1) is connected to the power supply, and its gate is connected to the power supply after passing through the second resistor (R2); the connection point between the gate of the PMOS tube (MP1) and the second resistor (R2) After the second capacitor (C2) is connected to the output end of the Schmitt trigger; the drain of the PMOS transistor (MP1) is connected to the anode of the second Zener diode (D2); the source of the power PMOS transistor (PMP1) is connected to the power supply, Its gate is connected to the connection point between the drain of the PMOS transistor (MP1) and the anode of the second Zener diode (D2); the gate of the power PMOS transistor (PMP1), the drain of the PMOS transistor (MP1) and the second Zener diode (D2) The positive connection point is connected to the drain of the NMOS transistor (MN1) through the third capacitor (C3); the source of the NMOS transistor (MN1) is grounded; the input terminal of the inverter is connected to the output terminal of the Schmitt trigger, inverting The output terminal of the device is connected to the gate of the power NMOS transistor (PMN1); the source of the power NMOS transistor (PMN1) is grounded, and its drain is connected to the drain of the power PMOS transistor (PMP1); the source of the NMOS transistor (PMN1) is connected to the power PMOS The connection point of the drain of the tube (PMP1) is the output end of the level shift circuit.