CN110048707A - High speed and wide scope level shifter - Google Patents
High speed and wide scope level shifter Download PDFInfo
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- CN110048707A CN110048707A CN201810034946.8A CN201810034946A CN110048707A CN 110048707 A CN110048707 A CN 110048707A CN 201810034946 A CN201810034946 A CN 201810034946A CN 110048707 A CN110048707 A CN 110048707A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
Abstract
The present invention relates to a kind of high speeds and wide scope level shifter.The some aspects of the disclosure are related to a kind of device.The device includes the first push-pull circuit, the first phase inverter, the second push-pull circuit and third push-pull circuit.First push-pull circuit can operate the input signal for receiving first voltage domain, and provide the first M signal in second voltage domain.Second low-pressure region is different from first voltage domain.First phase inverter is operable to first M signal and provides the inversion signal in second voltage domain.Second push-pull circuit be operable to input signal and reverse signal at least one of the second M signal in second voltage domain is provided.Third push-pull circuit is operable at least one of first M signal and second M signal and provides output voltage signal.Output voltage signal follows inversion signal.
Description
Technical field
Embodiment of the disclosure relates in general to voltage level offset device, and more particularly, to for phaselocked loop (PLL)
Voltage level offset device.
Background technique
Electronic system includes various electronic devices, such as PLL and input/output (I/O) device.These devices can be with thermocouple
It closes, and is operated in different voltage domains.In order to support all these devices, voltage level offset device to be widely used in
Different voltages deviate between domain.Conventional level deviator includes cross-linked framework circuit.However, these conventional levels deviate
Device only can be with the low-speed handing lower than 100MHz.
Summary of the invention
Embodiment of the disclosure provides a kind of device and electronic system.Device include the first push-pull circuit, the first phase inverter,
Second push-pull circuit and third push-pull circuit.First push-pull circuit is operable as receiving the input signal in first voltage domain and mention
For the first M signal in second voltage domain.Second voltage domain is different from first voltage domain.First phase inverter is operable to
The inversion signal in first M signal offer second voltage domain.Second push-pull circuit is operable to input signal and reverse phase letter
Number at least one of provide second voltage domain second M signal.Third push-pull circuit is operable to letter among first
Number and at least one of second M signal output voltage signal is provided.Output voltage signal follows inversion signal.
It is appreciated that this part content is not intended to the key or essential feature of the implementation of the identification disclosure,
It is not intended to for limiting the scope of the present disclosure.Some other feature of the disclosure will become prone to manage according to the following description
Solution.
Detailed description of the invention
Above and other object of the disclosure, feature and advantage will be real according to the example of the disclosure more specifically described
It applies example and attached drawing and becomes obvious, wherein similar number is frequently used for indicating similar in the example embodiment of the disclosure
Component.
Fig. 1 shows the environment of the example electronic system of one embodiment according to the disclosure；
Fig. 2 shows the examples of conventional level deviator；
Fig. 3 shows the variation of the conventional level deviator of Fig. 2；
Fig. 4 shows the level shifter of one embodiment according to the disclosure；
Fig. 5 shows the variation of level shifter shown in Fig. 4；
Fig. 6 shows level shifter according to another embodiment of the present disclosure；And
Fig. 7 shows the variation of level shifter shown in fig. 6.
Specific embodiment
Hereinafter, the disclosure will be described with reference to multiple embodiments.It is appreciated that the discussion of these embodiments is used for
So that those skilled in the art more fully understand and thus implement the disclosure, rather than imply to content of this disclosure
Any restrictions.
It is as used herein like that, term " includes " and its variant can be construed to open meaning " including but not
It is limited to ".Term "based" should be understood that " being based at least partially on ".Term " embodiment " or " one embodiment " should be by
It is interpreted as " at least one embodiment ".Term " another embodiment " will be read as " at least one other embodiment ".Term
" first ", " second " etc. may refer to different or identical object.Term " native transistor (native
Transistor) " may refer to various Metal Oxide Semiconductor Field Effect Transistor (MOSFET), in enhancement mode and
The centre of depletion-mode.Native transistor is the transistor with nearly zero threshold voltage.In general, native transistor can be n ditch
Road native transistor.Term " I/O transistor " may refer to the transistor for I/O device.I/O transistor is compared to primary
Transistor has the transistor of more high threshold voltage.Due to caused by thicker gate oxide, the operation of I/O transistor is than primary
Transistor is slower, but can be resistant to higher voltage.Term " push-pull circuit " may refer to the connection with opposed polarity
Transistor is operable as alternate conduction.Hereafter it is also possible that other specific and implicit definition.
It may relate to some specific numerical value or numberical range in the following description.It should be appreciated that these numerical value sum numbers
Value range is only exemplary, and is advantageously possible for being committed to practice by the thought of the disclosure.However, exemplary being retouched to these
It states and is not intended to be in any way limiting the scope of the present disclosure.According to specific application scenarios and demand, these numerical value or numerical value model
Enclosing separately to be arranged.
In addition, some specific materials can be described in an illustrative manner.It is appreciated that these materials are only for showing
The purpose of example, can be advantageous some aspects of the disclosure.However, these exemplary descriptions are not intended to
It limits the scope of the present disclosure in any way.According to some concrete application situations and demand, it can choose other materials.
As described above, level shifter can be widely applied to electronic system to deviate between different voltages domain.
Fig. 1 shows the environment of the example electronic system 10 according to one embodiment.Electronic system 10 include PLL 12,
Level shifter 14 and I/O device 16.The PLL signal in the generation of PLL 12 first voltage domain.In one example, first voltage domain
It can be between 0V and 1V.Level shifter (shifter) 14 receives the PLL signal in first voltage domain, and is offset to
The signal in second voltage domain is to meet the needs of I/O device is for input voltage.It second voltage domain can be between 0V and 1.8V.
Although describing embodiment of the disclosure about second voltage domain, this, which is only exemplary rather than, appoints the scope of the present disclosure
What is limited.In alternative embodiment, second voltage domain can be between 0V and 3.3V.
Fig. 2 shows the examples of conventional level deviator 141.Level shifter 141 includes phase inverter 42, cross-coupling electricity
Road and push-pull circuit.Inverters work is in first voltage domain, and cross-linked circuit and push-pull circuit work are in second voltage domain.
Cross-linked circuit includes the first PMOS device P2, the first NMOS device N2, the second PMOS device P4 and the second PMOS device
P4.Push-pull circuit includes third PMOS device P6 and third NMOS device N6.First to third PMOS device and first to third
NMOS device is I/O MOS device.
Input the mono- IN of PLL be low in first voltage domain in the case where, phase inverter 42 export reverse phase in first voltage
High RST in domain.First NMOS device N2 conducting, the second NMOS device N4 cut-off.Then, the second PMOS device P4 is connected, and
And second the drain electrode of PMOS device P4 be connected to power voltage line (Vddh), therefore be high level in second voltage domain.First
Therefore PMOS device P2 is turned off.In this case, push-pull circuit receives the high voltage in second voltage domain.Due to third
The grid of PMOS device P6 receives high voltage in second voltage domain, so third PMOS device P6 is turned off.3rd NMOS
Device N6 conducting, and therefore level shifter provides the low-voltage in second voltage domain at node OUT.
In the case where PLL signal IN is height in first voltage domain, phase inverter 42 exports the low-voltage of reverse phase.First
NMOS device N2 cut-off, the second NMOS device N4 conducting.Then, the first PMOS device P2 is connected, the leakage of the first PMOS device P2
Pole is connected to Vddh, therefore is high level in second voltage domain.Therefore second PMOS device P4 is turned off.In such case
Under, push-pull circuit receives low-voltage.Since the grid of third NMOS device N6 receives low-voltage, so third NMOS device N6
Cut-off.Third PMOS device P6 conducting, and therefore level shifter provides the height electricity in second voltage domain at node OUT
Pressure.
As described above, cross-linked circuit and push-pull circuit all include the I/O MOS device with thick gate oxide layer
The threshold voltage of part, I/O MOS device is likely to vary greatly at some process corners.In addition, the 3rd PMOS and NMOS device P6
Drain electrode and source electrode with N6 in different voltage levels due to vying each other.Due to these facts, when the frequency of input signal
When rate is high, level shifter cannot be overturn in time.
Fig. 3 shows the variant of traditional level shifter of Fig. 2.Other than cross-linked circuit, level shifter
142 are similar to the level shifter of Fig. 2.Cross-coupled circuit in Fig. 3 include the first PMOS device P2, the second PMOS device,
First NMOS device N5, the second NMOS device N7, the 4th NMOS device N1 and the 5th NMOS device N3.First NMOS device N5 and
The grid of second NMOS device N7 is coupled to receive constant high voltage (Vbias) to keep the first NMOS device N5 and second
N7 conducting.4th NMOS device N1 and the 5th NMOS device N3 is with the first NMOS device N2 and the second NMOS device N4 with Fig. 2
Similar mode works.By with the I/O NMOS device of series connection and primary NMOS device replace I/O NMOS device N2 and
The level shifter 142 of N4, Fig. 3 can the level shifter 141 than Fig. 2 quickly operate, this is because primary NMOS device
It is quickly operated than I/O NMOS device.For example, level shifter 142 can be operated with the speed of 300MHz.
Although level shifter 142 improves service speed compared with level shifter 141, some high speeds are answered
For, service speed may be still undesirable.In order to further increase service speed, some conventional solutions are for Fig. 1
Large scale ratio is used with the transistor device of Fig. 2.Because large scale ratio may reduce competition to a certain extent.So
And large scale ratio will inevitably increase chip size, this is because some transistors needs are made very greatly to ensure
Big dimensional ratios.
Although level shifter 142 improves service speed compared with level shifter 141, some high speeds are answered
For, service speed may not be desired.In order to further increase service speed, some conventional solutions are for figure
The transistor device of 1 and Fig. 2 uses large scale ratio.Because large scale ratio may reduce contention to a certain extent.However,
Large scale ratio will inevitably increase chip size, because some transistors needs are made very greatly to ensure big size
Than.
Fig. 4 shows level shifter 143 according to an embodiment of the present disclosure.Level shifter 143 includes being coupled in power supply
Pressure-wire Vddh and the first push-pull circuit being grounded between (GND), the first phase inverter 44 for being coupled to the first push-pull circuit, coupling
It is pushed away in power voltage line Vddh GND and the third being coupled between power voltage line Vddh and the output of the first phase inverter 44
Draw circuit.
First push-pull circuit includes I/O PMOS device P2 and I/O NMOS device N4.Second push-pull circuit includes I/O
PMOS device P5 and primary NMOS device N5.Third push-pull circuit includes I/O PMOS device P6 and I/O NMOS device N6.Electricity
Flat deviator 143 can also include the second phase inverter 42 and primary NMOS device N2.Although push-pull circuit is shown as having string
Join the PMOS and NMOS device of connection, but this is merely to illustrate that without proposing any restrictions to the scope of the present disclosure.?
In alternate embodiment, push-pull circuit may include other embodiments, the bipolar transistor being such as connected in series.
In the case where PLL signal IN is height in first voltage domain, phase inverter 42 exports the low-voltage of reverse phase, and former
Raw NMOS device N2 due to its with thin gate oxide fast conducting.For example, primary NMOS device can have 28
It is lower than 2nm, the preferably shorter than SiO of 1.8nm in nanometer technology2Gate oxide.In contrast, I/O MOS device can have
SiO2Gate oxide is higher than 2nm, preferably higher than 2.5nm in 28nm technique.Because the grid of PMOS device P2 receives the
High voltage in one voltage domain, so therefore PMOS device P2 is turned off.On the other hand, NMOS device N4 is connected, so that first
M signal is provided to the grid of the first phase inverter 44 and I/O NMOS device N6 from GND.Due to first M signal be it is low,
So I/O NMOS device N6 ends.Reverse phase high voltage in second voltage domain is output to I/O NMOS device by the first phase inverter 44
The source electrode of part N6 and the grid of I/O PMOS device P5.
Reverse phase high voltage closes I/O PMOS device P5, and the grid of I/O PMOS device P6 passes through the original having been turned on
Raw NMOS device N5 receives low-voltage.Therefore I/O PMOS device P6 is connected.On the other hand, since I/O NMOS device N6 is cut
Only, so level shifter 143 provides the high voltage in second voltage domain at node OUT.
In the case where PLL signal IN is low in first voltage domain, phase inverter 42 exports the high voltage of reverse phase, and former
Raw NMOS device N2 with thin gate oxide due to quickly ending.Because the grid of PMOS device P2 is connected to GND,
So PMOS device P2 is switched on.On the other hand, NMOS device N4 is turned off.In the case where PMOS device P2 conducting, first
M signal is supplied to the grid of the first phase inverter 44 and I/O NMOS device N6 from power voltage line Vddh.First M signal
It is high in second voltage domain, and the first phase inverter 44 is to the source electrode of I/O PMOS device P6 and the grid of I/O PMOS device P5
The low-voltage of pole output reverse phase.
I/O PMOS device P5 is connected in the low-voltage of reverse phase, and the grid of I/O PMOS device P6 is connected to supply voltage
Line Vddh.Therefore I/O PMOS device P6 is turned off.On the other hand, it is applied among the first of the grid of I/O NMOS device N6
Signal is high in second voltage domain, and therefore I/O NMOS device N6 is connected.In this case, level shifter 143
Low-voltage is provided at node OUT.
When PLL signal IN is low and high two kinds, the potential of the source electrode and drain electrode of I/O NMOS device N6 is basic
It is identical, because of the voltage follow I/O NMOS device N6 at node OUT.Which reduce competitions, and improve service speed.
In order to which the competition being further reduced between equipment is to mitigate turning problem, in some embodiments, equipment is selected
Relative size.For example, the grid length of I/O NMOS device N4 is designed to the grid length greater than I/O PMOS device P2.?
In one example, the grid length of I/O NMOS device N4 is at least twice of the grid length of I/O PMOS device P2, so that
All electric currents can be absorbed in I/O NMOS device N4, even if I/O NMOS device N4 and I/O PMOS device P2 is connected.Separately
Outside, complete depletion of silicon-on-insulator (FDSOI) technique can be used for the level shifter 143 of Fig. 4, allow to as I/O
Reverse bias is arranged in PMOS device P2.This allows the I/O PMOS device P2 in the case where input signal IN is high to close more,
To reduce the competition between I/O NMOS device N4 and I/O PMOS device P2.
By this method, reduce the turning problem of traditional level shifter, and improve the operation of level shifter 143
Speed.For example, level shifter 143 can be operated with the speed higher than 1GHz.Moreover, in order to avoid turning problem, this implementation
Transistor in example does not need to be configured to have very big ratio, so as to be suitably designed transistor and can save
Save the area of level shifter 143.In the case where inputting IN is height in first voltage domain, the output of level shifter 143
It is pulled to Vddh, because the source electrode of NMOS and PMOS device N6 and P6 are all connected to Vddh.Therefore, the embodiment is other excellent
Point is since there is no turning problem, so it supports biggish shift range.
Although this is merely to illustrate that it is appreciated that embodiment of the disclosure is reference operation speed to describe
Without proposing any restrictions to the scope of the present disclosure.In alternative embodiments, the service speed of level shifter 143 can be up to
3GHz。
Fig. 5 shows the variant of the level shifter in Fig. 4.Level shifter 144 is similar to the level shifter of Fig. 4
143, the difference is that I/O of the primary NMOS device N3 for I/O the NMOS device N7 and Fig. 5 being connected in series instead of Fig. 4
NMOS device N4.The series connection I/O NMOS device N7 and primary NMOS device N3 of Fig. 5 similarly acts as the I/O being connected in series
The primary NMOS device N3 of NMOS device N7 and Fig. 3.Pass through the I/O NMOS device N3 and primary NMOS device with series connection
N7 can be than level for example, level shifter 144 can be with instead of the level shifter 144 of I/O NMOS device N4, Fig. 5
The speed of 3.3GHz operates.
Fig. 6 shows level shifter 145 according to another embodiment of the present disclosure.Level shifter 145 includes coupling
The first push-pull circuit between power voltage line Vddh and GND is coupled to the first phase inverter 44 of the first push-pull circuit, coupling
The second push-pull circuit between power voltage line Vddh and GND and it is connected to power voltage line Vddh and the first phase inverter 44
Output between third push-pull circuit.
First push-pull circuit includes I/O PMOS device P2 and I/O NMOS device N4.Second push-pull circuit includes I/O
PMOS device P5 and primary NMOS device N5.Third push-pull circuit includes I/O PMOS device P6 and I/O NMOS device N6.Electricity
Flat deviator 143 can also include primary PMOS device P11, switch S2, the second phase inverter 42 and primary NMOS device N2.Although
Push-pull circuit is shown as with the PMOS and NMOS device being connected in series, but this is merely to illustrate that without to the disclosure
Range propose any restrictions.In alternative embodiments, push-pull circuit may include other embodiments, such as be connected in series
Bipolar transistor.
In the case where PLL signal IN is height in first voltage domain, phase inverter 42 exports the low-voltage of reverse phase, and former
Raw NMOS device N2 due to its with thin gate oxide fast conducting.For example, primary NMOS device has SiO2Grid
Oxide skin(coating) is lower than 2nm, preferably shorter than 1.8nm.In contrast, I/O MOS device may have 2nm or more, preferably
The SiO of 2.5nm or more2Gate oxide level.Since the grid of primary PMOS device P11 is connected to GND, so switch S2 is led
It is logical, and the grid of I/O PMOS device P2 is connected to the power voltage line (Vdd1) in first voltage domain, leads to primary PMOS
Device P11 is conductive.Switch S2 can be any device sufficiently rapidly turned on and off, not reduce level shifter 145
Service speed.
Therefore PMOS device P2 is turned off, because the grid of PMOS device P2 receives the high voltage in first voltage domain.Separately
On the one hand, NMOS device N4 is connected, so that first M signal is provided to the first phase inverter 44 and I/O NMOS device from GND
The grid of N6.Since first M signal is low, so I/O NMOS device N6 ends.First phase inverter 44 is by second voltage domain
In reverse phase high voltage be output to the source electrode of I/O NMOS device N6 and the grid of I/O PMOS device P5.
Reverse phase high voltage closes I/O PMOS device P5, and the grid of I/O PMOS device P6 passes through the primary of conducting
NMOS device N5 receives low-voltage.Therefore I/O PMOS device P6 is connected.On the other hand, since I/O NMOS device N6 ends,
So level shifter 143 provides the high voltage in second voltage domain at node OUT.
In the case where PLL signal IN is low in first voltage domain, phase inverter 42 exports the high voltage of reverse phase, and former
Raw NMOS device N2 with thin gate oxide due to quickly ending.Since the grid of PMOS device P2 is connected to GND, institute
With switch S2 shutdown, PMOS device P2 conducting.On the other hand, NMOS device N4 is turned off.The case where PMOS device P2 is connected
Under, first M signal is supplied to the grid of the first phase inverter 44 and I/O NMOS device N6 from power voltage line Vddh.First
M signal is high in second voltage domain, and the first phase inverter 44 is to the source electrode and I/O PMOS device of I/O PMOS device P6
The low-voltage of the grid output reverse phase of part P5.
I/O PMOS device P5 is connected in the low-voltage of reverse phase, and the grid of I/O PMOS device P6 is connected to supply voltage
Line Vddh.Therefore I/O PMOS device P6 is turned off.On the other hand, it is applied among the first of the grid of I/O NMOS device N6
Signal is high in second voltage domain, and therefore I/O NMOS device N6 is connected.In this case, level shifter 143
Low-voltage is provided at node OUT.
When PLL signal IN is low and high two kinds, the potential of the source electrode and drain electrode of I/O NMOS device N6 is basic
It is identical, because of the voltage follow I/O NMOS device N6 at node OUT.Which reduce competitions, and improve service speed.
Contention in order to be further reduced between equipment can design the size of equipment to mitigate turning problem.For example, I/
The grid length of O NMOS device N4 is designed to the grid length greater than I/O PMOS device P2.In one example, I/O
The grid length of NMOS device N4 is at least twice of the grid length of I/O PMOS device P2, so that I/O NMOS device N4 can
To absorb all electric currents, even if I/O NMOS device N4 and I/O PMOS device P2 is connected.
In such embodiments, the turning problem of conventional level deviator is at least partly improved, and level
The service speed of deviator 143 increases.For example, level shifter 143 can be operated with the speed higher than 1GHz.Moreover, in order to
Turning problem is avoided, the transistor in the present embodiment does not need to be configured to have very big ratio, so as to suitably
Design transistor and the area that level shifter 143 can be saved.In the case where inputting IN is height in first voltage domain,
The output of level shifter 143 is pulled to Vddh, because the source electrode of NMOS device N and PMOS device P6 are all connected to Vddh.Cause
This, the other advantage of the embodiment is can to support biggish deviation range, because turning problem is not present.Although with reference to behaviour
Embodiment of the disclosure is described as speed, but this is merely to illustrate that, without proposing any limit to the scope of the present disclosure
System.In alternative embodiments, the service speed of level shifter 143 can be up to 2.5GHz.
The variant of level shifter in Fig. 7 explanatory diagram 6.Level shifter 146 is similar to the level shifter 145 of Fig. 6,
The difference is that the I/O NMOS device N7 of the serial connection of Fig. 7 and primary NMOS device N3 replaces the I/O NMOS device of Fig. 6
Part N4.The I/O that the I/O NMOS device N7 of the series connection of Fig. 7 and primary NMOS device N3 similarly operates to be connected in series
The primary NMOS device N3 of NMOS device N7 and Fig. 6.Pass through the I/O NMOS device N3 and primary NMOS device with series connection
N7 instead of I/O NMOS device N4, Fig. 7 level shifter 146 can the level shifter 145 than Fig. 6 quickly operate.
Hereinafter, some sample implementations of the disclosure will be listed.
In some embodiments, a kind of device is provided.The device includes the first push-pull circuit, the first phase inverter, second
Push-pull circuit and third push-pull circuit.First push-pull circuit can be operated to receive input signal and the offer in first voltage domain
First M signal in second voltage domain.Second voltage domain is different from first voltage domain.First phase inverter can be operated with base
The inversion signal in second voltage domain is provided in first M signal.Second push-pull circuit can operate with based on input signal and
At least one of inversion signal provides the second M signal in second voltage domain.Third push-pull circuit can be operated to be based on
At least one of first M signal and second M signal provide output voltage signal, and output voltage signal follows reverse phase to believe
Number.
In some embodiments, first crystal pipe unit includes I/O PMOS device, and second transistor unit includes
I/O NMOS device.
In some embodiments, third push-pull circuit includes third transistor unit and the 4th transistor unit.Third is brilliant
Body pipe unit includes the third control terminal and third current path for receiving second M signal.4th transistor unit packet
Include the 4th control terminal for receiving first M signal and the floating ginseng including output node and for receiving inversion signal
Examine the 4th current path of terminal.Third current path and the 4th current path are coupled in series in power voltage line and the first reverse phase
Between device, third transistor unit and the 4th transistor unit can be operated to provide output voltage signal at output node.
In some embodiments, third transistor unit includes I/O PMOS device, and the 4th transistor unit includes I/O
NMOS device.
In some embodiments, the second push-pull circuit includes the 5th transistor unit and the 6th transistor unit.5th is brilliant
Body pipe unit includes the 5th control terminal and the 5th current path for receiving inversion signal.6th transistor unit includes using
In the 6th control terminal and the 6th current path that receive input signal.5th transistor unit and the series connection of the 6th transistor unit
It is coupled between power voltage line and reference voltage line.5th transistor unit and the 6th transistor unit can be operated the 5th
Second M signal is provided at the node between current path and the 6th current path.
In some embodiments, the 5th transistor unit includes I/O PMOS device, and the 6th transistor unit includes
Primary NMOS device.
In some embodiments, which further includes the second phase inverter and the 7th transistor unit.Second phase inverter can be grasped
Make will input and single be converted into rp input signal.7th transistor unit includes the 7 for receiving rp input signal
The 7th current path between control terminal and the control terminal and reference voltage line that are coupled in first crystal pipe unit.
In some embodiments, the 7th transistor unit includes primary NMOS device.
In some embodiments, the thickness of the gate oxide level of primary NMOS device is lower than 2nm, and I/O NMOS device
The thickness of the gate oxide level of part is higher than 2nm.
In some embodiments, second transistor unit includes the primary NMOS and I/O NMOS device of series coupled.It is former
The control terminal of raw NMOS device can be used to receive input signal and I/O NMOS device is switched on.
In some embodiments, the grid length of second transistor unit is greater than the grid length of first crystal pipe unit.
In some embodiments, the grid length of second transistor unit than first crystal pipe unit grid length greatly extremely
It is twice few.
In some embodiments, which is the level shifter operated with the speed greater than 2GHz.
In some embodiments, a kind of electronic system is provided.Electronic system includes phaselocked loop (PLL) and is coupled to PLL
Device.The device includes the first push-pull circuit, the first phase inverter, the second push-pull circuit and third push-pull circuit.First recommends
Circuit can be operated to receive in the input signal in first voltage domain and provide the first M signal in second voltage domain.
Second voltage domain is different from first voltage domain.First phase inverter can be operated to be provided based on first M signal in second voltage domain
In inversion signal.Second push-pull circuit can be operated to be provided based at least one of input signal and inversion signal second
Second M signal in voltage domain.Third push-pull circuit can be operated based in first M signal and second M signal
At least one provides output voltage signal.Output voltage signal follows inversion signal.
In some embodiments, the first push-pull circuit includes first crystal pipe unit and second transistor unit.First is brilliant
Body pipe unit includes the first control terminal and the first current path for receiving input signal.Second transistor unit includes using
In the second control terminal and the second current path that receive input signal.First current path and the second current path series coupled
Between the reference voltage line and power voltage line in second voltage domain.First crystal pipe unit and second transistor unit can operate
To provide first M signal at the intermediate node between the first current path and the second current path.
In some embodiments, first crystal pipe unit includes I/O PMOS device, and second transistor unit includes
I/O NMOS device.
In some embodiments, third push-pull circuit includes third transistor unit and the 4th transistor unit.Third is brilliant
Body pipe unit includes the third control terminal and third current path for receiving second M signal.4th transistor unit packet
Include the 4th control terminal for receiving first M signal and the floating ginseng including output node and for receiving inversion signal
Examine the 4th current path of terminal.Third current path and the 4th current path are coupled in series in power voltage line and the first reverse phase
Between device, third transistor unit and the 4th transistor unit can be operated to provide output voltage signal at output node.
In some embodiments, third transistor unit includes I/O PMOS device, and the 4th transistor unit includes
I/O NMOS device.
In some embodiments, the second push-pull circuit includes the 5th transistor unit and the 6th transistor unit.5th is brilliant
Body pipe unit includes the 5th control terminal and the 5th current path for receiving inversion signal.6th transistor unit includes using
In the 6th control terminal and the 6th current path that receive input signal.5th transistor unit and the series connection of the 6th transistor unit
It is coupled between power voltage line and reference voltage line.5th transistor unit and the 6th transistor unit can be operated the 5th
Second M signal is provided at the node between current path and the 6th current path.
In some embodiments, the 5th transistor unit includes I/O PMOS device, and the 6th transistor unit includes
Primary NMOS device.
In some embodiments, which further includes the second phase inverter and the 7th transistor unit.Second phase inverter can be grasped
Make will input and single be converted into rp input signal.7th transistor unit includes the 7 for receiving rp input signal
The 7th current path between control terminal and the control terminal and reference voltage line that are coupled in first crystal pipe unit.
In some embodiments, the 7th transistor unit includes primary NMOS device.
In some embodiments, the thickness of the gate oxide level of primary NMOS device is lower than 2nm, and I/O NMOS device
The thickness of the gate oxide level of part is higher than 2nm.
In some embodiments, second transistor unit includes the primary NMOS and I/O NMOS device of series coupled.It is former
The control terminal of raw NMOS device can be used to receive input signal and I/O NMOS device is switched on.
In some embodiments, the grid length of second transistor unit is greater than the grid length of first crystal pipe unit.
In some embodiments, the grid length of second transistor unit than first crystal pipe unit grid length greatly extremely
It is twice few.
In some embodiments, which is the level shifter operated with the speed greater than 2GHz.
The various embodiments of the disclosure are described above.Explanation above is merely to illustrate without the model to the disclosure
Enclose proposition any restrictions.In the case where not departing from the scope and spirit of various embodiments as shown, for this field skill
Many modifications and changes are obvious for art personnel.The selection of term as used herein is intended to best explain each
The principle of embodiment, the improvement of practical application or in the market technology, or make those skilled in the art it will be appreciated that
Embodiment disclosed herein.
Claims (23)
1. a kind of device (143,144,145,146), comprising:
First push-pull circuit (P2, N4) is operable as receiving the input signal in first voltage domain, and provides in second voltage
First M signal in domain, the second voltage domain are different from the first voltage domain；
First phase inverter (44) is operable to the first M signal and provides the reverse phase letter in the second voltage domain
Number；
Second push-pull circuit (N5, P5) is operable at least one of the input signal and the inversion signal and mentions
For the second M signal in the second voltage domain；And
Third push-pull circuit (P6, N6) is operable in the first M signal and the second M signal extremely
A few offer output voltage signal, the output voltage signal follow the inversion signal.
2. the apparatus according to claim 1, wherein first push-pull circuit (P2, N4) includes first crystal pipe unit
(P2) and second transistor unit (N4)；
The first crystal pipe unit includes the first control terminal and the first current path for receiving the input signal；
The second transistor unit includes the second control terminal and the second current path for receiving the input signal；
First current path and second current path are coupled in series in the reference voltage line in the second voltage domain
(GND) between power voltage line (Vddh)；
The first crystal pipe unit and the second transistor unit (P2, N4) be operable as in first current path and
Intermediate node between second current path provides the first M signal.
3. the apparatus of claim 2, wherein the first transistor unit includes I/O PMOS device, and second
Transistor unit includes I/O NMOS device.
4. the apparatus according to claim 1, wherein the third push-pull circuit includes third transistor unit (P6) and
Four transistor units (N6)；
The third transistor unit includes the third control terminal and third electric current road for receiving the second M signal
Diameter；
4th transistor unit include the 4th control terminal for receiving the first M signal and including output node and
For receiving the 4th current path of the floating reference terminal of the inversion signal；
In power voltage line and first reverse phase described in the third current path and the 4th current path series coupled
Between device, the third transistor unit and the 4th transistor unit can be operated to provide output voltage at output node
Signal.
5. device according to claim 4, wherein the third transistor unit includes I/O PMOS device, the 4th crystal
Pipe unit includes I/O NMOS device.
6. the apparatus of claim 2, wherein second push-pull circuit includes the 5th transistor unit (P5) and the
Six transistor units (N5)；
5th transistor unit includes the 5th control terminal and the 5th current path for receiving the inversion signal；
6th transistor unit includes the 6th control terminal and the 6th current path for receiving the input signal；
5th transistor unit and the 6th transistor unit are coupled in series in the power voltage line and the reference
Between pressure-wire；And
5th transistor unit and the 6th transistor unit can be operated in the 5th current path and described
The second M signal is provided at the node between six current paths.
7. device according to claim 6, wherein the 5th transistor unit includes I/O PMOS device, and described
6th transistor unit includes primary NMOS device.
8. device according to claim 7, further includes:
Second phase inverter (42) can be operated so that the input signal is converted into rp input signal；
7th transistor unit including the 7th control terminal for receiving the rp input signal and is coupled in described first
The 7th current path between the control terminal and the reference voltage line of transistor unit.
9. device according to claim 8, wherein the 7th transistor unit includes primary NMOS device.
10. device according to claim 9, wherein the thickness of the gate oxide level of the primary NMOS device is lower than
2nm, and the thickness of the gate oxide level of the I/O NMOS device is higher than 2nm.
11. the apparatus of claim 2, wherein the second transistor unit include series coupled primary NMOS and
I/O NMOS device, the control terminal of the primary NMOS device can be used to receive the input signal and the I/O
NMOS device is switched on.
12. device according to claim 11, wherein the grid length of the second transistor unit is greater than described first
The grid length of transistor unit.
13. device according to claim 12, wherein the grid length of the second transistor unit is more brilliant than described first
The big at least twice of the grid length of body pipe unit.
14. the apparatus according to claim 1, wherein described device is the level deviation operated with the speed greater than 2GHz
Device.
15. a kind of electronic system, including phaselocked loop (PLL) and it is coupled to the device of PLL, described device includes:
First push-pull circuit is operable as receiving in the input signal in first voltage domain and providing in second voltage domain
First M signal, the second voltage domain are different from the first voltage domain；
First phase inverter is operable to the first M signal and provides the inversion signal in the second voltage domain；
Second push-pull circuit is operable at least one of the input signal and the inversion signal and provides described
Second M signal in second voltage domain；And
Third push-pull circuit is operable at least one of the first M signal and the second M signal and mentions
For output voltage signal, the output voltage signal follows inversion signal.
16. electronic system according to claim 15, wherein first push-pull circuit include first crystal pipe unit and
Second transistor unit；
The first crystal pipe unit includes the first control terminal and the first current path for receiving the input signal；
The second transistor unit includes the second control terminal and the second current path for receiving the input signal；
First current path and second current path be coupled in series in the second voltage domain reference voltage line and
Between power voltage line；
The first crystal pipe unit and the second transistor unit are operable as in first current path and described
The first M signal is provided at the intermediate node between two current paths.
17. electronic system according to claim 15, wherein the first transistor unit includes I/O PMOS device, and
And the second transistor unit includes I/O NMOS device.
18. electronic system according to claim 15, wherein the third push-pull circuit include third transistor unit and
4th transistor unit；
The third transistor unit includes the third control terminal and third electric current road for receiving the second M signal
Diameter；
4th transistor unit includes the 4th control terminal for receiving the first M signal and saves including output
4th current path of point and the floating reference terminal for receiving the inversion signal；
The third current path and the 4th current path are coupled in series in the power voltage line and first reverse phase
Between device, described in the third transistor unit and the 4th transistor unit are operable as providing at the output node
Output voltage signal.
19. electronic system according to claim 18, wherein the third transistor unit includes I/O PMOS device, and
And the 4th transistor unit includes I/O NMOS device.
20. electronic system according to claim 16, wherein second push-pull circuit include the 5th transistor unit and
6th transistor unit；
5th transistor unit includes the 5th control terminal and the 5th current path for receiving the inversion signal；
6th transistor unit includes the 6th control terminal and the 6th current path for receiving the input signal；
5th transistor unit and the 6th transistor unit are coupled in series in the power voltage line and the reference
Between pressure-wire；
5th transistor unit and the 6th transistor unit are operable as in the 5th current path and described
The second M signal is provided at the node between six current paths.
21. electronic system according to claim 20, wherein the 5th transistor unit includes I/O PMOS device, and
And the 6th transistor unit includes primary NMOS device.
22. electronic system according to claim 20, further includes:
Second transistor unit, the primary NMOS and I/O NMOS device including series coupled, the control of the primary NMOS device
Terminal processed can be used to receive the input signal and the I/O NMOS device is switched on.
23. electronic system according to claim 16, wherein the grid length of the second transistor unit is greater than described
The grid length of first crystal pipe unit.
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| CN201810034946.8A CN110048707A (en) | 2018-01-15 | 2018-01-15 | High speed and wide scope level shifter |
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| CN201810034946.8A CN110048707A (en) | 2018-01-15 | 2018-01-15 | High speed and wide scope level shifter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620577A (en) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | FDSOI structure-based level conversion unit circuit and layout design method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1046821A (en) * | 1989-04-26 | 1990-11-07 | 国际商业机器公司 | The word-line boosting circuit that is used for the complementary MOSFET dynamic memor |
| EP1901430A2 (en) * | 2006-08-23 | 2008-03-19 | STMicroelectronics Pvt. Ltd. | High speed level shifter |
| US20080084231A1 (en) * | 2006-10-05 | 2008-04-10 | International Business Machines Corporation | Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits |
| US20080084237A1 (en) * | 2006-10-05 | 2008-04-10 | Derick Gardner Behrends | Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits |
| CN101222224A (en) * | 2006-12-04 | 2008-07-16 | 奇景光电股份有限公司 | Level shift circuit with voltage pulling and its voltage lifting circuit |
| CN103534949A (en) * | 2011-05-02 | 2014-01-22 | 美国亚德诺半导体公司 | System and method for level-shifting voltage signals using a dynamic level-shifting architecture |
| CN107534441A (en) * | 2015-02-12 | 2018-01-02 | 夸林克斯有限公司 | Level shifter |
-
2018
- 2018-01-15 CN CN201810034946.8A patent/CN110048707A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1046821A (en) * | 1989-04-26 | 1990-11-07 | 国际商业机器公司 | The word-line boosting circuit that is used for the complementary MOSFET dynamic memor |
| EP1901430A2 (en) * | 2006-08-23 | 2008-03-19 | STMicroelectronics Pvt. Ltd. | High speed level shifter |
| US20080084231A1 (en) * | 2006-10-05 | 2008-04-10 | International Business Machines Corporation | Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits |
| US20080084237A1 (en) * | 2006-10-05 | 2008-04-10 | Derick Gardner Behrends | Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits |
| CN101222224A (en) * | 2006-12-04 | 2008-07-16 | 奇景光电股份有限公司 | Level shift circuit with voltage pulling and its voltage lifting circuit |
| CN103534949A (en) * | 2011-05-02 | 2014-01-22 | 美国亚德诺半导体公司 | System and method for level-shifting voltage signals using a dynamic level-shifting architecture |
| CN107534441A (en) * | 2015-02-12 | 2018-01-02 | 夸林克斯有限公司 | Level shifter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620577A (en) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | FDSOI structure-based level conversion unit circuit and layout design method |
| CN110620577B (en) * | 2019-10-12 | 2023-06-02 | 上海华力微电子有限公司 | Level conversion unit circuit based on FDSOI structure and layout design method |
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