CN103199833B - The control circuit of IGBT switching speed and method in PDP output driving circuit - Google Patents

The control circuit of IGBT switching speed and method in PDP output driving circuit Download PDF

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Publication number
CN103199833B
CN103199833B CN201310098285.2A CN201310098285A CN103199833B CN 103199833 B CN103199833 B CN 103199833B CN 201310098285 A CN201310098285 A CN 201310098285A CN 103199833 B CN103199833 B CN 103199833B
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pmos
output
circuit module
igbt pipe
signal
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CN103199833A (en
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黄光佐
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Sichuan Changhong Electric Co Ltd
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Sichuan Changhong Electric Co Ltd
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Abstract

The invention discloses control circuit and the method for IGBT switching speed in PDP output driving circuit, this circuit comprises: state control signal processing circuit module, for the logical operation by chip status control signal; One IGBT pipe level shift circuit drive signal circuit, realizes the output signal of state control signal processing circuit module, the first drive singal to the control of an IGBT pipe switching speed in output driving circuit; 2nd IGBT pipe drive signal circuit module, realizes the output signal of state control signal processing circuit module and the second drive singal to the control of the 2nd IGBT2 switching speed in output driving circuit.Use the present invention can IGBT pipe opening time in control PDP output driving circuit, only remove open and close IGBT in the relatively fast speed of address period, thus meet immediate addressing and Jiang Di ⊿ I/ ⊿ T, thus realize the object of reduction electromagnetic radiation.

Description

The control circuit of IGBT switching speed and method in PDP output driving circuit
Technical field
The present invention relates to PDP(plasma display panel) display screen line Driving technique, be specifically related in a kind of control PDP line driving chip as igbts such as the IGBT(of device for power switching) switching frequency to reduce control circuit and the method for electromagnetic radiation.
Background technology
IGBT has easily driving and with higher switching frequency process big current and high-tension feature, can be widely used in PDP display screen line Driving technique.
According to the displaying principle of PDP, its course of work comprises interlock circuit and wipes the electric charge that PDP shields on electric capacity, addressing (writing new data), several processes such as display.And the conversion of IBGT pipe switch state in the line driving chip that these processes all must be shielded by PDP realizes, its process realized is then the process of PDP line driving chip operating state change, namely the output state of chip have passed through high resistant output, full high level output, full low level output, follows the process of input data variation.Because the line driving chip quantity on PDP screen is more, for the display screen of 1366*768 resolution, then need 768 high-voltage output circuits, if by now widely used row cutting mode, namely each chip has 96 road high-voltage output circuits, then need 8 line driving chips.According to IGBT(insulated gate bipolar transistor) switching characteristic, if do not take measures, larger punchthrough current will be produced to entirely low or entirely low by overall height in the change procedure of overall height on 768 roads simultaneously, in high voltage source, produce Ju great ⊿ I/ ⊿ T by causing like this, fierce curent change will produce larger electromagnetic radiation.In fact, the switching speed of IGBT only requires switching speed faster in addressing (the IBGT pipe in the high-voltage output circuit of address period Jin You mono-road carries out open and close state-transition) period, and not high to the switching speed requirements of IGBT at other times, namely do not need higher speed to remove the IGBT pipe of opening or closing in high-voltage output circuit.
Summary of the invention
What produce to make curent change reaches minimum compared with electromagnetic radiation, the invention provides the circuit of IGBT switching speed under different conditions in a kind of control PDP output driving circuit, comprise state control signal processing circuit module, one IGBT pipe level shift circuit drive signal circuit module, the 2nd IGBT pipe drive signal circuit module.
State control signal processing circuit module, for the logical operation of chip status control signal;
One IGBT pipe level shift circuit drive signal circuit module, realizes the output of state control signal processing circuit module and the first drive singal to the control of an IGBT pipe switching speed in output driving circuit;
2nd IGBT pipe drive signal circuit module, realizes the output signal of state control signal processing circuit module and the second drive singal to the control of the 2nd IGBT pipe switching speed in output driving circuit;
The output signal of the one IGBT pipe level shift circuit drive signal circuit module becomes large in address period, and the non-addressed phase diminishes; The output signal of the 2nd IGBT pipe drive signal circuit module becomes large in address period, and the non-addressed phase diminishes.
The present invention controls the on off state of the PMOS used in parallel, makes the ratio of PMOS channel width/communication length in parallel during address period become large, increases driving current signal, shorten the IGBT opening time; In the non-addressed phase, reduce the ratio of PMOS in parallel channel width/communication length raceway groove, reduce driving current signal, extend the IGBT opening time.
Use the present invention, circuit can be made when different operating states, change the drive current driving high-voltage output circuit, change the opening time, only remove open and close IGBT in the relatively fast speed of address period, thus meet immediate addressing and Jiang Di ⊿ I/ ⊿ T, thus realize the object reducing electromagnetic radiation.
Accompanying drawing explanation
Fig. 1 is PDP output driving circuit figure in prior art.
Fig. 2 is prior art the one IGBT pipe level shift circuit drive signal circuit module map.
Fig. 3 is prior art the 2nd IGBT pipe drive signal circuit figure.
Fig. 4 is state control signal processing circuit module of the present invention.
Fig. 5 is the present invention the one IGBT pipe level shift circuit drive signal circuit module.
Fig. 6 is the present invention the 2nd IGBT pipe drive signal circuit module.
Embodiment
In this invention:
OC1 represents the first chip status control signal;
OC2 represents the second chip status control signal;
DATA1 represents the first drive singal;
DATA2 represents the second drive singal;
OC12 represents the output signal of state control signal processing circuit module;
Character " L " represents low level;
Character " H " represents high level.
Fig. 1 is typical output driving circuit figure in PDP prior art, by the output state of the transformation control lines driving chip of two IGBT pipe open and close states, the IGBT of figure middle and upper part is called an IGBT pipe herein, the IGBT of figure middle and lower part is called the 2nd IGBT pipe.In prior art, DATA1 is DO1, DO2 signal through circuit conversion shown in Fig. 2, DATA2 through Fig. 3 logical transition circuit conversion be DO3 signal.DO1, DO2, DO3 act on IGBT pipe in Fig. 1.
According to the switching characteristic of IGBT, in the charge erasure of PDP, addressing (writing new data), several processes such as display, all high-voltage output circuits of PDP display can simultaneously by overall height to entirely low or entirely low to overall height, by producing larger punchthrough current in change procedure, produce Ju great ⊿ I/ ⊿ T like this by causing in high voltage source, fierce curent change will produce larger electromagnetic radiation.In fact, in line driving chip, the switching speed of IGBT only requires switching speed faster in addressing (the IBGT pipe in the high-voltage output circuit of address period Jin You mono-road carries out open and close state-transition) period, and it is not high to the switching speed requirements of IGBT at other times, if the switching speed of IGBT can be made to reduce in the non-addressed phase, the electromagnetic radiation that fierce curent change causes just greatly can be reduced.
In order to achieve the above object, the present invention proposes the circuit of the switching speed of IGBT in control PDP output driving circuit figure, it is divided into three modules: state control signal processing circuit module, an IGBT pipe level shift circuit drive signal circuit module, the 2nd IGBT pipe drive signal circuit module.Before illustrating various piece, be necessary to be described the relation in the present invention between each signal,
Be PDP line driving chip working state control signal OC1 shown in table 1, OC2 is to the state of a control of chip.
Address data OC1 OC2 Output state
X L L High-impedance state
X H L Complete low state
L H H Overall height state
L L H L, follows data variation
H L H H, follows data variation
Table 1
Table 2 is that other circuit of PDP line driving chip produce the relation table of DATA1, DATA2 control signal according to state control signal OC1, OC2 and address data.
Address data OC1 OC2 DATA1 DATA2
X L L L L
X H L L H
L H H H L
L L H H L
H L H L H
Table 2
Below various piece circuit diagram and principle are made an explanation respectively.
State control signal processing circuit module:
This module realizes the logical operation of chip status control signal OC1 and OC2: .After OC1 logical inversion with OC2 phase with obtain OC12, when OC1 be L, OC2 is H, enter addressed state.
As shown in Figure 4: comprise the first inverter INV1, the second inverter INV2, the first NAND gate NAND1; First chip status control signal OC1 is connected to the first NAND gate NAND1 mono-input after being connected with the first inverter INV1, the second chip status control signal OC2 is connected to another input of the first NAND gate NAND1; Second inverter INV2 input connects the first NAND gate NAND1 output, and output connects an IGBT pipe level shift circuit drive signal circuit module and the 2nd IGBT pipe drive signal circuit module.
One IGBT pipe level shift circuit drive signal circuit module:
This module realizes the output of state control signal processing circuit module and the first drive singal to the control of an IGBT pipe switching speed in output driving circuit.
As shown in Figure 5: a described IGBT pipe level shift circuit drive signal circuit module, by the 3rd inverter INV3, the second NAND gate NAND2, the first NMOS tube MNC1, the first PMOS MPC1, the second PMOS MPC2 pipe is formed; The output signal OC12 of described second NAND gate (NAND2) input difference connection status control signal processing circuit module and the first drive singal DATA1, output is connected to the grid of the second PMOS MPC2; The input of the 3rd inverter INV3 connects the first drive singal DATA1, and output is connected to the grid of the first NMOS tube MNC1 and the grid of the first PMOS MPC1; First PMOS MPC1 and the second PMOS MPC2 manages measure-alike, and both are in parallel, and the first PMOS MPC1 source electrode drains with the first NMOS tube MNC1 and is connected; The output of the 3rd inverter INV3 is a signal output part of a described IGBT pipe level shift circuit drive signal circuit module, PMOS (MPC1 in parallel, MPC2) source electrode of pipe is another signal output part of a described IGBT pipe level shift circuit drive signal circuit module, and the output signal of two signal output parts is respectively DO1, DO2.
Contrast known with prior art shown in Fig. 3, invention increases a PMOS, in parallel with former PMOS, both are measure-alike.DATA1 and OC12 carry out logical operation ( ) result be applied to the grid with newly-increased PMOS as new signal.
When OC1=L, OC2=H (during normal addressing), OC12=H; Now whether MPC2 pipe is opened and is depended on DATA1 signal, namely as DATA1=L to DATA1=H, MPC2 pipe, MPC1 pipe are opened simultaneously, be equivalent to add PMOS base width, the ratio of PMOS base width/base length becomes large, DO1, D02 drive current becomes large, an IGBT pipe transfer open state to rapidly.And when entering overall height state, (i.e. when OC1=H, OC2=H), OC12=L; MPC2 will enter closed condition, and now DO1 and DO2 only controls by DATA1, and now DATA1=H, and the ratio of the PMOS base width/base length DO1 drive current that diminishes diminishes.Thus when realizing entering overall height state, the driving force of DO1 signal reduces, and achieves the weak unlatching of pipe IGBT, reduces impulse current, i.e. Jian little ⊿ I/ ⊿ T, electromagnetic radiation when reducing from other states to overall height state variation.
2nd IGBT pipe drive signal circuit module:
This module realizes the output signal of state control signal processing circuit module and the second drive singal to the control of the 2nd IGBT pipe switching speed in output driving circuit.
As shown in Figure 6: this module is made up of the 3rd NAND gate NAND3, the 4th inverter INV4, the 5th inverter INV5, the second NMOS tube MNC2, the 3rd PMOS MPC3, the 4th PMOS MPC4; 4th inverter INV4 input connects the second drive singal DATA2, and output is connected to an input of the 3rd NAND gate NAND3, and the output signal OC12 of state control signal processing circuit module is connected to another input of the 3rd NAND gate NAND3; 3rd NAND gate NAND3 output connects the grid of the 4th PMOS MPC4; The input of the 5th inverter INV5 connects the second drive singal DATA2, and output connects the grid of the second NMOS tube MNC2 and the grid of the 3rd PMOS MPC3; 3rd PMOS MPC3 and the 4th PMOS MPC4 is measure-alike, and both are in parallel, and the 3rd PMOS MPC3 source electrode drains with the second NMOS tube MNC2 and is connected; As the signal output part of the 2nd IGBT pipe drive signal circuit module after 3rd PMOS MPC3, the 4th PMOS MPC4 sources connected in parallel, output signal as DO3.
Contrast known with Fig. 4, add a PMOS in parallel with former PMOS, both are measure-alike.DATA2 and OC12 is carried out logical operation ( ) result be that new signal is applied to the grid with newly-increased PMOS.
When OC1=L, OC2=H (during normal addressing), OC12=H; Now whether MPC4 pipe is opened and is depended on DATA2 signal, i.e. as DATA2=H (when needing the row of addressing addressed), MPC3 and MPC4 pipe is opened simultaneously, because PMOS is in parallel, be equivalent to add PMOS base width, the ratio of PMOS base width/base length becomes large, and ER effect is large, DO3 signal code becomes large, and the 2nd IGBT pipe is opened rapidly; And when enter entirely low (i.e. OC1=H, OC2=L) state time OC12=L; MPC4 will enter closed condition, now output signal DO3 only to control by DATA2, and now DATA2=H, the ratio of PMOS base width/base length diminishes, DO3 drive current is little, thus the weak unlatching of the 2nd IGBT pipe when realizing entering complete low state, namely subtract little ⊿ I/ ⊿ T, electromagnetic radiation when reducing from other states to complete low state variation.
In a word, the present invention utilizes the conducting principle of PMOS in parallel, achieves the control to IGBT switch transition speed in PDP output driving circuit, effectively reduces electromagnetic radiation.

Claims (4)

  1. In 1.PDP output driving circuit, the control circuit of IGBT switching speed, is characterized in that, comprises:
    State control signal processing circuit module, for the logical operation of chip status control signal;
    One IGBT pipe level shift circuit drive signal circuit module, realizes the output signal (OC12) of state control signal processing circuit module and the first drive singal (DATA1) to the control of an IGBT pipe switching speed in output driving circuit;
    2nd IGBT pipe drive signal circuit module, realizes the output signal (OC12) of state control signal processing circuit module and the second drive singal (DATA2) to the control of the 2nd IGBT pipe switching speed in output driving circuit;
    Described state control signal processing circuit module comprises the first inverter (INV1), the second inverter (INV2), the first NAND gate (NAND1); Be connected to the first NAND gate (NAND1) input after first chip status control signal (OC1) is connected with the first inverter (INV1), the second chip status control signal (OC2) is connected to the first NAND gate (NAND1) another input; Second inverter (INV2) input connects the first NAND gate (NAND1) output, and output connects an IGBT pipe level shift circuit drive signal circuit module and the 2nd IGBT pipe drive signal circuit module;
    A described IGBT pipe level shift circuit drive signal circuit module, by the 3rd inverter (INV3), the second NAND gate (NAND2), the first NMOS tube (MNC1), the first PMOS (MPC1), the second PMOS (MPC2) pipe is formed; The output signal (OC12) of described second NAND gate (NAND2) input difference connection status control signal processing circuit module and the first drive singal (DATA1), output is connected to the grid of the second PMOS (MPC2); The input of the 3rd inverter (INV3) connects the first drive singal (DATA1), and output is connected to the grid of the first NMOS tube (MNC1) and the grid of the first PMOS (MPC1); First PMOS (MPC1) is measure-alike with the second PMOS (MPC2), and both are in parallel, and the first PMOS (MPC1) source electrode drains with the first NMOS tube (MNC1) respectively with the source electrode of the second PMOS (MPC2) and is connected; The output of the 3rd inverter (INV3) is a signal output part of a described IGBT pipe level shift circuit drive signal circuit module, and the first PMOS (MPC1) in parallel and the source electrode of the second PMOS (MPC2) are another signal output part of a described IGBT pipe level shift circuit drive signal circuit module;
    Described 2nd IGBT pipe drive signal circuit module, is made up of the 3rd NAND gate (NAND3), the 4th inverter (INV4), the 5th inverter (INV5), the second NMOS tube (MNC2), the 3rd PMOS (MPC3), the 4th PMOS (MPC4); 4th inverter (INV4) input connects the second drive singal (DATA2), output is connected to an input of the 3rd NAND gate (NAND3), and the output signal (OC12) of state control signal processing circuit module is connected to another input of the 3rd NAND gate (NAND3); 3rd NAND gate (NAND3) output connects the grid of the 4th PMOS (MPC4); The input of the 5th inverter (INV5) connects the second drive singal (DATA2), and output connects the grid of the second NMOS tube (MNC2) and the grid of the 3rd PMOS (MPC3); 3rd PMOS (MPC3) is measure-alike with the 4th PMOS (MPC4), and both are in parallel, and the 3rd PMOS (MPC3) source electrode drains with the second NMOS tube (MNC2) respectively with the source electrode of the 4th PMOS (MPC4) and is connected; 3rd PMOS (MPC3) in parallel, the source electrode of the 4th PMOS (MPC4) are as the signal output part of the 2nd IGBT pipe drive signal circuit module.
  2. 2. a kind ofthe control method of the control circuit of IGBT switching speed in PDP output driving circuit as claimed in claim 1, it is characterized in that: the output signal (DO1, DO2) of an IGBT pipe level shift circuit drive signal circuit module becomes large in address period, and the non-addressed phase diminishes; The output signal (DO3) of the 2nd IGBT pipe drive signal circuit module becomes large in address period, and the non-addressed phase diminishes.
  3. 3. control method as claimed in claim 2, it is characterized in that: the second PMOS (MPC2) that the output signal (OC12) of using state control signal processing circuit module and the first drive singal (DATA1) realize in an IGBT pipe level shift circuit drive signal circuit module is opened in address period, and the non-addressed phase turns off.
  4. 4. control method as claimed in claim 3, it is characterized in that: the 4th PMOS (MPC4) that the output signal (OC12) of state control signal processing circuit module and the second drive singal (DATA2) realize the 2nd IGBT pipe drive signal circuit module is opened in address period, and the non-addressed phase turns off.
CN201310098285.2A 2013-03-26 2013-03-26 The control circuit of IGBT switching speed and method in PDP output driving circuit Expired - Fee Related CN103199833B (en)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106849923B (en) * 2016-12-23 2019-06-04 电子科技大学 A kind of IGBT drive circuit
CN107863912B (en) * 2017-11-27 2023-06-09 深圳市优必选科技有限公司 Steering engine and motor driving circuit thereof
CN110008524A (en) * 2019-03-13 2019-07-12 珠海博雅科技有限公司 With the method and large capacity chip of single type chip extension large capacity chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140201A (en) * 1990-04-02 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Gate drive circuit for insulated gate semiconductor device and flash controller using the circuit
CN201270500Y (en) * 2008-07-29 2009-07-08 南京华士电子科技有限公司 Novel IGBT driver
CN101814266A (en) * 2010-04-27 2010-08-25 四川长虹电器股份有限公司 Method for driving IGBT in PDP display screen line driving chip

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140201A (en) * 1990-04-02 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Gate drive circuit for insulated gate semiconductor device and flash controller using the circuit
CN201270500Y (en) * 2008-07-29 2009-07-08 南京华士电子科技有限公司 Novel IGBT driver
CN101814266A (en) * 2010-04-27 2010-08-25 四川长虹电器股份有限公司 Method for driving IGBT in PDP display screen line driving chip

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