CN207490899U - Level shifting circuit and data transmission device - Google Patents
Level shifting circuit and data transmission device Download PDFInfo
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- CN207490899U CN207490899U CN201721248408.6U CN201721248408U CN207490899U CN 207490899 U CN207490899 U CN 207490899U CN 201721248408 U CN201721248408 U CN 201721248408U CN 207490899 U CN207490899 U CN 207490899U
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Abstract
The utility model discloses a kind of level shifting circuit and data transmission devices.Wherein, which includes：The first transistor, second transistor, third transistor, the 4th transistor；Conducting structure is connected between third transistor and analog circuit power supply AVSS, is controlled for the reverse signal according to output terminal output signal whether the circuit of the first transistor, third transistor to AVSS is connected；Duty cycle adjustment structure is connected between the 4th transistor and analog circuit power supply AVSS, for according to the signal that output terminal exports by the duty cycle adjustment of level shifting circuit to predetermined duty ratio.By the utility model, solves level conversion process high speed and the technical issues of low-power consumption can not have both.
Description
Technical field
The utility model is related to electronic technology fields, are filled in particular to a kind of level shifting circuit and data transmission
It puts.
Background technology
In design of electronic circuits of new generation, with the introducing of low logic voltage, usually there is input/output in internal system
The problem of logic is uncoordinated, the different module and required voltage of I/O interface is different cannot directly carry out signal exchange, institute
To design level translator, it is widely applied between varying level module.Different modules requires not level translator
Together, main performance index is speed and power consumption.And the power consumption that common high-speed level shifter needs is big, and low-power consumption level turns
Change and be not well positioned to meet the needs of high speed.
Fig. 1 is according to a kind of schematic diagram of common level shifting circuit of the relevant technologies, as shown in Figure 1, it uses intersection
Manifold type (cross coupled) structure, since there is latch structure (latch) in top, so the variation per secondary input end state
The state that will have very big driving force could change latch structure (latch) causes conversion speed relatively slow, it is impossible to be used in
In high-speed circuits.Fig. 2 is the schematic diagram that level shifting circuit is commonly used according to the another kind of the relevant technologies, as shown in Fig. 2, it makes
With electric current mirror (current mirror) structure, without latch structure (latch) latch output state, so output
Stronger driving force is not needed to during the low and high level conversion of end, fireballing purpose can be reached, but deposited during structure conducting
In power supply to the access on ground, so larger quiescent dissipation can be generated.
The technical issues of can not being had both for above-mentioned level conversion process high speed and low-power consumption, not yet proposes effective at present
Solution.
Utility model content
The utility model embodiment provides a kind of level shifting circuit and data transmission device, is turned at least solving level
Change process high speed and the technical issues of low-power consumption can not annex.
According to the one side of the utility model embodiment, a kind of level shifting circuit is provided, including：First crystal
Pipe, including source electrode, drain electrode and grid, the source electrode of the first transistor is connected to analog circuit power supply AVDD, and described first is brilliant
The grid of body pipe is connected with the first transistor drain electrode；Second transistor, including source electrode, drain electrode and grid, described second is brilliant
The source electrode of body pipe is connected to the AVDD, and the second transistor grid is connected with the first crystal tube grid；Third crystal
Pipe, including source electrode, drain electrode and grid, the drain electrode of the third transistor is connected to the drain electrode of the first transistor, and described the
The grid of three transistors is the level shifting circuit first input end, for receiving the first of the level shifting circuit the input
Signal；4th transistor, including source electrode, drain electrode and grid, the drain electrode of the 4th transistor is connected to the second transistor
Drain electrode, the grid of the 4th transistor is second input terminal of level shifting circuit, for receiving the level conversion
Second input signal of circuit, the drain electrode and the drain electrode of the 4th transistor of the second transistor are commonly connected to the electricity
The output terminal of circuit output signal is changed in flat turn；Conducting structure, be connected to the third transistor and analog circuit power supply AVSS it
Between, for being to the circuit of the first transistor, third transistor to AVSS according to the reverse signal of the output terminal output signal
No conducting is controlled；Duty cycle adjustment structure is connected between the 4th transistor and analog circuit power supply AVSS, is used for
The signal exported according to the output terminal is by the duty cycle adjustment of the level shifting circuit to predetermined duty ratio.
Optionally, the conducting structure includes：5th transistor, including source electrode, drain electrode and grid, the 5th transistor
Drain electrode be connected to the source electrode of the third transistor, the source electrode of the 5th transistor is connected to the AVSS；First reverse phase
Device, the input terminal of first phase inverter are connected to the drain electrode of the second transistor and the drain electrode of the 4th transistor, and described
The output terminal of one phase inverter is connected to the grid of the 5th transistor.
Optionally, the duty cycle adjustment structure includes：6th transistor, including source electrode, drain electrode and grid, the described 6th
The drain electrode of transistor is connected to the source electrode of the 4th transistor, and the source electrode of the 6th transistor is connected to the AVSS, institute
The grid for stating the 6th transistor is connected to the output terminal of the level shifting circuit output signal.
Optionally, the level shifting circuit further includes：Second phase inverter, the input terminal of second phase inverter are connected to
The output terminal of first phase inverter, the output terminal of second phase inverter substitute the defeated of the level shifting circuit output signal
Outlet.
Optionally, the level shifting circuit further includes：First shielding construction is connected to the third transistor and described
Between AVSS, for shielding the interference of the access between the third transistor and the AVSS.
Optionally, the level shifting circuit further includes：Secondary shielding structure is connected to the 4th transistor and described
Between AVSS, for shielding the interference of the access between the 4th transistor and the AVSS.
Optionally, first shielding construction includes：7th transistor, including source electrode, drain electrode and grid, the described 7th is brilliant
The drain electrode of body pipe is connected to the source electrode of the third transistor, and the source electrode of the 7th transistor is connected to the AVSS, described
The grid of 7th transistor is the level shifting circuit third input terminal, for receiving described the of the level shifting circuit
One input signal.
Optionally, the secondary shielding structure includes：8th transistor, including source electrode, drain electrode and grid, the described 8th is brilliant
The drain electrode of body pipe is connected to the source electrode of the 4th transistor, and the source electrode of the 8th transistor is connected to the AVSS, described
The grid of 8th transistor is the 4th input terminal of level shifting circuit, for receiving described the of the level shifting circuit
Two input signals.
Optionally, the level shifting circuit the first transistor, second transistor be P-channel field-effect transistor (PEFT) pipe PMOS tube, institute
State third transistor, the 4th transistor is N-channel field-effect tube NMOS tube.
Optionally, the 5th transistor of level shifting circuit is N-channel field-effect tube NMOS tube.
Optionally, the 6th transistor of level shifting circuit is N-channel field-effect tube NMOS tube.
Optionally, the 7th transistor of level shifting circuit is N-channel field-effect tube NMOS tube.
Optionally, the 8th transistor of level shifting circuit is N-channel field-effect tube NMOS tube.
Another aspect according to the present utility model additionally provides a kind of data transmission device, the data transmission device packet
Include level shifting circuit described in any one of the above embodiments.
The utility model is by providing a kind of preferred circuit design structure, using increase conducting structure, duty cycle adjustment
Structure, shielding construction etc. realize the purpose of the level conversion high-speed low-power-consumption in the case where not influencing duty ratio, and then solve
The technical issues of level conversion process high speed and low-power consumption can not have both.
Description of the drawings
Attached drawing described herein is used to provide a further understanding of the present invention, and forms the part of the application,
The illustrative embodiments and their description of the utility model are not formed for explaining the utility model to the improper of the utility model
It limits.In the accompanying drawings：
Fig. 1 is the schematic diagram according to a kind of common level shifting circuit of the relevant technologies；
Fig. 2 is the schematic diagram that level shifting circuit is commonly used according to the another kind of the relevant technologies；
Fig. 3 is the schematic diagram according to the level shifting circuit of the utility model embodiment；
Fig. 4 is the schematic diagram according to the level shifting circuit conducting structure 36 of the utility model embodiment；
Fig. 5 is the schematic diagram according to the level shifting circuit duty cycle adjustment structure 38 of the utility model embodiment；
Fig. 6 is the preferred structure schematic diagram one according to the level shifting circuit of the utility model embodiment；
Fig. 7 is the preferred structure schematic diagram two according to the level shifting circuit of the utility model embodiment；
Fig. 8 is the first shielding construction of level shifting circuit 72 according to the utility model embodiment, secondary shielding structure 74
Structure diagram；
Fig. 9 is the Transient in speed 800MHz realized according to the level shifting circuit of the utility model embodiment
Schematic diagram；
Figure 10 is the flow chart according to the level conversion method of the utility model embodiment.
Specific embodiment
In order to which those skilled in the art is made to more fully understand the utility model, below in conjunction with the utility model reality
The attached drawing in example is applied, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that described
Embodiment is only the embodiment of the utility model part, instead of all the embodiments.Based on the reality in the utility model
Apply example, those of ordinary skill in the art's all other embodiments obtained without making creative work all should
When the range for belonging to the utility model protection.
It should be noted that term " first " in the specification and claims of the utility model and above-mentioned attached drawing,
" second " etc. is the object for distinguishing similar, and specific sequence or precedence are described without being used for.It should be appreciated that in this way
The data used can be interchanged in the appropriate case, can be in addition at this so as to the embodiment of the utility model described herein
In diagram or description those other than sequence implement.In addition, term " comprising " and " having " and their any deformation, meaning
Figure be to cover it is non-exclusive include, for example, containing the process of series of steps or unit, method, system, product or equipment
Be not necessarily limited to those steps clearly listed or unit, but may include not listing clearly or for these processes,
The intrinsic other steps of method, product or equipment or unit.
According to the utility model embodiment, a kind of circuit embodiments of level conversion are provided.
Fig. 3 is according to the schematic diagram of the level shifting circuit of the utility model embodiment, as shown in figure 3, the level conversion
Circuit includes：The first transistor 31, second transistor 32, third transistor 33, the 4th transistor 34, conducting structure 36, duty
Than adjustment structure 38, the structure is illustrated below.
The first transistor 31, including source electrode, drain electrode and grid, the source electrode of the first transistor is connected to analog circuit power supply
AVDD, grid and the first transistor drain electrode of the first transistor connect；
Second transistor 32, including source electrode, drain electrode and grid, the source electrode of second transistor is connected to AVDD, the second crystal
Tube grid is connected with first crystal tube grid；
Third transistor 33, including source electrode, drain electrode and grid, the drain electrode of third transistor is connected to the leakage of the first transistor
Pole, the grid of third transistor is level shifting circuit first input end, for receiving the first of level shifting circuit the input letter
Number IP；
4th transistor 34, including source electrode, drain electrode and grid, the drain electrode of the 4th transistor is connected to the leakage of second transistor
Pole, the grid of the 4th transistor is the second input terminal of level shifting circuit, for receiving the second of level shifting circuit the input letter
Number IN, the drain electrode of second transistor and the drain electrode of the 4th transistor are commonly connected to the output of level shifting circuit output signal
End；
Conducting structure 36 is connected between third transistor and analog circuit power supply AVSS, for being exported according to output terminal
The reverse signal of signal is controlled whether the circuit of the first transistor, third transistor to AVSS is connected；
Duty cycle adjustment structure 38 is connected between the 4th transistor and analog circuit power supply AVSS, for according to output
The signal of output is held by the duty cycle adjustment of level shifting circuit to predetermined duty ratio.
Specifically, above-mentioned the first transistor 31,32 connection mode of second transistor are current-mirror structure, image current is played
Effect；Third transistor 33, the 4th transistor 34 are input pipe, respectively while the input signal of incoming level conversion circuit i.e. the
One input signal IP and its reverse signal i.e. the second input signal IN；If being not turned on structure 36, third transistor 33 with
Analog circuit power supply AVSS is connected directly, and can give tacit consent to AVSS herein for analog power ground terminal, when the first input signal IP is low
When pressing the high potential of signal, third transistor 33 is connected, and pulls down the grid potential of the first transistor 31 and second transistor 32, into
And second transistor 32 is connected, the output terminal of level shifting circuit is pulled to simulation together with the drain electrode of second transistor 32
The high voltage reference current potential that circuit power AVDD is provided.Meanwhile there are an accesses from analog circuit power supply AVDD to AVSS, it will
Consume larger electric current.At this point, adding in conducting structure 36, it is connected between third transistor 33 and analog circuit power supply AVSS,
By the reverse signal of input/output terminal output signal whether the circuit of the first transistor, third transistor to AVSS is connected into
Row control, i.e., when the first input signal IP is low-voltage signal high potential, the reverse signal of circuit output end output signal is height
After signal low potential, conducting structure 36 is pressed to input the low potential, the state of blocking is set as, and then reduce the conducting of AVDD to AVSS
Time, so as to reduce the power consumption of circuit.Then, the first input signal IP becomes low-voltage signal low potential, the second input signal IN
Accordingly become low-voltage signal high potential, third transistor 33 turns off, and the 4th transistor 34 is connected, and then level shifting circuit is defeated
Outlet is pulled low to the low potential of analog circuit power supply AVSS offers with the drain electrode of the 4th transistor 34 together.Output voltage at this time
Drop-down speed will greatly influence duty ratio, therefore add in duty cycle adjustment structure 38, be connected to the 4th transistor 34 and simulation
Between circuit power AVSS, for signal the accounting for level shifting circuit in above-mentioned state change, exported according to output terminal
Sky is than adjusting to predetermined duty ratio.
The utility model embodiment adds in traditional electric current mirror (current mirror) structure level shifting circuit
Enter conducting structure 36 and duty cycle adjustment structure 38, reference voltage end AVDD is controlled to ground terminal by using the state of output terminal
It the connection of AVSS accesses and blocking, conducting structure 36 and duty cycle adjustment structure 38 start to change after state output terminal foundation,
Reduce the time that power supply is connected to earth-current in the case where not influencing normally to export in this way, so as to reduce at high speeds
The power consumption of circuit, in turn ensures ideal duty ratio.
Fig. 4 is according to the schematic diagram of the level shifting circuit conducting structure 36 of the utility model embodiment, the level conversion
Circuit turn-on structure includes：5th transistor 42, the first phase inverter 44.
5th transistor 42, including source electrode, drain electrode and grid, the drain electrode of the 5th transistor is connected to the source of third transistor
Pole, the source electrode of the 5th transistor are connected to AVSS；
First phase inverter 44, the input terminal of the first phase inverter are connected to the drain electrode of second transistor and the leakage of the 4th transistor
Pole, the output terminal of the first phase inverter are connected to the grid of the 5th transistor.
I.e. by transistor and its corresponding connection mode in conducting structure, to realize power voltage terminal AVDD to ground terminal
It the connection of AVSS accesses and blocks.According to its connection, when the first input signal IP is low-voltage signal high potential, circuit output end
The reverse signal of output signal is high-voltage signal low potential, after the 5th transistor inputs the low potential, can not be connected, become circuit
State is blocked, and then reduces the turn-on time of AVDD to AVSS, so as to reduce the power consumption of ground circu-it.Meanwhile in conducting structure
By the first phase inverter, level shifting circuit is exported into reverse process, is input to the 5th transistor in structure, is blocked with realizing
The purpose of ground circu-it.
Fig. 5 is according to the schematic diagram of the level shifting circuit duty cycle adjustment structure 38 of the utility model embodiment, the electricity
Flat turn is changed circuit turn-on structure and is included：6th transistor 52, wherein：
6th transistor 52, including source electrode, drain electrode and grid, the drain electrode of the 6th transistor is connected to the source of the 4th transistor
Pole, the source electrode of the 6th transistor are connected to AVSS, and the grid of the 6th transistor is connected to the defeated of level shifting circuit output signal
Outlet.
By above-mentioned setting, by transistor and its corresponding connection mode in duty cycle adjustment structure, reach according to defeated
The signal of outlet output is by the purpose of the duty cycle adjustment of level shifting circuit to predetermined duty ratio.That is the second input signal IN
When accordingly becoming low-voltage signal high potential, the 4th transistor 34 is connected, and the output terminal of level shifting circuit is the same as the 4th transistor 34
Drain electrode be pulled low to together analog circuit power supply AVSS offer low potential, after the 5th transistor inputs the low potential, become
State is blocked, and then adjusts current potential drop-down speed and ensures that signal dutyfactor is unaffected.
Fig. 6 is the preferred structure schematic diagram one according to the level shifting circuit of the utility model embodiment, as shown in fig. 6,
The level shifting circuit conducting structure further includes：Second phase inverter 62, wherein：
Second phase inverter 62, the input terminal of the second phase inverter are connected to the output terminal of the first phase inverter, the second phase inverter
Output terminal substitutes the output terminal of level shifting circuit output signal.
Because conducting structure input signal needs, primary circuit output is changed into reverse signal with the first phase inverter, therefore to protect
The normal output of card, sets the second phase inverter, primary circuit is exported and is restored, and becomes consistent with the first input signal IP phases normal
Output.
Fig. 7 is the preferred structure schematic diagram two according to the level shifting circuit of the utility model embodiment, including：First screen
Shield structure 72, secondary shielding structure 74, wherein：
First shielding construction 72, is connected between third transistor and AVSS, for shield third transistor and AVSS it
Between access interference；
Secondary shielding structure 74 is connected between the 4th transistor and AVSS, for shield the 4th transistor and AVSS it
Between access interference.
By above-mentioned setting, ensure that level shifting circuit when low frequency inputs or has external disturbance circuit performance it is steady
It is fixed.Specially when the first input signal IP or the second input signal IN is for a long time low-voltage signal low potential or high potential, i.e.,
When inputting low frequency, probability of the circuit output since mistake occurring when electric leakage or external signal interference is reduced.If without M6, M7
Both when the first input signal IP is low-voltage high potential, the second input signal IN is low-voltage low potential, and third transistor is led
Logical, the 4th transistor cutoff, circuit output end Initial output signal is high voltage high potential, by the reversed of the first phase inverter
Signal high voltage low potential, then the 5th transistor cutoff, the 6th transistor turns, are not present logical from AVDD to ground AVSS in this way
Road if circuit output end leaks electricity to ground, can be pulled low circuit output terminal potential and invert, so as to which mistake occur
Accidentally.Therefore the first shielding construction, the addition of secondary shielding structure cause from AVDD to ground AVSS there are one access, in such case
Under when due to the first input signal IP being low-voltage high potential, in third transistor and the first shielding construction, there are power supplys to ground
Access, so the first transistor and second transistor can be connected so that the drain electrode of second transistor can maintain high potential, so i.e.
Circuit output end is made to leak electricity, but analog circuit power supply AVDD can maintain its high level for circuit output end charging always
State.
Fig. 8 is the first shielding construction of level shifting circuit 72 according to the utility model embodiment, secondary shielding structure 74
Structure diagram, the first shielding construction 72, secondary shielding structure 74 respectively include：7th transistor 82, the 8th transistor 84,
Wherein：
7th transistor 82, including source electrode, drain electrode and grid, the drain electrode of the 7th transistor is connected to the source of third transistor
Pole, the source electrode of the 7th transistor are connected to AVSS, and the grid of the 7th transistor is level shifting circuit third input terminal, for connecing
Receive the first input signal IP of level shifting circuit；
8th transistor 84, including source electrode, drain electrode and grid, the drain electrode of the 8th transistor is connected to the source of the 4th transistor
Pole, the source electrode of the 8th transistor are connected to AVSS, and the grid of the 8th transistor is the 4th input terminal of level shifting circuit, for connecing
Receive the second input signal IN of level shifting circuit.
Meanwhile wherein the 5th transistor 42, the first phase inverter 44 belong to above-mentioned conducting structure 36, the 6th transistor 52 belongs to
In duty cycle adjustment structure 38.
I.e. with the above arrangement, the first shielding construction, secondary shielding structure are by transistor and its corresponding connection mode,
Achieve the purpose that shield the access interference between AVSS respectively of third transistor, the 4th transistor.Wherein, in the first shielding construction
7th transistor is consistent with third transistor, inputs the first input signal IP, when input is low-voltage high potential, the 7th crystal
Pipe is connected, and forms third transistor to the access of AVSS；The 8th transistor is consistent with the 4th transistor in secondary shielding structure, defeated
Enter the second input signal IN, when input is low-voltage high potential, the 8th transistor turns form the 4th transistor to AVSS's
Access.Seven, the 8th transistors are selected for metal-oxide-semiconductor, because switching tube is operated in linear zone according to metal-oxide-semiconductor linear zone when working
Current formula：
Wherein, μ is carrier mobility, COXGate oxide capacitance, W for unit area are the grid width of metal-oxide-semiconductor, L is
The grid of metal-oxide-semiconductor are long, VGSFor metal-oxide-semiconductor gate source voltage, VTHFor metal-oxide-semiconductor threshold voltage, VDSFor source-drain voltage, IDIt is linear for metal-oxide-semiconductor
Area's operating current.
By designing the long size of grid of the 7th transistor and the 8th transistor, the larger grid long value L in zone of reasonableness is taken, is made
Must be minimum by the electric current of access, although increasing the overall stability that passage current ensure that conversion circuit in this way.
Preferably, the level shifting circuit described in any of the above item, the first transistor, second transistor are imitated for P-channel field
Should pipe PMOS tube, third and fourth, five, six, seven, eight transistors be N-channel field-effect tube NMOS tube.
According to above-mentioned metal-oxide-semiconductor linear zone current formula, by the grid for reasonably designing the 5th transistor and the 6th transistor
Long size, the level shifting circuit can achieve the purpose that high-speed low-power-consumption in the case where not damaging duty ratio well.Through
Test of many times, derives the reasonable value of the long size of each transistor gate, and Fig. 9 is the level conversion according to the utility model embodiment
The Transient schematic diagram in speed 800MHz that circuit is realized, wherein working together situation for two groups of circuits.Such as Fig. 9 institutes
Show, it can be seen that its output has achieved the effect that quickly to track, and power consumption also controls in a certain range.Continue to debug each transistor gate
Long size, power consumption control is at uA grades when this circuit can reach speed 2GHz, power dissipation ratio primary current mirror (current
Mirror) structure reduces by 40% or so good result.
According to the utility model another embodiment, a kind of level conversion method is additionally provided, Figure 10 is according to this reality
With the flow chart of the level conversion method of new embodiment, as shown in the figure, this method comprises the following steps：
Step S120 inputs the first input signal of pending level conversion in the grid of third transistor；
Step S140 inputs reversed the second of the first input signal of pending level conversion in the grid of the 4th transistor
Input signal；
Step S160, in the transformed output letter of the drain electrode of second transistor or the drain electrode output level of the 4th transistor
Number, wherein, AVDD is the supply voltage of level shifting circuit.
A still further embodiment according to the present utility model provides a kind of data transmission device, the data transmission device packet
Include level shifting circuit described in any one of the above embodiments.Wherein, which can be a kind of interface, and the kind of interface
Class may be a variety of, for example, can be to meet low-voltage differential signal (Low-Voltage in liquid crystal display
Differential Signaling, referred to as LVDS) standard interface, or the fine definition in laptop is more
Media (High Definition Multimedia Interface, referred to as HDMI) interface, can also be transmitter TX
(Transmit) interface of module.In addition, any one of them level also may be used in the conversion of level between distinct interface
Conversion circuit, for example, Electronic Industries Association (Electronic Industries Association, referred to as EIA) is formulated
Proposed standard (Recommended standard, referred to as RS) interface in interface rs232 level turn Transistor-Transistor
Logic circuit (Transistor-Transistor-Logic, referred to as TTL) level.
Above-mentioned the utility model embodiment serial number is for illustration only, does not represent the quality of embodiment.
In above-described embodiment of the utility model, all emphasize particularly on different fields to the description of each embodiment, in some embodiment
The part not being described in detail may refer to the associated description of other embodiment.
In several embodiments provided herein, it should be understood that disclosed technology contents can pass through others
Mode is realized.Wherein, the apparatus embodiments described above are merely exemplary, such as the division of the unit, Ke Yiwei
A kind of division of logic function, can there is an other dividing mode in actual implementation, for example, multiple units or component can combine or
Person is desirably integrated into another system or some features can be ignored or does not perform.Another point, shown or discussed is mutual
Between coupling, direct-coupling or communication connection can be INDIRECT COUPLING or communication link by some interfaces, unit or module
It connects, can be electrical or other forms.
The unit illustrated as separating component may or may not be physically separate, be shown as unit
The component shown may or may not be physical unit, you can be located at a place or can also be distributed to multiple
On unit.Some or all of unit therein can be selected according to the actual needs to realize the purpose of this embodiment scheme.
In addition, each functional unit in each embodiment of the utility model can be integrated in a processing unit,
Can be that each unit is individually physically present, can also two or more units integrate in a unit.It is above-mentioned integrated
Unit both may be used hardware form realize, can also be realized in the form of SFU software functional unit.
If the integrated unit is realized in the form of SFU software functional unit and is independent product sale or uses
When, it can be stored in a computer read/write memory medium.Based on such understanding, the technical solution of the utility model sheet
The part to contribute in other words to the prior art in matter or all or part of the technical solution can be with software products
Form embodies, which is stored in a storage medium, is used including some instructions so that a meter
It calculates machine equipment (can be personal computer, server or network equipment etc.) and performs each embodiment the method for the utility model
All or part of step.And aforementioned storage medium includes：USB flash disk, read-only memory (ROM, Read-Only Memory),
Random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disc or CD etc. are various to be stored
The medium of program code.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
For art personnel, under the premise of the utility model principle is not departed from, several improvements and modifications can also be made, these improve and
Retouching also should be regarded as the scope of protection of the utility model.
Claims (19)
1. a kind of level shifting circuit, which is characterized in that the level shifting circuit includes：
The first transistor, including source electrode, drain electrode and grid, the source electrode of the first transistor is connected to analog circuit power supply
AVDD, the grid of the first transistor are connected with the first transistor drain electrode；
Second transistor, including source electrode, drain electrode and grid, the source electrode of the second transistor is connected to the AVDD, and described
Two-transistor grid is connected with the first crystal tube grid；
Third transistor, including source electrode, drain electrode and grid, the drain electrode of the third transistor is connected to the first transistor
Drain electrode, the grid of the third transistor is the level shifting circuit first input end, for receiving the level conversion electricity
First input signal on road；
4th transistor, including source electrode, drain electrode and grid, the drain electrode of the 4th transistor is connected to the second transistor
Drain electrode, the grid of the 4th transistor is second input terminal of level shifting circuit, for receiving the level conversion electricity
Second input signal on road, the drain electrode and the drain electrode of the 4th transistor of the second transistor are commonly connected to the level
The output terminal of conversion circuit output signal；
Conducting structure is connected between the third transistor and analog circuit power supply AVSS, for defeated according to the output terminal
The reverse signal for going out signal is controlled to whether the circuit of the first transistor, the third transistor to the AVSS is connected
System；
Duty cycle adjustment structure is connected between the 4th transistor and the AVSS, for being exported according to the output terminal
Signal by the duty cycle adjustment of the level shifting circuit to predetermined duty ratio.
2. level shifting circuit according to claim 1, which is characterized in that the conducting structure includes：
5th transistor, including source electrode, drain electrode and grid, the drain electrode of the 5th transistor is connected to the third transistor
Source electrode, the source electrode of the 5th transistor are connected to the AVSS；
First phase inverter, the input terminal of first phase inverter are connected to drain electrode and the 4th transistor of the second transistor
Drain electrode, the output terminal of first phase inverter are connected to the grid of the 5th transistor.
3. level shifting circuit according to claim 2, which is characterized in that the duty cycle adjustment structure includes：
6th transistor, including source electrode, drain electrode and grid, the drain electrode of the 6th transistor is connected to the 4th transistor
Source electrode, the source electrode of the 6th transistor are connected to the AVSS, and the grid of the 6th transistor is connected to the level and turns
Change the output terminal of circuit output signal.
4. level shifting circuit according to claim 2, which is characterized in that further include：
Second phase inverter, the input terminal of second phase inverter are connected to the output terminal of first phase inverter, and described second is anti-
The output terminal of phase device substitutes the output terminal of the level shifting circuit output signal.
5. according to the level shifting circuit described in claim 4, which is characterized in that further include：
First shielding construction is connected between the third transistor and the AVSS, for shield the third transistor with
The interference of access between the AVSS.
6. level shifting circuit according to claim 5, which is characterized in that further include：
Secondary shielding structure is connected between the 4th transistor and the AVSS, for shield the 4th transistor with
The interference of access between the AVSS.
7. level shifting circuit according to claim 5, which is characterized in that first shielding construction includes：
7th transistor, including source electrode, drain electrode and grid, the drain electrode of the 7th transistor is connected to the third transistor
Source electrode, the source electrode of the 7th transistor are connected to the AVSS, and the grid of the 7th transistor is level conversion electricity
Road third input terminal, for receiving first input signal of the level shifting circuit.
8. level shifting circuit according to claim 6, which is characterized in that the secondary shielding structure includes：
8th transistor, including source electrode, drain electrode and grid, the drain electrode of the 8th transistor is connected to the 4th transistor
Source electrode, the source electrode of the 8th transistor are connected to the AVSS, and the grid of the 8th transistor is level conversion electricity
The 4th input terminal of road, for receiving second input signal of the level shifting circuit.
9. level shifting circuit according to claim 3, which is characterized in that further include：
Second phase inverter, the input terminal of second phase inverter are connected to the output terminal of first phase inverter, and described second is anti-
The output terminal of phase device substitutes the output terminal of the level shifting circuit output signal.
10. according to the level shifting circuit described in claim 9, which is characterized in that further include：
First shielding construction is connected between the third transistor and the AVSS, for shield the third transistor with
The interference of access between the AVSS.
11. level shifting circuit according to claim 10, which is characterized in that further include：
Secondary shielding structure is connected between the 4th transistor and the AVSS, for shield the 4th transistor with
The interference of access between the AVSS.
12. level shifting circuit according to claim 10, which is characterized in that first shielding construction includes：
7th transistor, including source electrode, drain electrode and grid, the drain electrode of the 7th transistor is connected to the third transistor
Source electrode, the source electrode of the 7th transistor are connected to the AVSS, and the grid of the 7th transistor is level conversion electricity
Road third input terminal, for receiving first input signal of the level shifting circuit.
13. level shifting circuit according to claim 11, which is characterized in that the secondary shielding structure includes：
8th transistor, including source electrode, drain electrode and grid, the drain electrode of the 8th transistor is connected to the 4th transistor
Source electrode, the source electrode of the 8th transistor are connected to the AVSS, and the grid of the 8th transistor is level conversion electricity
The 4th input terminal of road, for receiving second input signal of the level shifting circuit.
14. level shifting circuit according to any one of claim 1 to 13, which is characterized in that the first transistor,
Second transistor is P-channel field-effect transistor (PEFT) pipe PMOS tube, and the third transistor, the 4th transistor are N-channel field-effect tube NMOS
Pipe.
15. level shifting circuit according to claim 2, which is characterized in that the 5th transistor is N-channel field-effect
Pipe NMOS tube.
16. level shifting circuit according to claim 3, which is characterized in that the 6th transistor is N-channel field-effect
Pipe NMOS tube.
17. the level shifting circuit according to claim 7 or 12, which is characterized in that the 7th transistor is N-channel field
Effect pipe NMOS tube.
18. the level shifting circuit according to claim 8 or 13, which is characterized in that the 8th transistor is N-channel field
Effect pipe NMOS tube.
19. a kind of data transmission device, which is characterized in that the data transmission device includes any one of claim 1 to 18
The level shifting circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721248408.6U CN207490899U (en) | 2017-09-26 | 2017-09-26 | Level shifting circuit and data transmission device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721248408.6U CN207490899U (en) | 2017-09-26 | 2017-09-26 | Level shifting circuit and data transmission device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107623518A (en) * | 2017-09-26 | 2018-01-23 | 北京集创北方科技股份有限公司 | The method of level shifting circuit and application level change-over circuit |
| CN109713900A (en) * | 2018-12-25 | 2019-05-03 | 广东浪潮大数据研究有限公司 | A kind of electric potential transfer circuit and system low-speed backplane module |
| CN113129844A (en) * | 2021-04-06 | 2021-07-16 | Tcl华星光电技术有限公司 | Backlight driving circuit, driving method and backlight module |
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2017
- 2017-09-26 CN CN201721248408.6U patent/CN207490899U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107623518A (en) * | 2017-09-26 | 2018-01-23 | 北京集创北方科技股份有限公司 | The method of level shifting circuit and application level change-over circuit |
| CN107623518B (en) * | 2017-09-26 | 2024-05-14 | 北京集创北方科技股份有限公司 | Level shifter circuit and method for applying level shifter circuit |
| CN109713900A (en) * | 2018-12-25 | 2019-05-03 | 广东浪潮大数据研究有限公司 | A kind of electric potential transfer circuit and system low-speed backplane module |
| CN113129844A (en) * | 2021-04-06 | 2021-07-16 | Tcl华星光电技术有限公司 | Backlight driving circuit, driving method and backlight module |
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