CN106128354A - Flat display apparatus and scan drive circuit thereof - Google Patents
Flat display apparatus and scan drive circuit thereof Download PDFInfo
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- CN106128354A CN106128354A CN201610817091.7A CN201610817091A CN106128354A CN 106128354 A CN106128354 A CN 106128354A CN 201610817091 A CN201610817091 A CN 201610817091A CN 106128354 A CN106128354 A CN 106128354A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a kind of flat display apparatus and scan drive circuit thereof.This scan drive circuit includes multiple scan drive cells of cascade, and each scan drive cell produces scan signal by positive and negative scanning circuit, the first input circuit, first control circuit, the first pull-down circuit, the first pull-up circuit and the first output circuit；The second scanning signal is produced by the second input circuit, second control circuit, the second pull-down circuit, the second pull-up circuit and the second output circuit.By the way, the present invention is capable of simplifying the circuit of flat display apparatus, saves space, and then the narrow frame design of beneficially flat display apparatus.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of flat display apparatus and scan drive circuit thereof.
Background technology
Current flat display apparatus uses scan drive circuit, namely utilizes existing thin film transistor (TFT) plane to show
Scan drive circuit is produced on array base palte by device array process, it is achieved the type of drive to progressive scan.
In existing flat display apparatus, each scan drive cell only drives a scan line, and each turntable driving list
Unit is required to complete circuit and realizes producing driving signal, arranges all a plurality of scan lines in general closed planar display device, and this will
Need to design many scan drive cells, it is impossible to realize sharing, complex circuit designs certainly will be made, and take up room, be unfavorable for
The narrow frame design of flat display apparatus.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of flat display apparatus and scan drive circuit thereof, to simplify
The circuit of flat display apparatus, saves space, and then the narrow frame design of beneficially flat display apparatus.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of scan drive circuit, its
Including multiple scan drive cells of cascade, each scan drive cell includes:
Positive and negative scanning circuit, for receive the first scan control signal, the second scan control signal, drive signal and under
One-level scanning signal, and export forward and reverse control signal, forward and reverse control signal is used for controlling scan drive cell and is just carrying out
To scanning or reverse scan；
First input circuit, for receiving the first clock signal and receiving forward and reverse control signal from positive and negative scanning circuit,
And export the first input signal；
First pull-down circuit, for receiving the first input signal and the first reference voltage, and exports the first pulldown signal, right
Primary nodal point carries out drop-down；
First pull-up circuit, during for receiving the first input signal, the first reference voltage, the second reference voltage and second
Clock signal, and export the first pull-up signal, primary nodal point is pulled up；
First control circuit, for receiving the first input signal and the second reference voltage, for according to the first input signal
Secondary nodal point is charged；
First output circuit, is used for receiving second clock signal, produces scan signal according to second clock signal；
Second input circuit, receives scan signal for second clock signal with from the first output circuit, and defeated
Go out the second input signal；
Second pull-down circuit, for receiving the second input signal and the first reference voltage, and exports the second pulldown signal, right
3rd node carries out drop-down；
Second pull-up circuit, during for receiving the second input signal, the first reference voltage, the second reference voltage and second
Clock signal, and export the second pull-up signal, the 3rd node is pulled up；
Second control circuit, for receiving the second input signal and the second reference voltage, for according to the second input signal
Fourth node is charged；
Second output circuit, for receiving the first clock signal, produces the second scanning signal according to the first clock signal.
Wherein, positive and negative scanning circuit includes the first gate-controlled switch and the second gate-controlled switch, the control end of the first gate-controlled switch
Receiving the first scan control signal, the first end of the first gate-controlled switch connects the first end and the first input electricity of the second gate-controlled switch
Road, the second end of the first gate-controlled switch receives and drives signal, and the control end of the second gate-controlled switch receives the second scan control signal,
Second termination of the second gate-controlled switch accepts one-level scanning signal.
Wherein, the first input circuit includes that the 3rd gate-controlled switch, the control end of the 3rd gate-controlled switch receive the first clock letter
Number, the first end of the 3rd gate-controlled switch connects the first pull-down circuit, and the second end of the 3rd gate-controlled switch connects the first gate-controlled switch
The first end and the first end of the second gate-controlled switch；
First pull-down circuit includes the 4th gate-controlled switch, the 5th gate-controlled switch, the 6th gate-controlled switch and the first electric capacity, the
Control end, the second end of the 5th gate-controlled switch, the first end of the first electric capacity and the control of the 6th gate-controlled switch of four gate-controlled switches
End processed is all connected with primary nodal point, and the first end of the 4th gate-controlled switch and the control end of the 5th gate-controlled switch connect the 3rd gate-controlled switch
The first end, the second end of the 4th gate-controlled switch, the first end of the 5th gate-controlled switch, the first electric capacity the second end and the 6th can
First end of control switch all receives the first reference voltage.
Wherein, the first pull-up circuit includes the 7th gate-controlled switch, the 8th gate-controlled switch and the second electric capacity, and the 7th controlled opens
The end that controls closed connects the first end of the 3rd gate-controlled switch, and the second end of the 7th gate-controlled switch receives the first reference voltage, and the 7th
First end of gate-controlled switch connects control end and first end of the second electric capacity of the 8th gate-controlled switch, the second termination of the second electric capacity
Receiving second clock signal, the first end of the 8th gate-controlled switch connects primary nodal point, and the second end of the 8th gate-controlled switch receives second
Reference voltage；
First control circuit includes that the 9th gate-controlled switch, the control end of the 9th gate-controlled switch receive the second reference voltage, the
Second end of nine gate-controlled switches connects the first end of the 3rd gate-controlled switch, and the first end of the 9th gate-controlled switch connects secondary nodal point；
First output circuit includes the tenth gate-controlled switch and the 3rd electric capacity, and the first end of the 3rd electric capacity and the tenth controlled is opened
The control end closed connects secondary nodal point, and the second end of the tenth gate-controlled switch receives second clock signal, the of the 6th gate-controlled switch
Two ends connect the second end and first end of the tenth gate-controlled switch of the 3rd electric capacity, second end output the first scanning letter of the 3rd electric capacity
Number.
Wherein, the second input circuit includes the 11st gate-controlled switch, when the control end of the 11st gate-controlled switch receives second
Clock signal, the second end of the 11st gate-controlled switch connects the second end of the 3rd electric capacity, and the first end of the 11st gate-controlled switch connects
Second pull-down circuit；
Second pull-down circuit includes the 12nd gate-controlled switch, the 13rd gate-controlled switch, the 14th gate-controlled switch and the 4th
Electric capacity, control end, the second end of the 13rd gate-controlled switch, first end and the 14th of the 4th electric capacity of the 12nd gate-controlled switch
The control end of gate-controlled switch is all connected with the 3rd node, the first end of the 12nd gate-controlled switch and the control end of the 13rd gate-controlled switch
Connect the first end of the 11st gate-controlled switch, the second end of the 12nd gate-controlled switch, the first end of the 13rd gate-controlled switch, the 4th
Second end of electric capacity and the first end of the 14th gate-controlled switch all receive the first reference voltage.
Wherein, second control circuit includes the 15th gate-controlled switch, and the control end of the 15th gate-controlled switch receives the second ginseng
Examining voltage, the second end of the 15th gate-controlled switch connects the first end of the 11st gate-controlled switch, the first of the 15th gate-controlled switch
End connects fourth node；
Second output circuit includes the 16th gate-controlled switch and the 5th electric capacity, and first end and the 16th of the 5th electric capacity can
The control end of control switch connects fourth node, and the second end of the 16th gate-controlled switch receives the first clock signal, and the 14th is controlled
Second end of switch connects the second end and first end of the 16th gate-controlled switch of the 5th electric capacity, the second end output of the 5th electric capacity
Second scanning signal；
Second pull-up circuit includes the 17th gate-controlled switch, and the first end of the 17th gate-controlled switch receives second with reference to electricity
Pressure, the second end of the 17th gate-controlled switch connects the 3rd node, and the control end of the 17th gate-controlled switch connects the 7th gate-controlled switch
The first end.
Wherein, the second pull-up circuit farther includes the 18th gate-controlled switch, and the control end of the 18th gate-controlled switch connects
First end of the 11st gate-controlled switch, the control end of the first end connection the 17th gate-controlled switch of the 18th gate-controlled switch, the tenth
Second end of eight gate-controlled switches receives the first reference voltage.
Wherein, the first reference voltage is low level, and the second reference voltage is high level, and the first to the 18th gate-controlled switch is
N-type TFT, the most corresponding N-type film crystal of the control end of the first to the 18th gate-controlled switch, the first end and the second end
The grid of pipe, drain electrode and source electrode.
Wherein, the first reference voltage is low level, and the second reference voltage is high level, and the first to the 18th gate-controlled switch is
P-type TFT, the most corresponding p-type film crystal of the control end of the first to the 18th gate-controlled switch, the first end and the second end
The grid of pipe, drain electrode and source electrode.
For solving above-mentioned technical problem, another technical solution used in the present invention is: provide a kind of flat display apparatus,
Flat display apparatus includes any of the above-described scan drive circuit.
The invention has the beneficial effects as follows: be different from the situation of prior art, the scan drive circuit of the present invention is by positive and negative
Scanning circuit scans forward or backwards, is charged secondary nodal point by the first input circuit and first control circuit,
By the first pull-down circuit, primary nodal point is carried out drop-down, by the first pull-up circuit, primary nodal point is pulled up, by
One output circuit produces scan signal；By the second input circuit and second control circuit, fourth node is charged,
By the second pull-down circuit, the 3rd node is carried out drop-down, by the second pull-up circuit, the 3rd node is pulled up, by
Two output circuits produce the second scanning signal, and the present invention produces scan signal and second by shared positive and negative scanning circuit and sweeps
Retouch signal, the circuit realizing simplifying flat display apparatus with this, save space, and then the narrow frame of beneficially flat display apparatus sets
Meter.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below required for make
Accompanying drawing be briefly described, it should be apparent that, below describe in accompanying drawing be only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.Wherein:
Fig. 1 is the circuit diagram of the scan drive cell of the scan drive circuit of first embodiment of the invention；
Fig. 2 is the sequential chart of the scan drive circuit forward scan in Fig. 1；
Fig. 3 is the sequential chart of the scan drive circuit reverse scan in Fig. 1；
Fig. 4 is the structural representation of scan drive circuit in Fig. 1；
Fig. 5 is the simulation waveform schematic diagram of scan drive cell in Fig. 1；
Fig. 6 is the circuit diagram of the scan drive cell of second embodiment of the invention；
Fig. 7 is the circuit diagram of the scan drive cell of third embodiment of the invention；
Fig. 8 is the circuit diagram of the scan drive cell of fourth embodiment of the invention；
Fig. 9 is the structural representation of the flat display apparatus of first embodiment of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiment wholely.Based on this
Embodiment in invention, it is every other that those of ordinary skill in the art are obtained under not making performing creative labour premise
Embodiment, broadly falls into the scope of protection of the invention.
Referring to shown in Fig. 1-5, Fig. 1 is the electricity of the scan drive cell of the scan drive circuit of first embodiment of the invention
Lu Tu；Fig. 2 is the sequential chart of the scan drive circuit forward scan in Fig. 1；Fig. 3 is that the scan drive circuit in Fig. 1 is reversely swept
The sequential chart retouched；Fig. 4 is the structural representation of scan drive circuit in Fig. 1；Fig. 5 is the emulation ripple of scan drive cell in Fig. 1
Shape schematic diagram.Scan drive circuit disclosed in the present embodiment is used for producing scanning signal, to drive scanning by scanning signal
Line.As shown in Figure 4, scan drive circuit 10 includes multiple scan drive cells 11 of cascade.
As it is shown in figure 1, each scan drive cell 11 includes positive and negative scanning circuit the 111, first input circuit 112, first
Pull-down circuit the 113, first pull-up circuit 114, first control circuit the 115, first output circuit the 116, second input circuit 121,
Second pull-down circuit the 122, second pull-up circuit 123, second control circuit 124 and the second output circuit 125.
Wherein, positive and negative scanning circuit 111 is for receiving the first scan control signal U2D (Up to Down), the second scanning
Control signal D2U (Down to Up), driving signal STV and next stage scanning signal G7, and export forward and reverse control letter
Number CL1, forward and reverse control signal CL1 is used for controlling scan drive cell 11 and carries out forward scan or reverse scan.
Positive and negative scanning circuit 111 includes the first gate-controlled switch T1 and the second gate-controlled switch T2, the control of the first gate-controlled switch T1
End processed receives the first scan control signal U2D, and first end of the first gate-controlled switch T1 connects first end of the second gate-controlled switch T2
And first input circuit 112, second end of the first gate-controlled switch T1 receives and drives signal STV, the control of the second gate-controlled switch T2
End receives second termination of the second scan control signal D2U, the second gate-controlled switch T2 and accepts one-level scanning signal Gate7.
First input circuit 112 is for receiving the first clock signal CK1 and receiving forward and reverse control from positive and negative scanning circuit 111
Signal CL1 processed, and export the first input signal IN1.Wherein, the first input circuit 112 includes the 3rd gate-controlled switch T3, the 3rd
The control end of gate-controlled switch T3 receives the first clock signal CK1, and first end of the 3rd gate-controlled switch T3 connects the first pull-down circuit
113, second end of the 3rd gate-controlled switch T3 connects the first end and first end of the second gate-controlled switch T2 of the first gate-controlled switch T1.
First pull-down circuit 113 is for receiving the first input signal IN1 and the first reference voltage VGL, and exports first time
Draw signal, primary nodal point P1 is carried out drop-down.Wherein, the first pull-down circuit 113 includes the 4th gate-controlled switch T4, the 5th controlled opens
Close T5, the 6th gate-controlled switch T6 and the first electric capacity C1, the 4th gate-controlled switch T4 control end, the second of the 5th gate-controlled switch T5
The control end of end, first end of the first electric capacity C1 and the 6th gate-controlled switch T6 is all connected with primary nodal point P1, the 4th gate-controlled switch
First end of T4 and first end controlling end connection the 3rd gate-controlled switch T3 of the 5th gate-controlled switch T5, the 4th gate-controlled switch T4's
First end of the second end, first end of the 5th gate-controlled switch T5, second end of the first electric capacity C1 and the 6th gate-controlled switch T6 is equal
Receive the first reference voltage VGL.
First pull-up circuit 114 is for receiving the first input signal IN1, the first reference voltage VGL, the second reference voltage
VGH and second clock signal CK3, and export the first pull-up signal, primary nodal point P1 is pulled up.Wherein, the first pull-up
Circuit 114 includes the 7th gate-controlled switch T7, the 8th gate-controlled switch T8 and the second electric capacity C2, the control end of the 7th gate-controlled switch T7
Connecting first end of the 3rd gate-controlled switch T3, second end of the 7th gate-controlled switch T7 receives the first reference voltage VGL, and the 7th is controlled
First end of switch T7 connects control end and first end (i.e. node H1) of the second electric capacity C2 of the 8th gate-controlled switch T8, the second electricity
The second end holding C2 receives the first end connection primary nodal point P1 of second clock signal CK3, the 8th gate-controlled switch T8, and the 8th is controlled
Second end of switch T8 receives the second reference voltage VGH.
First control circuit 115 is for receiving the first input signal IN1 and the second reference voltage VGH, for according to first
Secondary nodal point Q1 is charged by input signal IN1.Wherein, first control circuit 115 includes the 9th gate-controlled switch T9, and the 9th can
The control end of control switch T9 receives the second reference voltage VGH, and second end of the 9th gate-controlled switch T9 connects the 3rd gate-controlled switch T3
The first end, the 9th gate-controlled switch T9 first end connect secondary nodal point Q1.
First output circuit 116 is used for receiving second clock signal CK3, produces first according to second clock signal CK3 and sweeps
Retouch signal Gate1.Wherein, the first output circuit 116 includes the tenth gate-controlled switch T10 and the 3rd electric capacity C3, the 3rd electric capacity C3
The first end and the control end of the tenth gate-controlled switch T10 connect second end of secondary nodal point Q1, the tenth gate-controlled switch T10 and receive the
Two clock signals CK3, second end of the 6th gate-controlled switch T6 connects second end of the 3rd electric capacity C3 and the tenth gate-controlled switch T10
First end, second end of the 3rd electric capacity C3 exports scan signal Gate1.
Second input circuit 121 for second clock signal CK3 and receives scan signal from the first output circuit 116
Gate1, and export the second input signal IN2.Wherein, the second input circuit 121 includes the 11st gate-controlled switch T11, the tenth
The control end of one gate-controlled switch T11 receives second end of second clock signal CK3, the 11st gate-controlled switch T11 and connects the 3rd electricity
Holding second end of C3, first end of the 11st gate-controlled switch T11 connects the second pull-down circuit 122.
Second pull-down circuit 122 is for receiving the second input signal IN2 and the first reference voltage VGL, and exports second time
Draw signal, the 3rd node P3 is carried out drop-down.Wherein, the second pull-down circuit 122 include the 12nd gate-controlled switch T12, the 13rd
Gate-controlled switch T13, the 14th gate-controlled switch T14 and the 4th electric capacity C4, the control end of the 12nd gate-controlled switch T12, the 13rd
The control end of second end of gate-controlled switch T13, first end of the 4th electric capacity C4 and the 14th gate-controlled switch T14 is all connected with the 3rd
First end of node P3, the 12nd gate-controlled switch T12 and the control end of the 13rd gate-controlled switch T13 connect the 11st gate-controlled switch
First end of T11, second end of the 12nd gate-controlled switch T12, first end of the 13rd gate-controlled switch T13, the 4th electric capacity C4
First end of the second end and the 14th gate-controlled switch T14 all receives the first reference voltage VGL.
Second control circuit 124 is for receiving the second input signal IN2 and the second reference voltage VGH, for according to second
Fourth node Q3 is charged by input signal IN2.Wherein, second control circuit 124 includes the 15th gate-controlled switch T15, the
The control end of 15 gate-controlled switch T15 receives the second reference voltage VGH, and second end of the 15th gate-controlled switch T15 connects the tenth
First end of one gate-controlled switch T11, first end of the 15th gate-controlled switch T15 connects fourth node Q3.
Second output circuit 125, for receiving the first clock signal CK1, produces second according to the first clock signal CK1 and sweeps
Retouch signal Gate3.Wherein, the second output circuit 125 includes the 16th gate-controlled switch T16 and the 5th electric capacity C5, the 5th electric capacity
First end of C5 and the control end of the 16th gate-controlled switch T16 connect fourth node Q3, second end of the 16th gate-controlled switch T16
Receiving the first clock signal CK1, second end of the 14th gate-controlled switch T14 connects second end and the 16th of the 5th electric capacity C5 can
First end of control switch T16, second end output the second scanning signal Gate3 of the 5th electric capacity C5.
Second pull-up circuit 123 is for receiving the second input signal IN2, the first reference voltage VGL, the second reference voltage
VGH and second clock signal CK3, and export the second pull-up signal, the 3rd node P3 is pulled up.Wherein, the second pull-up
Circuit 123 includes that the 17th gate-controlled switch T17, first end of the 17th gate-controlled switch T17 receive the second reference voltage VGH, the
The control end connection the 7th of second end connection the 3rd node P3, the 17th gate-controlled switch T17 of 17 gate-controlled switch T17 is controlled opens
Closing first end of T7, the i.e. second pull-up circuit 123 receives the first reference voltage VGL by the 7th gate-controlled switch T7, and passes through
Second electric capacity C2 receives second clock signal CK3.
Preferably, the first reference voltage VGL is low level, and the second reference voltage VGH is high level, and first can to the 17th
Control switch is N-type TFT, the most corresponding N-type of the control end of the first to the 17th gate-controlled switch, the first end and the second end
The grid of thin film transistor (TFT), drain electrode and source electrode.Wherein, the 9th gate-controlled switch T9 and second of first control circuit 115 controls electricity
The 15th gate-controlled switch T15 conducting on road 124.
The operation principle of scan drive cell 11 forward scan disclosed in the present embodiment is described in detail in conjunction with Fig. 2, below
Illustrate as a example by a scan drive cell (such as first order scan drive cell).
When scan drive cell 11 carries out forward scan, the first scan control signal U2D is high level, the second scan control
Signal D2U is low level, now the first gate-controlled switch T1 conducting, and the second gate-controlled switch T2 disconnects, and positive and negative scanning circuit 111 exports
Forward and reverse control signal CL1 for drive signal STV.
When the first clock signal CK1 is low level, the 3rd gate-controlled switch T3 of the first input circuit 112 disconnects, and first
First input signal IN1 of input circuit 112 output is low level.
It is high level driving signal STV, and when the first clock signal CK1 is high level, the first input circuit 112
3rd gate-controlled switch T3 conducting, the first input signal IN1 of the first input circuit 112 output is high level, and now first controls
Secondary nodal point Q1 is charged by circuit 115, and secondary nodal point Q1 charges to high level.5th gate-controlled switch T5 conducting, first time
It is low level that puller circuit 113 exports the first pulldown signal, and primary nodal point P1 is pulled down to low level, the 6th gate-controlled switch T6
Disconnect；7th gate-controlled switch T7 conducting, the 8th gate-controlled switch T8 disconnects, and primary nodal point P1 is pulled down stable to low level.
Owing to secondary nodal point Q1 charges to high level, the tenth gate-controlled switch T10 conducting of the first output circuit 116, now
It is identical with second clock signal CK3 that first output circuit 116 produces scan signal Gate1, at second clock signal CK3 is
During high level, scan signal Gate1 is high level, i.e. produces the gate drive signal of the first order.
Now, the 11st gate-controlled switch T11 conducting of the second input circuit 121, the second input signal IN2 is high level,
I.e. fourth node Q3 is charged, when fourth node Q3 is charged to high level, the 13rd gate-controlled switch T13 conducting, second time
3rd node P3 is carried out drop-down by puller circuit 122, and the 3rd node P3 is pulled down to low level, and the 14th gate-controlled switch T14 disconnects,
Now primary nodal point P1 and the 7th gate-controlled switch T7 the first end (i.e. H1 node) remain low level.
High level pulse in the first clock signal CK1 comes interim, the second scanning signal of the second output circuit 125 output
It is high level that Gate3 exports high level, i.e. third level gate drive signal.Therefore the scan drive cell disclosed in the present embodiment
11 are simultaneously suitable for Dual Drive circuit.
Being low level driving signal STV, the i.e. first input signal IN1 is low level, the 5th gate-controlled switch T5 and the 7th
Gate-controlled switch T7 disconnects, and the control end of the 8th gate-controlled switch T8 is booted to high level due to the second electric capacity C2, the 8th gate-controlled switch
T8 turns on, and the first pull-up circuit 114 is pulled to high level to primary nodal point P1, and primary nodal point P1 is by the first electric capacity C1
It is maintained at high level；4th gate-controlled switch T4 and the 6th gate-controlled switch T6 conducting, the 4th gate-controlled switch T4 is further by second section
Point Q1 is pulled low to low level, and the tenth gate-controlled switch T10 disconnects, and now scan signal Gate1 is drawn by the 6th gate-controlled switch T6
As little as low level.17th gate-controlled switch T17 conducting, the second pull-up circuit 123 is pulled to high level to the 3rd node P3,
And the 3rd node P3 be maintained at high level by the 4th electric capacity C4；12nd gate-controlled switch T12 and the 14th gate-controlled switch T14 leads
Logical, fourth node Q3 is pulled low to low level by the 12nd gate-controlled switch T12, and the 16th gate-controlled switch T16 disconnects, and the 14th is controlled
Second scanning signal Gate3 is pulled low to low level by switch T14, now scan signal Gate1 and second scanning signal
Gate3 stablizes output low level.
As it is shown on figure 3, the operation principle of scan drive cell 11 reverse scan disclosed in the present embodiment and forward scan
Work is similar, does not repeats them here.
As illustrated in figures 4-5, the function of scan drive circuit 10 of the present invention and the consistent of description and pass at multistage intercaste
Also can well work.From fig. 4, it can be seen that drive signal STV to include, the left side drives signal STVL and the right to drive letter
Number STVR, each scan drive cell 11 on the left side is operated alone by clock signal CK1 and clock signal CK3, the right
Each scan drive cell 11 is operated alone by clock signal CK2 and clock signal CK4, and described flat display apparatus uses
Interleaved type of drive, the scan drive circuit 10 that certain present invention provides can also be used for double drivings of panel.
The present embodiment produces scan signal Gate1 and second scanning signal by sharing positive and negative scanning circuit 111
Gate3, it is achieved common circuit, realizes simplifying circuit with this, saves space, and then the narrow frame of beneficially flat display apparatus sets
Meter.
As shown in Figure 6, the present invention also provides for the scan drive cell of the second embodiment, and it is disclosed in first embodiment
Scan drive cell 10 difference is: the first to the 17th gate-controlled switch is P-type TFT, and first can to the 17th
The most corresponding grid of P-type TFT of control end, the first end and the second end, drain electrode and the source electrode of control switch.Real at other
Executing in example, the first to the 17th gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
As it is shown in fig. 7, the present invention also provides for the scan drive cell of the 3rd embodiment, it is disclosed in first embodiment
Scan drive cell 10 difference is: the second pull-up circuit 123 farther includes the 18th gate-controlled switch T18, the 18th
Gate-controlled switch T18 controls the first end that end connects the 11st gate-controlled switch T11, and first end of the 18th gate-controlled switch T18 is even
Connecing the control end of the 17th gate-controlled switch T17, second end of the 18th gate-controlled switch T18 receives the first reference voltage VGL.
Preferably, the 18th gate-controlled switch T18 is N-type TFT, the control end of the 18th gate-controlled switch T18,
One end and the most corresponding grid of N-type TFT of the second end, drain electrode and source electrode.
Relative to the scan drive cell 10 disclosed in first embodiment, fourth node Q3 of the present embodiment passes through the 18th
The gate-controlled switch T18 control to node H1, increases the stability of node H1.
As shown in Figure 8, the present invention also provides for the scan drive cell of the 4th embodiment, and it is disclosed in the 3rd embodiment
Scan drive cell difference is: the first to the 18th gate-controlled switch is P-type TFT, and first is controlled to the 18th
The most corresponding grid of P-type TFT of control end, the first end and the second end, drain electrode and the source electrode of switch.Implement at other
In example, the first to the 18th gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
As it is shown in figure 9, the present invention also provides for the flat display apparatus of first embodiment.As it is shown in figure 9, flat display apparatus
Including aforesaid scan drive circuit, scan drive circuit is arranged on the both sides of flat display apparatus.In flat display apparatus
Other devices and function are identical with the device of existing flat display apparatus and function, do not repeat them here.Wherein, plane display dress
It is set to LCD or OLED.
In sum, the scan drive circuit of the present invention is scanned forward or backwards by positive and negative scanning circuit, passes through
Secondary nodal point is charged by the first input circuit and first control circuit, under being carried out primary nodal point by the first pull-down circuit
Draw, by the first pull-up circuit, primary nodal point is pulled up, produce scan signal by the first output circuit；By
Fourth node is charged by two input circuits and second control circuit, under being carried out the 3rd node by the second pull-down circuit
Draw, by the second pull-up circuit, the 3rd node is pulled up, produce the second scanning signal, the present invention by the second output circuit
Produce scan signal and the second scanning signal by sharing positive and negative scanning circuit, realize simplifying flat display apparatus with this
Circuit, saves space, and then the narrow frame design of beneficially flat display apparatus.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization is originally
Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or are directly or indirectly used in what other were correlated with
Technical field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. a scan drive circuit, it is characterised in that described scan drive circuit includes multiple scan drive cells of cascade,
Each described scan drive cell includes:
Positive and negative scanning circuit, for receiving the first scan control signal, the second scan control signal, driving signal and next stage
Scanning signal, and export forward and reverse control signal, described forward and reverse control signal is used for controlling described scan drive cell and enters
Row forward scan or reverse scan；
First input circuit, for receiving the first clock signal and receiving described forward and reverse control letter from described positive and negative scanning circuit
Number, and export the first input signal；
First pull-down circuit, is used for receiving described first input signal and the first reference voltage, and exports the first pulldown signal, right
Primary nodal point carries out drop-down；
First pull-up circuit, is used for receiving described first input signal, described first reference voltage, the second reference voltage and
Two clock signals, and export the first pull-up signal, described primary nodal point is pulled up；
First control circuit, is used for receiving described first input signal and described second reference voltage, for according to described first
Secondary nodal point is charged by input signal；
First output circuit, is used for receiving described second clock signal, produces the first scanning letter according to described second clock signal
Number；
Second input circuit, receives described first scanning letter for described second clock signal with from described first output circuit
Number, and export the second input signal；
Second pull-down circuit, is used for receiving described second input signal and described first reference voltage, and exports the second drop-down letter
Number, the 3rd node is carried out drop-down；
Second pull-up circuit, be used for receiving described second input signal, described first reference voltage, described second reference voltage with
And described second clock signal, and export the second pull-up signal, described 3rd node is pulled up；
Second control circuit, is used for receiving described second input signal and described second reference voltage, for according to described second
Fourth node is charged by input signal；
Second output circuit, is used for receiving described first clock signal, produces the second scanning letter according to described first clock signal
Number.
Scan drive circuit the most according to claim 1, it is characterised in that described positive and negative scanning circuit includes that first is controlled
Switch and the second gate-controlled switch, control end described first scan control signal of reception of described first gate-controlled switch, described first
First end of gate-controlled switch connects the first end of described second gate-controlled switch and described first input circuit, and described first controlled opens
The second end closed receives described driving signal, and the control end of described second gate-controlled switch receives described second scan control signal,
Second end of described second gate-controlled switch receives described next stage scanning signal.
Scan drive circuit the most according to claim 2, it is characterised in that described first input circuit includes that the 3rd is controlled
Switch, the control end of described 3rd gate-controlled switch receives described first clock signal, and the first end of described 3rd gate-controlled switch is even
Connecing described first pull-down circuit, the second end of described 3rd gate-controlled switch connects the first end of described first gate-controlled switch and described
First end of the second gate-controlled switch；
Described first pull-down circuit includes the 4th gate-controlled switch, the 5th gate-controlled switch, the 6th gate-controlled switch and the first electric capacity, institute
That states the 4th gate-controlled switch controls end, the second end of described 5th gate-controlled switch, the first end of described first electric capacity and described
The control end of the 6th gate-controlled switch is all connected with described primary nodal point, the first end of described 4th gate-controlled switch and described 5th controlled
The end that controls of switch connects the first end of described 3rd gate-controlled switch, the second end of described 4th gate-controlled switch, the described 5th can
First end of the first end, the second end of described first electric capacity and described 6th gate-controlled switch of control switch all receives described first
Reference voltage.
Scan drive circuit the most according to claim 3, it is characterised in that described first pull-up circuit includes that the 7th is controlled
Switch, the 8th gate-controlled switch and the second electric capacity, the end that controls of described 7th gate-controlled switch connects described 3rd gate-controlled switch
First end, the second end of described 7th gate-controlled switch receives described first reference voltage, the first end of described 7th gate-controlled switch
Connect described 8th gate-controlled switch controls end and the first end of described second electric capacity, and the second end of described second electric capacity receives institute
Stating second clock signal, the first end of described 8th gate-controlled switch connects described primary nodal point, the of described 8th gate-controlled switch
Two ends receive described second reference voltage；
Described first control circuit includes the 9th gate-controlled switch, and the control end of described 9th gate-controlled switch receives described second reference
Voltage, the second end of described 9th gate-controlled switch connects the first end of described 3rd gate-controlled switch, described 9th gate-controlled switch
First end connects described secondary nodal point；
First output circuit includes the tenth gate-controlled switch and the 3rd electric capacity, and first end and the described tenth of described 3rd electric capacity can
The control end of control switch connects described secondary nodal point, and the second end of described tenth gate-controlled switch receives described second clock signal,
Second end of described 6th gate-controlled switch connects the second end and the first end of described tenth gate-controlled switch, the institute of described 3rd electric capacity
The second end stating the 3rd electric capacity exports described scan signal.
Scan drive circuit the most according to claim 4, it is characterised in that described second input circuit includes that the 11st can
Control switch, the control end of described 11st gate-controlled switch receives described second clock signal, the of described 11st gate-controlled switch
Two ends connect the second end of described 3rd electric capacity, and the first end of described 11st gate-controlled switch connects described second pull-down circuit；
Described second pull-down circuit includes the 12nd gate-controlled switch, the 13rd gate-controlled switch, the 14th gate-controlled switch and the 4th
Electric capacity, described 12nd gate-controlled switch control end, the second end of described 13rd gate-controlled switch, the first of described 4th electric capacity
The control end of end and described 14th gate-controlled switch is all connected with described 3rd node, the first end of described 12nd gate-controlled switch
The first end of described 11st gate-controlled switch, described 12nd gate-controlled switch is connected with the end that controls of described 13rd gate-controlled switch
The second end, the first end of described 13rd gate-controlled switch, the second end of described 4th electric capacity and the described 14th controlled open
The first end closed all receives described first reference voltage.
Scan drive circuit the most according to claim 5, it is characterised in that described second control circuit includes that the 15th can
Control switch, the control end of described 15th gate-controlled switch receives described second reference voltage, the of described 15th gate-controlled switch
Two ends connect the first end of described 11st gate-controlled switch, and the first end of described 15th gate-controlled switch connects described Section four
Point；
Described second output circuit includes the 16th gate-controlled switch and the 5th electric capacity, the first end of described 5th electric capacity and described
The control end of the 16th gate-controlled switch connects described fourth node, and the second end of described 16th gate-controlled switch receives described first
Clock signal, the second end of described 14th gate-controlled switch connects second end and the described 16th of described 5th electric capacity and controlled opens
The first end closed, the described second scanning signal of the second end output of described 5th electric capacity；
Described second pull-up circuit includes the 17th gate-controlled switch, and the first end of described 17th gate-controlled switch receives described second
Reference voltage, the second end of described 17th gate-controlled switch connects described 3rd node, the control of described 17th gate-controlled switch
End connects the first end of described 7th gate-controlled switch.
Scan drive circuit the most according to claim 6, it is characterised in that described second pull-up circuit farther includes
18 gate-controlled switches, the end that controls of described 18th gate-controlled switch connects the first end of described 11st gate-controlled switch, and described the
First end of 18 gate-controlled switches connects the control end of described 17th gate-controlled switch, the second end of described 18th gate-controlled switch
Receive described first reference voltage.
Scan drive circuit the most according to claim 7, it is characterised in that described first reference voltage is low level, institute
Stating the second reference voltage is high level, and described first to the 18th gate-controlled switch is N-type TFT, described first to the tenth
The grid, drain electrode and the source electrode that control end, the first end and the second end corresponding described N-type TFT respectively of eight gate-controlled switches.
Scan drive circuit the most according to claim 7, it is characterised in that described first reference voltage is low level, institute
Stating the second reference voltage is high level, and described first to the 18th gate-controlled switch is P-type TFT, described first to the tenth
The grid, drain electrode and the source electrode that control end, the first end and the second end corresponding described P-type TFT respectively of eight gate-controlled switches.
10. a flat display apparatus, it is characterised in that described flat display apparatus includes as described in claim 1-9 is arbitrary
Scan drive circuit.
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| CN201610817091.7A CN106128354B (en) | 2016-09-12 | 2016-09-12 | Flat display apparatus and its scan drive circuit |
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| CN201610817091.7A CN106128354B (en) | 2016-09-12 | 2016-09-12 | Flat display apparatus and its scan drive circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107016970A (en) * | 2017-04-17 | 2017-08-04 | 深圳市华星光电技术有限公司 | DEMUX circuits |
| WO2021203485A1 (en) * | 2020-04-07 | 2021-10-14 | 武汉华星光电技术有限公司 | Goa circuit and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040189681A1 (en) * | 2003-02-19 | 2004-09-30 | Naoyuki Itakura | Display device and method of driving same |
| CN104485079A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
| CN104849928A (en) * | 2015-04-16 | 2015-08-19 | 上海中航光电子有限公司 | TFT array substrate, display panel and display device |
| CN104882107A (en) * | 2015-06-03 | 2015-09-02 | 深圳市华星光电技术有限公司 | Gate drive circuit |
| CN105206244A (en) * | 2015-10-29 | 2015-12-30 | 武汉华星光电技术有限公司 | GOA circuit and liquid crystal display |
-
2016
- 2016-09-12 CN CN201610817091.7A patent/CN106128354B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040189681A1 (en) * | 2003-02-19 | 2004-09-30 | Naoyuki Itakura | Display device and method of driving same |
| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
| CN104485079A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
| CN104849928A (en) * | 2015-04-16 | 2015-08-19 | 上海中航光电子有限公司 | TFT array substrate, display panel and display device |
| CN104882107A (en) * | 2015-06-03 | 2015-09-02 | 深圳市华星光电技术有限公司 | Gate drive circuit |
| CN105206244A (en) * | 2015-10-29 | 2015-12-30 | 武汉华星光电技术有限公司 | GOA circuit and liquid crystal display |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107016970A (en) * | 2017-04-17 | 2017-08-04 | 深圳市华星光电技术有限公司 | DEMUX circuits |
| CN107016970B (en) * | 2017-04-17 | 2019-12-24 | 深圳市华星光电半导体显示技术有限公司 | DEMUX circuit |
| WO2021203485A1 (en) * | 2020-04-07 | 2021-10-14 | 武汉华星光电技术有限公司 | Goa circuit and display panel |
| US11749166B2 (en) | 2020-04-07 | 2023-09-05 | Wuhan China Star Optoelectronics Technology Co., Ltd. | GOA circuit and display panel thereof |
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|---|---|
| CN106128354B (en) | 2018-01-30 |
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