CN112003596A

CN112003596A - Analog switch circuit

Info

Publication number: CN112003596A
Application number: CN202011079950.XA
Authority: CN
Inventors: 柯可人; 张富强
Original assignee: Sripu Microelectronics Technology Suzhou Co ltd
Current assignee: Sripu Microelectronics Technology Suzhou Co ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2020-11-27

Abstract

The invention discloses an analog switch circuit, which comprises: the switch comprises a plurality of switch branches, each switch branch comprises an NMOS (N-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) tube and a negative pressure protection unit, the source electrode and the drain electrode of each NMOS tube are electrically connected with two ports respectively, the drain electrode and the source electrode of each PMOS tube are electrically connected with the two ports respectively, grid control signals of the NMOS tubes and the PMOS tubes are VCN (vertical control channel) and VCP (vertical control channel), the NMOS tubes are MOS (metal oxide semiconductor) tubes based on a deep n-well, the substrate voltage is NBULK, and the negative pressure protection units are used for configuring the substrate voltage NBULK of. The analog switch circuit can be applied to negative voltage, can realize the function of negative voltage protection, has simple circuit and saves the area of a chip; the body effect of the MOS tube is eliminated, the on-resistance and on-resistance change of the MOS tube are reduced, the THD performance of the on-state of the MOS tube is improved, and the problem of leakage of a closed switch branch is solved; the whole switch circuit does not need extra static power consumption and can realize 0 static power consumption.

Description

Analog switch circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to an analog switch circuit.

Background

In integrated circuit design, analog switches are often used for path switching during signal transmission.

Referring to fig. 1, an analog switch circuit in the prior art includes two channels B0-a and B1-a, wherein a channel B0-a is connected in parallel with an NMOS transistor NM1 and a PMOS transistor PM1, a channel B1-a is connected in parallel with an NMOS transistor NM2 and a PMOS transistor PM2, gate control signals of NM1, PM1, NM2, and PM2 are VCN1, VCP1, VCN2, and VCP2, and timing charts of control signals VCN1, VCP1, VCN2, and VCP2 are shown in fig. 2, and are controlled by a high level (AVDD) and a low level (0), and substrate voltages of NM1 and NM2 are AVSS, and substrate voltages of PM1 and PM2 are AVDD.

In the analog switch circuit, B0-a channel is turned on at times t1-t1 and t4-t5 (NM1 and PM1 are on, substrate voltage NBULK1 of NM1 is min (B0, a), substrate voltage PBULK1 of PM1 is B0 potential), B1-a channel is turned on at times t2-t3 (NM1 and PM1 are on), substrate voltage NBULK1 of NM1 is min (B1, a), substrate voltage PBULK1 of PM1 is B1 potential), dead zones (B1-a channel and B1-a channel are both off at times t1-t1 (that is, NM1, PM1 are not on), NM1, NBULK1 and PM1 are all not on, and NM1, NBULK 1B (B) is on or not on, and PBULK 1B (B) is not on, and PBULK 1/B is not on. Wherein, B0, B1 and A are all positive voltages, and the analog switch circuit does not support the application that B0, B1 and A are negative voltages.

Referring to fig. 3, another analog switch circuit in the prior art includes two channels B0-a and B1-a, wherein a channel B0-a is connected in parallel with an NMOS transistor NM1 and a PMOS transistor PM1, a channel B1-a is connected in parallel with an NMOS transistor NM2 and a PMOS transistor PM2, gate control signals of NM1, PM1, NM2, and PM2 are VCN1, VCP1, VCN2, and VCP2, timing charts of control signals VCN1, VCP1, VCN2, and VCP2 are shown in fig. 4, the gate control signals of VCP1 and VCP2 are controlled by a high level (AVDD) and a low level (0), the gate control signals of VCN1 and VCN2 are controlled by a high level (AVDD) and a low level (NV, which are independently generated negative voltages, and simultaneously, the substrate voltages of PM1 and PM2 are controlled by a high level (AVDD), the substrate voltage of substrate 1 and Deep Well (wen 59n) and the substrate voltage (NV, and NV 2, and NV-NV, and NV 592 are adopted as process voltage.

In the analog switch circuit, the time points t1-t1 and t4-t5 are B0-A channel conduction, the time points t2-t3 are B1-A channel conduction, the time points t1-t2 and t3-t4 are dead zones, and the principles and the device operating states of the B0-A channel conduction, the B1-A channel conduction and the dead zones are similar to those of the first scheme, and are not described herein again. The analog switch circuit supports the application that B0, B1 and A are negative pressure, and NV is the lowest negative pressure in the allowable working range of B0, B1 and A.

Although the second scheme can support the negative voltage application, it needs additional static power consumption, and the NMOS transistor has bulk effect, has large on-resistance and on-resistance variation, and affects the performance of the whole switch circuit.

Therefore, in view of the above technical problems, it is necessary to provide an analog switch circuit.

Disclosure of Invention

The invention aims to provide an analog switch circuit to improve the performance of the switch circuit.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

an analog switching circuit, the circuit comprising:

the switch comprises a plurality of switch branches, each switch branch comprises an NMOS (N-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) tube and a negative pressure protection unit, the source electrode and the drain electrode of each NMOS tube are electrically connected with two ports respectively, the drain electrode and the source electrode of each PMOS tube are electrically connected with the two ports respectively, grid control signals of the NMOS tubes and the PMOS tubes are VCN (vertical control channel) and VCP (vertical control channel), the NMOS tubes are MOS (metal oxide semiconductor) tubes based on a deep n-well, the substrate voltage is NBULK, and the negative pressure protection units are used for configuring the substrate voltage NBULK of.

In one embodiment, the circuit includes:

the first switch branch circuit is electrically connected between the first port and the third port and comprises a first NMOS tube, a first PMOS tube and a first negative pressure protection unit, wherein the source electrode and the drain electrode of the first NMOS tube are respectively electrically connected with the first port and the third port, the source electrode and the drain electrode of the first PMOS tube are respectively electrically connected with the third port and the first port, the grid control signals of the first NMOS tube and the first PMOS tube are respectively VCN1 and VCP1, the first NMOS tube is an MOS tube based on a deep n well, the substrate voltage is NBULK1, and the first negative pressure protection unit is used for configuring the substrate voltage NBULK1 of the first NMOS tube to be the smaller of the voltage of the first port and the voltage of the third port;

the second switch branch circuit is electrically connected between the second port and the third port, and comprises a second NMOS transistor, a second PMOS transistor and a second negative voltage protection unit, wherein a source and a drain of the second NMOS transistor are electrically connected with the second port and the third port, respectively, a source and a drain of the second PMOS transistor are electrically connected with the third port and the second port, respectively, gate control signals of the second NMOS transistor and the second PMOS transistor are VCN2 and VCP2, the second NMOS transistor is a deep n-well-based MOS transistor, a substrate voltage is NBULK2, and the second negative voltage protection unit is configured to configure a substrate voltage NBULK2 of the second NMOS transistor as the smaller of the second port voltage and the third port voltage.

In one embodiment, the first protection unit includes a third NMOS transistor and a fourth NMOS transistor, where a gate of the third NMOS transistor is connected to a source of the first NMOS transistor, a drain of the third NMOS transistor is connected to the first port, a source of the third NMOS transistor and a source of the fourth NMOS transistor are both connected to a substrate voltage NBULK1, a gate of the fourth NMOS transistor is connected to a drain of the first NMOS transistor, a drain of the fourth NMOS transistor is connected to the third port, and a substrate of the third NMOS transistor and a substrate of the fourth NMOS transistor are connected to a substrate of the first NMOS transistor;

the second protection unit comprises a sixth NMOS tube and a seventh NMOS tube, wherein the grid electrode of the sixth NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the sixth NMOS tube is connected with the second port, the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are both connected with a substrate voltage NBULK2, the grid electrode of the seventh NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the seventh NMOS tube is connected with the third port, and the substrate of the sixth NMOS tube and the substrate of the seventh NMOS tube are connected with the substrate of the second NMOS tube.

In one embodiment, the first protection unit further includes a fifth NMOS transistor, a gate, a drain, and a substrate of the fifth NMOS transistor are connected to the substrate of the first NMOS transistor, and a source of the fifth NMOS transistor is connected to a gate of the third NMOS transistor;

the second protection unit further comprises an eighth NMOS tube, a grid electrode, a drain electrode and a substrate of the eighth NMOS tube are connected with a substrate of the second NMOS tube, and a source electrode of the eighth NMOS tube is connected with a grid electrode of the sixth NMOS tube.

In one embodiment, the circuit further comprises:

the first substrate following unit is used for connecting the substrate of the first PMOS tube to the source electrode of the first NMOS tube when the first switch branch is conducted;

and the second substrate following unit is used for connecting the substrate of the second PMOS tube to the source electrode of the second NMOS tube when the second switch branch is conducted.

In one embodiment, the first substrate following unit comprises a third PMOS transistor and a fourth PMOS transistor, a drain of the third PMOS transistor is connected to a source of the first NMOS transistor, a drain of the third PMOS transistor is connected to a substrate of the first PMOS transistor, a substrate of the third PMOS transistor is connected to a power supply voltage, a drain of the fourth PMOS transistor is connected to a substrate of the first PMOS transistor, and a substrate and a source of the fourth PMOS transistor are both connected to the power supply voltage AVDD;

the second substrate following unit comprises a fifth PMOS tube and a sixth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube is connected with the substrate of the second PMOS tube, the substrate of the fifth PMOS tube is connected with a power supply voltage, the drain electrode of the sixth PMOS tube is connected with the substrate of the second PMOS tube, and the substrate and the source electrode of the sixth PMOS tube are both connected with the power supply voltage AVDD.

In one embodiment, the gate control signal VCN1 of the first NMOS transistor is controlled by a high level AVDD and a low level NBULK 1;

the grid control signal VCP1 of the first PMOS tube is controlled by high level AVDD and low level 0;

the gate control signal VCN2 of the second NMOS transistor is controlled by a high level AVDD and a low level NBULK 2;

the gate control signal VCP2 of the second PMOS transistor is controlled by the high level AVDD and the low level 0.

In one embodiment, the circuit further comprises:

at time t0-t1, VCN1 is at high level AVDD, VCP1 is at low level 0, VCN2 is at low level NBULK2, and VCP2 is at high level AVDD, the first switching branch is turned on, and the second switching branch is turned off;

at time t1-t2, the voltage level of the VCN1 gradually decreases from the high level AVDD to the low level NBULK1, the voltage level of the VCP1 gradually increases from the low level 0 to the high level AVDD, the voltage level of the VCN2 is NBULK2, the voltage level of the VCP2 is AVDD, and the first switching branch and the second switching branch are both closed;

at time t2-t3, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 is gradually raised from low level NBULK2 to high level AVDD and maintained, VCP2 is gradually lowered from high level AVDD to low level 0 and maintained, the first switching branch is turned off, and the second switching branch is turned on;

at time t3-t4, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 is gradually lowered from high level AVDD to low level NBULK2 and is kept, VCP2 is gradually raised from low level 0 to high level AVDD and is kept, and the first switching branch and the second switching branch are both closed;

at time t4-t5, VCN1 gradually increases from low level NBULK1 to high level AVDD and maintains, VCP1 gradually decreases from high level AVDD to low level 0 and maintains, VCN2 is low level NBULK2, VCP2 is high level AVDD, the first switching branch is turned on, and the second switching branch is turned off.

Compared with the prior art, the invention has the following advantages:

the analog switch circuit can be applied to negative voltage, can realize the function of negative voltage protection, has simple circuit and saves the area of a chip;

the body effect of the MOS tube is eliminated, the on-resistance and on-resistance change of the MOS tube are reduced, the THD performance of the on-state of the MOS tube is improved, and the problem of leakage of a closed switch branch is solved;

the whole switch circuit does not need extra static power consumption and can realize 0 static power consumption.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of an analog switch circuit in the prior art;

FIG. 2 is a timing diagram of control signals of an analog switch circuit in the prior art;

FIG. 3 is a schematic diagram of another prior art analog switch circuit;

FIG. 4 is a timing diagram of control signals of an analog switch circuit according to another prior art;

FIG. 5 is a schematic diagram of an analog switch circuit in accordance with an embodiment of the present invention;

FIG. 6 is a timing diagram of control signals of the analog switch circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.

The invention discloses an analog switch circuit which comprises a plurality of switch branches, wherein each switch branch comprises an NMOS (N-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) tube and a negative pressure protection unit, the source electrode and the drain electrode of the NMOS tube are respectively and electrically connected with two ports, the drain electrode and the source electrode of the PMOS tube are respectively and electrically connected with two ports, grid control signals of the NMOS tube and the PMOS tube are respectively VCN (vertical control network) and VCP (vertical control network), the NMOS tube is an MOS (metal oxide semiconductor) tube based on a deep n well, the substrate voltage is NBULK, and the negative pressure protection unit is used for configuring the substrate voltage NBULK of the NMOS.

Referring to fig. 5, an analog switch circuit according to an embodiment of the invention includes:

a first switch branch (B0-a) electrically connected between the first port B0 and the third port a, including a first NMOS transistor NM1, a first PMOS transistor PM1 and a first negative voltage protection unit 11, wherein a source and a drain of the first NMOS transistor NM1 are electrically connected to the first port B0 and the third port a, respectively, a source and a drain of the first PMOS transistor PM1 are electrically connected to the third port a and the first port B0, respectively, gate control signals of the first NMOS transistor NM1 and the first PMOS transistor PM1 are VCN1 and VCP1, respectively, the first NMOS transistor NM1 is a deep n-well-based MOS transistor, the substrate voltage is NBULK1, and the first negative voltage protection unit 11 is configured to configure the substrate voltage NBULK1 of the first NMOS transistor NM1 as the smaller one of the first port voltage B0 and the third port a voltage, namely, 0, a (B0-a);

a second switch branch (B1-a) electrically connected between the second port B1 and the third port a, including a second NMOS tube NM2, a second PMOS tube PM2 and a second negative voltage protection unit 12, wherein the source and the drain of the second NMOS tube NM2 are electrically connected to the second port B1 and the third port a, respectively, the source and the drain of the second PMOS tube PM2 are electrically connected to the third port a and the second port B1, respectively, the gate control signals of the second NMOS tube NM2 and the second PMOS tube PM2 are VCN2 and VCP2, respectively, the second NMOS tube NM2 is a deep n-well-based MOS tube, the substrate voltage is NBULK2, and the second negative voltage protection unit 12 is configured to configure the substrate voltage NBULK2 of the second NMOS tube NM2 as the smaller one of the second port voltage B1 and the third port a, namely, i.e., min 1, a (B1-a).

Specifically, the first protection unit 11 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4, wherein a gate of the third NMOS transistor NM3 is connected to a source of the first NMOS transistor NM1, a drain of the third NMOS transistor NM3 is connected to the first port B0, a source of the third NMOS transistor NM3 and a source of the fourth NMOS transistor NM4 are both connected to the substrate voltage NBULK1, a gate of the fourth NMOS transistor NM4 is connected to a drain of the first NMOS transistor NM1, a drain of the fourth NMOS transistor NM4 is connected to the third port a, and a substrate of the third NMOS transistor NM3 and a substrate of the fourth NMOS transistor NM4 are connected to a substrate of the first NMOS transistor NM 1;

the second protection unit 12 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7, wherein a gate of the sixth NMOS transistor NM6 is connected to a source of the second NMOS transistor NM2, a drain of the sixth NMOS transistor NM6 is connected to the second port B1, a source of the sixth NMOS transistor NM6 and a source of the seventh NMOS transistor NM7 are both connected to the substrate voltage NBULK2, a gate of the seventh NMOS transistor NM7 is connected to a drain of the second NMOS transistor NM2, a drain of the seventh NMOS transistor NM7 is connected to the third port a, and a substrate of the sixth NMOS transistor NM6 and a substrate of the seventh NMOS transistor NM7 are connected to the substrate of the second NMOS transistor NM 2.

Further, the first protection unit 11 further includes a fifth NMOS transistor NM5, a gate, a drain, and a substrate of the fifth NMOS transistor NM5 are connected to the substrate of the first NMOS transistor NM1, and a source of the fifth NMOS transistor NM5 is connected to the gate of the third NMOS transistor NM 3;

the second protection unit 12 further includes an eighth NMOS transistor NM8, a gate, a drain, and a substrate of the eighth NMOS transistor NM8 are connected to the substrate of the second NMOS transistor NM2, and a source of the eighth NMOS transistor NM8 is connected to the gate of the sixth NMOS transistor NM 6.

The arrangement of NM3, NM4, NM6, and NM7 in the negative voltage protection unit of this embodiment can make the voltages of NBULK1 and NBULK2 be min (B0, a) and min (B1, a), respectively, thereby ensuring that the potentials of NBULK1 and NBULK2 are lower than the source and drain voltages of NM1 and the source and drain voltages of NM2, respectively, and thus realizing the negative voltage protection function. In addition, the invention does not need additional static power consumption, can realize 0 static power consumption, and the substrate of NM1 and NM2 follows the source, thereby eliminating the body effect of the NMOS tube.

The arrangement of NM5 and NM8 in the negative voltage protection unit solves the problem of leakage of the closed switch branch circuit at low temperature and under a rapid process angle, especially when the voltage B0 is close to the voltage B1, so that the leakage is reduced to na magnitude from a potential magnitude of dozens of mu a.

The switching circuit in this embodiment further includes:

a first substrate following unit 21 for connecting the substrate of the first PMOS transistor PM1 to the source of the first NMOS transistor NM1 when the first switching branch (B0-a) is turned on;

and a second substrate follower unit 22 for connecting the substrate of the second PMOS transistor PM2 to the source of the second NMOS transistor NM2 when the second switching branch (B1-a) is turned on.

Specifically, the first substrate following unit comprises a third PMOS transistor PM3 and a fourth PMOS transistor PM4, a drain electrode of the third PMOS transistor PM3 is connected to a source electrode of the first NMOS transistor NM1, a drain electrode of the third PMOS transistor PM3 is connected to a substrate of the first PMOS transistor PM1, a substrate of the third PMOS transistor PM3 is connected to a power supply voltage, a drain electrode of the fourth PMOS transistor PM4 is connected to the substrate of the first PMOS transistor PM1, and a substrate and a source electrode of the fourth PMOS transistor PM4 are both connected to the power supply voltage AVDD.

When the B0-A switch branch is closed, the grid of the PM3 is connected with AVDD, and the grid of the PM4 is connected with 0; when the B0-A switch branch is conducted, the grid of the PM3 is connected with 0, and the grid of the PM4 is connected with AVDD; when the B0-A switch branch is in a dead zone, the gate of the PM3 is connected with AVDD, and the gate of the PM4 is connected with 0.

The second substrate following unit comprises a fifth PMOS pipe PM5 and a sixth PMOS pipe PM6, the drain electrode of the fifth PMOS pipe PM5 is connected with the source electrode of a second NMOS pipe NM2, the drain electrode of the fifth PMOS pipe PM5 is connected with the substrate of a second PMOS pipe PM2, the substrate of the fifth PMOS pipe PM5 is connected with a power supply voltage, the drain electrode of the sixth PMOS pipe PM6 is connected with the substrate of the second PMOS pipe PM2, and the substrate and the source electrode of the sixth PMOS pipe PM6 are both connected with the power supply voltage AVDD.

When the B1-A switch branch is closed, the grid of the PM5 is connected with AVDD, and the grid of the PM6 is connected with 0; when the B1-A switch branch is conducted, the grid of the PM5 is connected with 0, and the grid of the PM6 is connected with AVDD; when the B1-A switch branch is in a dead zone, the gate of the PM5 is connected with AVDD, and the gate of the PM6 is connected with 0.

In the embodiment, when the switch branch B0-A or B1-A is conducted, PBULK1 or PBULK2 is connected to the source through PM3 or PM 5; when the switch branch of the B0-A or B1-A is turned off, PBULK1 or PBULK2 is connected to a power supply voltage AVDD through PM4 or PM6, the substrate of the PMOS transistor follows the source, and the body effect of the PMOS transistor is eliminated.

Because the body effect of NMOS and PMOS is eliminated in the analog switch circuit, the on-resistance (smaller on-resistance) of the MOS tube in unit area can be greatly improved; meanwhile, the change of the on-resistance (smaller on-resistance change) caused by the change of B0, B1, A and AVDD is also improved, so that the THD performance of the MOS tube on is improved.

Referring to fig. 6, the present embodiment includes four control signals, VCN1, VCP1, VCN2 and VCP2, wherein:

the gate control signal VCN1 of the first NMOS transistor NM1 is controlled by a high level AVDD and a low level NBULK 1;

the gate control signal VCP1 of the first PMOS transistor PM1 is controlled by a high level AVDD and a low level 0;

a gate control signal VCN2 of the second NMOS transistor NM2 is controlled by a high level AVDD and a low level NBULK 2;

the gate control signal VCP2 of the second PMOS transistor PM2 is controlled by the high level AVDD and the low level 0.

The first switching leg (B0-A) and the second switching leg (B1-A) operate in the following modes:

at time t0-t1, VCN1 is at high level AVDD, VCP1 is at low level 0, VCN2 is at low level NBULK2, VCP2 is at high level AVDD, the first switching leg (B0-a) is turned on (i.e., NM1 and PM1 are turned on), and the second switching leg (B1-a) is turned off (i.e., NM2 and PM2 are not turned on);

at time t1-t2, VCN1 gradually decreases from high level AVDD to low level NBULK1, VCP1 gradually increases from low level 0 to high level AVDD, VCN2 is low level NBULK2, VCP2 is high level AVDD, and both the first switch branch (B0-a) and the second switch branch (B1-a) are turned off (i.e., NM1, PM1, NM2, and PM2 are not conductive);

at time t2-t3, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 is gradually raised from low level NBULK2 to high level AVDD and maintained, VCP2 is gradually lowered from high level AVDD to low level 0 and maintained, first switch branch (B0-a) is turned off (i.e. NM1 and PM1 are not conductive), and second switch branch (B1-a) is conductive (i.e. NM2 and PM2 are conductive);

at time t3-t4, VCN1 is at low level NBULK1, VCP1 is at high level AVDD, VCN2 is gradually lowered from high level AVDD to low level NBULK2 and is kept, VCP2 is gradually raised from low level 0 to high level AVDD and is kept, and both the first switch branch (B0-a) and the second switch branch (B1-a) are turned off (that is, NM1, PM1, NM2, and PM2 are all not turned on);

at time t4-t5, VCN1 gradually increases from low level NBULK1 to high level AVDD and maintains, VCP1 gradually decreases from high level AVDD to low level 0 and maintains, VCN2 is low level NBULK2, VCP2 is high level AVDD, first switch branch (B0-a) is turned on (i.e., NM1 and PM1 are turned on), and second switch branch (B1-a) is turned off (i.e., NM2 and PM2 are turned off).

The low level of the control signals VCN1 and VCN2 in this embodiment is provided by NBULK1 or NBULK2, rather than the conventional fixed level, to ensure complete shut-off when the channel is re-opened.

According to the technical scheme, the invention has the following beneficial effects:

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. An analog switching circuit, the circuit comprising:

2. The analog switch circuit of claim 1, wherein the circuit comprises:

3. The analog switch circuit according to claim 2, wherein the first protection unit comprises a third NMOS transistor and a fourth NMOS transistor, wherein a gate of the third NMOS transistor is connected to a source of the first NMOS transistor, a drain of the third NMOS transistor is connected to the first port, a source of the third NMOS transistor and a source of the fourth NMOS transistor are both connected to a substrate voltage NBULK1, a gate of the fourth NMOS transistor is connected to a drain of the first NMOS transistor, a drain of the fourth NMOS transistor is connected to the third port, and a substrate of the third NMOS transistor and a substrate of the fourth NMOS transistor are connected to a substrate of the first NMOS transistor;

4. The analog switch circuit according to claim 3, wherein the first protection unit further comprises a fifth NMOS transistor, a gate, a drain and a substrate of the fifth NMOS transistor are connected to the substrate of the first NMOS transistor, and a source of the fifth NMOS transistor is connected to the gate of the third NMOS transistor;

5. The analog switch circuit of claim 2, further comprising:

6. The analog switch circuit according to claim 5, wherein the first substrate follower unit comprises a third PMOS transistor and a fourth PMOS transistor, wherein a drain electrode of the third PMOS transistor is connected with a source electrode of the first NMOS transistor, a drain electrode of the third PMOS transistor is connected with a substrate of the first PMOS transistor, the substrate of the third PMOS transistor is connected with a power supply voltage, a drain electrode of the fourth PMOS transistor is connected with the substrate of the first PMOS transistor, and a substrate and a source electrode of the fourth PMOS transistor are both connected with the power supply voltage AVDD;

7. The analog switch circuit of claim 2, wherein the gate control signal VCN1 of the first NMOS transistor is controlled by a high level AVDD and a low level NBULK 1;

8. The analog switch circuit of claim 7, wherein in the circuit: