CN106803755B

CN106803755B - Novel high-stability isolating switch circuit for negative pressure application

Info

Publication number: CN106803755B
Application number: CN201611203918.1A
Authority: CN
Inventors: 邓翔
Original assignee: Changsha Jingmei Integrated Circuit Design Co ltd
Current assignee: Changsha Jingmei Integrated Circuit Design Co ltd
Priority date: 2016-12-23
Filing date: 2016-12-23
Publication date: 2020-04-28
Anticipated expiration: 2036-12-23
Also published as: CN106803755A

Abstract

When negative voltage exists at two ends of a switch circuit, for a common MOS tube switch, if a substrate is fixedly connected at a source end or a drain end of the switch circuit, when the voltage at two ends of the switch changes, two ends of an originally disconnected MOS tube are possibly conducted or form a conducting diode, and the isolation performance of the switch is deteriorated. The invention provides a novel high-stability isolating switch circuit applied to negative pressure application, aiming at the situation, the switch circuit can ensure that the switch can not be conducted no matter how the voltage at the two ends of the switch circuit changes when the switch is disconnected, the switch circuit can be stably isolated, and the switch circuit can also normally work when the switch circuit is closed.

Description

Novel high-stability isolating switch circuit for negative pressure application

Technical Field

The invention mainly relates to the field of negative pressure application, in particular to a novel high-stability isolating switch circuit for negative pressure application.

Background

For an analog integrated circuit, a negative voltage circuit is often needed to realize a specific function in one module, but in order to control the negative voltage circuit and other circuits, a switch circuit needs to be added before the output of the negative voltage circuit is connected with other circuits, so that the negative voltage circuit and other modules work normally when the switch is switched on, and the negative voltage circuit and other modules are isolated from each other when the switch is switched off, and the work of each circuit is not influenced. However, the original isolation may be turned into a conductive state with the change of the environment, so that the originally disconnected circuits are conducted and mutually affected. For example, in a negative voltage application, a gate of a simple NMOS switch tube is controlled to disconnect a negative voltage circuit at two ends of the switch tube, and a substrate of the NMOS switch tube is fixedly connected to a source of the lowest potential.

Disclosure of Invention

The problems to be solved by the invention are as follows: to solve the problems in the prior art, a novel high-stability isolating switch circuit for negative pressure application is provided.

The solution proposed by the invention is as follows: this circuit is through adopting four extra supplementary MOS pipes, when the switch disconnection, with the substrate of switch tube and grid along with the source electrode of the minimum potential of output voltage potential difference connect switch tube all the time, the diode that so switch tube formed will be in reverse bias's state all the time, will not switch on to play the effect of abundant isolation.

Drawings

FIG. 1 is a circuit diagram of a conventional switch;

fig. 2 is a schematic diagram of the circuit principle of the present invention.

Detailed Description

The invention will be described in further detail with reference to the drawings and specific embodiments.

As known from the conventional isolation switch in fig. 1, the switch M0 is used to isolate the negative voltage branch, when VA0-VB0>0, VB0 is a negative voltage, or VA0 and VB0 are both negative voltages, in order to turn off the switch, the F node is grounded, and the substrate G node of the NMOS transistor must be connected to the source of the lowest point, determined by the process. If a substrate is connected with a node A0, a conducting diode is generated when a switch is disconnected, and the condition is not allowed to occur, so a node G of the substrate is connected with a lowest potential end B0, at the moment, the end B0 is used as a source, and because the end B0 is a negative potential and the node F is a0 potential, the grid-source voltage of M0 is a positive value, the switch is likely to be conducted, and when the simple NMOS switch is disconnected, the nodes A0 and B0 are conducted, so that the isolation performance of the switch when the switch is disconnected is influenced; similarly, when VA0-VB0<0, the nodes A0 and B0 are also conducted.

For the isolating switch circuit of the invention in fig. 2, the two situations of switch on and switch off are analyzed in detail respectively.

Analyzing the circuit for the condition of switch closure, wherein the C node is connected with 0 potential, the switches M5 and M1 are closed, the A node and the B node are conducted and are negative voltage, the E node potential is initially at an indefinite potential when M4 does not exist and the branch is disconnected, if the E node potential is higher, the substrates of M2 and M3 and the A node and the B node form a conducting diode and continuously discharge until the potential is not enough to make the diode conduct, the E node potential is stabilized at a potential value close to the A node and the B node, if the E node potential is less than A, B node, two tubes are conducted because the grid source voltage of M2 and M3 is greater than 0, and finally the E node potential is gradually increased until M2 and M3 are cut off, and the E node potential is stabilized at a potential value close to the A node and the B node; as shown in the figure, in the case of M4, the D node is VDD, the C node is 0 potential, if the E node is a high potential, then M4 is completely turned off, and simultaneously, the E node is turned on along with the turning on of M2 and M3 to a negative potential, because the gate-source voltage of M4 is greater than 0, M4 is turned on, the E node potential rises until the E node potential is stable when M4 is turned off, because the C node is greater than the A and B nodes, the E node potential is finally determined by the branch of M4, and the E node potential can be close to the A, B node potential by reducing the size of M4. Therefore, when the switch circuit is conducted, the voltage of the substrate E node is stabilized at a fixed potential, and the potential switch is normally conducted.

Analyzing the circuit for the case that the switch is disconnected, wherein the node C is connected with VDD, the switch M5 is disconnected, the M4 is conducted, the NMOS tubes M2 and M3 select the node E connected with lower potential according to the point with smaller potential values of the node A and the node B, if the potential of the point A is higher, the M3 is conducted, the M2 is cut off, the point E is connected with the point B through the M3, the grid D of the M1 is connected with the node B through the M4 and the M3, and the M1 is completely disconnected; assuming that the potential at the point B is high, M2 is turned on, M3 is turned off, the point E is connected with the point A through M2, the grid D of M1 is connected with the node A through M4 and M2, and M1 is completely disconnected; meanwhile, even if the potential of the node A and the potential of the node B are changed continuously in the working process, the grid and the substrate of the M1 can select the lowest potential point, the switch M1 is ensured to be in an off state all the time, and the stable isolation of the switch is ensured.

Claims

1. A novel high stable isolator circuit for negative pressure is used which characterized in that: the switch circuit is composed of a first NMOS transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3), a fourth NMOS transistor (M4) and a first PMOS transistor (M5); the grid electrode of the first NMOS tube (M1) is connected to the drain electrodes of the fourth NMOS tube (M4) and the first PMOS tube (M5), the drain electrode of the first NMOS tube (M1) is connected with the drain electrode of the third NMOS tube (M3) and the grid electrode of the second NMOS tube (M2), the source electrode of the first NMOS tube (M1) is connected with the drain electrode of the second NMOS tube (M2) and the grid electrode of the third NMOS tube (M3), the substrate of the first NMOS tube (M1) is connected with the substrate and the source electrode of the second NMOS tube (M2), the third NMOS tube (M3) and the fourth NMOS tube (M4), the source electrode and the substrate of the first PMOS tube (M5) are connected with a power supply, the grid electrode of the first PMOS tube (M5) is connected with the grid electrode of the fourth NMOS tube (M4), the grid electrode of the first PMOS tube (M5) is controlled by logic, and the input and the output of the first NMOS tube (M1) are respectively.