CN114389232B - Power-off protection circuit for multiplexer - Google Patents
Power-off protection circuit for multiplexer Download PDFInfo
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- CN114389232B CN114389232B CN202210056760.9A CN202210056760A CN114389232B CN 114389232 B CN114389232 B CN 114389232B CN 202210056760 A CN202210056760 A CN 202210056760A CN 114389232 B CN114389232 B CN 114389232B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/021—Details concerning the disconnection itself, e.g. at a particular instant, particularly at zero value of current, disconnection in a predetermined order
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/05—Details with means for increasing reliability, e.g. redundancy arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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Abstract
The invention belongs to the field of analog integrated circuits, and particularly relates to a power-off protection circuit for a multiplexer, which comprises: the circuit comprises a buffer circuit, a power-off protection circuit and a switch circuit; the output end of the buffer circuit is connected with the switch circuit, and the output end of the power-off protection circuit is connected with the switch circuit; the buffer circuit comprises four MOS tubes and two diodes; the power-off protection circuit comprises four MOS tubes and two diodes; the switching circuit comprises two MOS tubes; the invention designs a power-off protection circuit of a multiplexer, which can eliminate abnormal channel current and parasitic diode current generated by the multiplexer during power off through a buffer circuit and the power-off protection circuit, and improve the reliability of the circuit.
Description
Technical Field
The invention belongs to the field of analog integrated circuits, and particularly relates to a power-off protection circuit for a multiplexer.
Background
A multiplexer, i.e. a data selector, for multiplexing data of N input channels onto one output channel has a very important application in digital systems. As shown in figure 1, the address and enabling signals of a conventional multiplexer are converted into channel selection signals through a decoder, and then a multi-stage inverter generates differential signals to control on and off of a switch, the signals are input by S1-Sn, and one of the signals is selected to be output from D.
Conventional multiplexer circuits have stringent constraint requirements for analog signals, supply voltages, and power-up sequences in use: the analog signal must be controlled within the power supply voltages VSS-VDD, otherwise signal crosstalk and even damage to the circuit may occur. When the multiplexer is powered down, the analog signal will go beyond the supply voltage range, and 2 situations will occur: (1) when vdd=0 and S1> vdd+0.7v, VGS < VTHP of the PMOS transistor P3 cannot be turned off, and a signal is transmitted to the output, which affects the load of the subsequent stage; the parasitic diode formed by the source end P+ active region and the substrate N well is conducted forward, abnormal large current is generated, and the chip is burnt out seriously; (2) when vss=0 and S1< VSS-0.7V, the NMOS transistor N3 cannot be turned off and the source-liner parasitic diode is turned on in the forward direction, generating an abnormal output voltage and channel current.
In summary, in the use process of the conventional multiplexer chip, abnormal channel current and parasitic diode current are caused by power failure, and when a typical power failure mode such as cold backup, arbitrary power-up sequence and the like is used, a power failure protection circuit needs to be added for the switch.
Disclosure of Invention
To solve the above problems in the prior art, the present invention proposes a power-off protection circuit for a multiplexer, the circuit comprising: the circuit comprises a buffer circuit, a power-off protection circuit and a switch circuit; the output end of the buffer circuit is connected with the switch circuit, and the output end of the power-off protection circuit is connected with the switch circuit; the power-off protection circuit is characterized by comprising: MOS tube P6, MOS tube P7, MOS tube N6, MOS tube N7, diode D3 and diode D4; the switching circuit comprises a MOS tube P8 and a MOS tube N8;
the output of the power-off protection circuit is connected with the switching circuit and comprises: the grid electrodes of the MOS tube P6 and the MOS tube P7 are connected with a power supply VDD, the drain electrode of the MOS tube P6 is connected with the grid electrode of the MOS tube P8, the source electrode of the MOS tube P6 is respectively connected with the source electrode of the MOS tube P8 and the drain electrode of the MOS tube N8, and the substrate of the MOS tube P6 is respectively connected with the source electrode of the MOS tube P7, the substrate of the MOS tube P7 and the substrate of the MOS tube P8; the source electrode of the MOS tube P7 is connected with the cathode of the diode D3, the drain electrode is connected with the source electrode of the MOS tube P8, and the substrate is connected with the substrate of the MOS tube P8; the anode of the diode D3 is connected with a power supply VDD; the grid electrode of the MOS tube N6 is connected with the grid electrode of the MOS tube N7 and then connected with a negative power supply VSS; the drain electrode of the MOS tube N6 is respectively connected with the drain electrode of the MOS tube N7 and the drain electrode of the MOS tube N8, the source electrode is connected with the grid electrode of the MOS tube N8, and the substrate is connected with the anode of the diode D4; the drain electrode of the MOS tube N7 is connected with the drain electrode of the MOS tube N8, and the source electrode is connected with the anode of the diode D4; the negative electrode of the diode D4 is connected with a negative power supply VSS; the source electrode of the MOS tube P8 is connected with the drain electrode of the MOS tube N8, the drain electrode is connected with the source electrode of the MOS tube N8, and the substrate of the MOS tube N8 is connected with the anode of the diode D4.
Preferably, the buffer circuit includes a first inverter and a second inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the first phase inverter and the output end of the second phase inverter are respectively connected with the switch circuit to obtain the buffer circuit.
Further, the first inverter includes a MOS transistor P4, a MOS transistor N4, and a diode D1; the source electrode of the MOS tube P4 is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the MOS tube N4, and the grid electrode is connected with the grid electrode of the MOS tube N4; the source electrode of the MOS transistor N4 is connected with the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected with the negative power supply VSS; the grid electrode of the MOS tube P4 connected with the MOS tube N4 is used as a channel selection signal input end of the first phase inverter, and the drain electrode of the MOS tube P4 connected with the MOS tube N4 is used as an output end of the first phase inverter.
Further, the second inverter includes a MOS transistor P5, a MOS transistor N5, and a diode D2; the anode of the diode D2 is connected with the power supply VDD, and the cathode of the diode D is connected with the source electrode of the MOS tube P5; the grid electrode of the MOS tube P5 is connected with the grid electrode of the MOS tube N5, and the drain electrode is connected with the drain electrode of the MOS tube N5; the source electrode of the MOS tube N5 is connected with a negative power supply VSS; and taking a grid electrode formed by connecting the MOS tube P5 and the MOS tube N5 as an input end of the second phase inverter, and taking a drain electrode formed by connecting the MOS tube P5 and the MOS tube N5 as an output end of the second phase inverter.
Preferably, the snubber circuit is connected to the switching circuit and includes: the output end of the first phase inverter of the buffer circuit is connected with the grid electrode of the MOS tube N8 of the switch circuit, and the output end of the second phase inverter of the buffer circuit is connected with the grid electrode of the MOS tube P8 of the switch circuit.
The invention has the beneficial effects that:
in the power-off protection circuit for the multiplexer, the channel selection signals generated by the decoder form differential signal control switches P8 and N8 through the buffer circuit; when the power supply is powered off, P6, P7, N6 and N7 controlled by the positive power supply VDD and the negative power supply VSS in the power-off protection circuit are respectively conducted, an analog input signal S is transmitted to the grid electrodes and the substrate of P8 and N8, a MOSFET channel of the switching circuit is closed, and the substrate-drain voltage drop is reduced; the diodes D1, D2, D3 and D4 in the power-off protection circuit can prevent the analog input voltage from flowing back to the positive and negative power ports through the parasitic diode, so that abnormal channel current and parasitic diode current generated by the multiplexer during power-off are eliminated, and the application range and reliability of the circuit are improved.
Drawings
FIG. 1 is a circuit diagram of a conventional analog switch;
fig. 2 is a circuit diagram of a power-off protection circuit for a multiplexer according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A power-off protection circuit for a multiplexer includes, in order, a buffer circuit, a power-off protection circuit, and a switching circuit. The power-off protection circuit adopts the following measures: 1. the switch circuit avoids forward bias leakage of a source-substrate parasitic diode of the switch Guan Fa through a substrate-power supply series diode; 2. the power-off protection circuit samples analog input signals to the switch tube substrate and the grid electrode, and thoroughly closes the parasitic diode and the MOSFET channel; 3. and a diode is adopted in the buffer circuit to avoid backward current.
A power-down protection circuit for a multiplexer, as shown in fig. 2, comprising: the circuit comprises a buffer circuit, a power-off protection circuit and a switch circuit; the output end of the buffer circuit is connected with the switch circuit, and the output end of the power-off protection circuit is connected with the switch circuit. The power-off protection circuit includes: MOS tube P6, MOS tube P7, MOS tube N6, MOS tube N7, diode D3 and diode D4; the switch circuit comprises a MOS tube P8 and a MOS tube N8.
The output of the power-off protection circuit is connected with the switching circuit and comprises: the grid electrodes of the MOS tube P6 and the MOS tube P7 are connected with a power supply VDD, the drain electrode of the MOS tube P6 is connected with the grid electrode of the MOS tube P8, the source electrode of the MOS tube P6 is respectively connected with the source electrode of the MOS tube P8 and the drain electrode of the MOS tube N8, and the substrate of the MOS tube P6 is respectively connected with the source electrode of the MOS tube P7, the substrate of the MOS tube P7 and the substrate of the MOS tube P8; the source electrode of the MOS tube P7 is connected with the cathode of the diode D3, the drain electrode is connected with the source electrode of the MOS tube P8, and the substrate is connected with the substrate of the MOS tube P8; the anode of the diode D3 is connected with a power supply VDD; the grid electrode of the MOS tube N6 is connected with the grid electrode of the MOS tube N7 and then connected with a negative power supply VSS; the drain electrode of the MOS tube N6 is respectively connected with the drain electrode of the MOS tube N7 and the drain electrode of the MOS tube N8, the source electrode is connected with the grid electrode of the MOS tube N8, and the substrate is connected with the anode of the diode D4; the drain electrode of the MOS tube N7 is connected with the drain electrode of the MOS tube N8, and the source electrode is connected with the anode of the diode D4; the negative electrode of the diode D4 is connected with a negative power supply VSS; the source electrode of the MOS tube P8 is connected with the drain electrode of the MOS tube N8, the drain electrode is connected with the source electrode of the MOS tube N8, and the substrate of the MOS tube N8 is connected with the anode of the diode D4.
The buffer circuit is connected with the switch circuit and comprises: the output end of the first phase inverter of the buffer circuit is connected with the grid electrode of the MOS tube N8 of the switch circuit, and the output end of the second phase inverter of the buffer circuit is connected with the grid electrode of the MOS tube P8 of the switch circuit.
The buffer circuit comprises a first phase inverter and a second phase inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the first phase inverter and the output end of the second phase inverter are respectively connected with the switch circuit to obtain the buffer circuit.
The first phase inverter comprises a MOS tube P4, a MOS tube N4 and a diode D1; the source electrode of the MOS tube P4 is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the MOS tube N4, and the grid electrode is connected with the grid electrode of the MOS tube N4; the source electrode of the MOS transistor N4 is connected with the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected with the negative power supply VSS; the grid electrode of the MOS tube P4 connected with the MOS tube N4 is used as a channel selection signal input end of the first phase inverter, and the drain electrode of the MOS tube P4 connected with the MOS tube N4 is used as an output end of the first phase inverter.
The second phase inverter comprises a MOS tube P5, a MOS tube N5 and a diode D2; the anode of the diode D2 is connected with the power supply VDD, and the cathode of the diode D is connected with the source electrode of the MOS tube P5; the grid electrode of the MOS tube P5 is connected with the grid electrode of the MOS tube N5, and the drain electrode is connected with the drain electrode of the MOS tube N5; the source electrode of the MOS tube N5 is connected with a negative power supply VSS; and taking a grid electrode formed by connecting the MOS tube P5 and the MOS tube N5 as an input end of the second phase inverter, and taking a drain electrode formed by connecting the MOS tube P5 and the MOS tube N5 as an output end of the second phase inverter.
The power-off protection circuit for the multiplexer specifically comprises the following components in the working process:
when the power is off, the positive and negative power supplies are grounded equivalently, namely vdd=vss=0v, and the inverter consisting of N4 and P4, N5 and P5 in the buffer circuit does not work.
When the analog input signal S is a positive voltage V1, N6 and N7 are turned off, and a high resistance is provided between V1 and node B. Node B is clamped to VDD by the source-lined parasitic diode of P4, so b=vdd=0v, switch N8 is off, N6, N7, N8 is high-impedance to positive-voltage analog signal V1. V1 is transmitted to node a through P6 which is on, N5 is off because b=0v, and V1 is transmitted to D2 minus terminal because P5 is on, but D2 is reverse biased because vdd=0v, and the paths are all free of leakage, so node a is equal to V1 and P8 channel is off. Similar to P6, P7 conduction transmits V1 to the substrates of P6, P7, P8, the source-to-liner parasitic diode positive and negative terminals are equipotential, and no leakage occurs. To sum up, when the power is off and S is positive voltage V1, the switch is high-resistance and has no leakage.
When the analog input signal S is a negative voltage V2, P6 and P7 are turned off, and a high resistance is provided between V2 and node a. Node a is clamped to VSS by the source-liner parasitic diode of N5, so a=vss=0v > V2, switch P8 is off, and P6, P7, P8 are high-impedance to negative-voltage analog signal V2. V2 is transferred to node B through turned on N6, where N4, P4 are turned off, and although N4 drain-liner parasitic diode transfers V2 to the positive terminal of D1, vss=0v so D1 is reversed biased, and none of the paths has leakage, so node B is equal to V2 and N8 channel is turned off. Similar to N6, N7 conduction transmits V2 to the substrates of N6, N7 and N8, and the positive and negative terminals of the source-liner parasitic diode are equipotential and have no electric leakage. To sum up, when the power is off and S is a negative voltage V2, the switch is high-resistance and has no leakage.
In summary, the invention discloses a power-off protection circuit for a multiplexer, which can eliminate abnormal channel current and parasitic diode current generated by the multiplexer during power off and improve the reliability of the circuit. The multiplexer and the post-stage load are effectively protected, and the reliability of the circuit and the system application is improved.
While the foregoing is directed to embodiments, aspects and advantages of the present invention, other and further details of the invention may be had by the foregoing description, it will be understood that the foregoing embodiments are merely exemplary of the invention, and that any changes, substitutions, alterations, etc. which may be made herein without departing from the spirit and principles of the invention.
Claims (5)
1. A power-down protection circuit for a multiplexer, comprising: the circuit comprises a buffer circuit, a power-off protection circuit and a switch circuit; the output end of the buffer circuit is connected with the switch circuit, and the output end of the power-off protection circuit is connected with the switch circuit; the power-off protection circuit is characterized by comprising: MOS tube P6, MOS tube P7, MOS tube N6, MOS tube N7, diode D3 and diode D4; the switching circuit comprises a MOS tube P8 and a MOS tube N8;
the output of the power-off protection circuit is connected with the switching circuit and comprises: the grid electrodes of the MOS tube P6 and the MOS tube P7 are connected with a power supply VDD, the drain electrode of the MOS tube P6 is connected with the grid electrode of the MOS tube P8, the source electrode of the MOS tube P6 is respectively connected with the source electrode of the MOS tube P8 and the drain electrode of the MOS tube N8, and the substrate of the MOS tube P6 is respectively connected with the source electrode of the MOS tube P7, the substrate of the MOS tube P7 and the substrate of the MOS tube P8; the source electrode of the MOS tube P7 is connected with the cathode of the diode D3, the drain electrode is connected with the source electrode of the MOS tube P8, and the substrate is connected with the substrate of the MOS tube P8; the anode of the diode D3 is connected with a power supply VDD; the grid electrode of the MOS tube N6 is connected with the grid electrode of the MOS tube N7 and then connected with a negative power supply VSS; the drain electrode of the MOS tube N6 is respectively connected with the drain electrode of the MOS tube N7 and the drain electrode of the MOS tube N8, the source electrode is connected with the grid electrode of the MOS tube N8, and the substrate is connected with the anode of the diode D4; the drain electrode of the MOS tube N7 is connected with the drain electrode of the MOS tube N8, and the source electrode is connected with the anode of the diode D4; the cathode of the diode D4 is connected with a negative power supply VSS; the source electrode of the MOS tube P8 is connected with the drain electrode of the MOS tube N8, the drain electrode is connected with the source electrode of the MOS tube N8, and the substrate of the MOS tube N8 is connected with the anode of the diode D4.
2. The power down protection circuit for a multiplexer of claim 1, wherein the buffer circuit comprises a first inverter and a second inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the first phase inverter and the output end of the second phase inverter are respectively connected with the switch circuit to obtain the buffer circuit.
3. The power-down protection circuit for a multiplexer of claim 2, wherein the first inverter comprises a MOS transistor P4, a MOS transistor N4, and a diode D1; the source electrode of the MOS tube P4 is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the MOS tube N4, and the grid electrode is connected with the grid electrode of the MOS tube N4; the source electrode of the MOS transistor N4 is connected with the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected with the negative power supply VSS; the grid electrode of the MOS tube P4 connected with the MOS tube N4 is used as a channel selection signal input end of the first phase inverter, and the drain electrode of the MOS tube P4 connected with the MOS tube N4 is used as an output end of the first phase inverter.
4. The power-down protection circuit for a multiplexer of claim 2, wherein the second inverter comprises a MOS transistor P5, a MOS transistor N5, and a diode D2; the anode of the diode D2 is connected with the power supply VDD, and the cathode of the diode D is connected with the source electrode of the MOS tube P5; the grid electrode of the MOS tube P5 is connected with the grid electrode of the MOS tube N5, and the drain electrode is connected with the drain electrode of the MOS tube N5; the source electrode of the MOS tube N5 is connected with a negative power supply VSS; and taking a grid electrode formed by connecting the MOS tube P5 and the MOS tube N5 as an input end of the second phase inverter, and taking a drain electrode formed by connecting the MOS tube P5 and the MOS tube N5 as an output end of the second phase inverter.
5. A power down protection circuit for a multiplexer as recited in claim 1, wherein the buffer circuit is coupled to the switching circuit comprising: the output end of the first phase inverter of the buffer circuit is connected with the grid electrode of the MOS tube N8 of the switch circuit, and the output end of the second phase inverter of the buffer circuit is connected with the grid electrode of the MOS tube P8 of the switch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210056760.9A CN114389232B (en) | 2022-01-18 | 2022-01-18 | Power-off protection circuit for multiplexer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210056760.9A CN114389232B (en) | 2022-01-18 | 2022-01-18 | Power-off protection circuit for multiplexer |
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| Publication Number | Publication Date |
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| CN114389232A CN114389232A (en) | 2022-04-22 |
| CN114389232B true CN114389232B (en) | 2023-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210056760.9A Active CN114389232B (en) | 2022-01-18 | 2022-01-18 | Power-off protection circuit for multiplexer |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0157220A1 (en) * | 1984-03-08 | 1985-10-09 | FISHER & PAYKEL LIMITED | Improvements in or relating to electronic control circuits |
| CN1089043A (en) * | 1992-09-21 | 1994-07-06 | 株式会社东芝 | Power transistor overcurrent protection circuit |
| KR20000010965A (en) * | 1996-05-17 | 2000-02-25 | 데이비드 에스. 호이리스 | Cmos output driver with p-channel substrate tracking for cold spare capability |
| CN102394490A (en) * | 2011-09-05 | 2012-03-28 | 上海贝岭股份有限公司 | Protective circuit for analogue switch |
| CN103166616A (en) * | 2011-12-13 | 2013-06-19 | 无锡华润矽科微电子有限公司 | Simulative switch circuit structure |
| CN111585266A (en) * | 2020-04-20 | 2020-08-25 | 上海泓语电气技术有限公司 | DC distribution electronic soft start switch |
-
2022
- 2022-01-18 CN CN202210056760.9A patent/CN114389232B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0157220A1 (en) * | 1984-03-08 | 1985-10-09 | FISHER & PAYKEL LIMITED | Improvements in or relating to electronic control circuits |
| CN1089043A (en) * | 1992-09-21 | 1994-07-06 | 株式会社东芝 | Power transistor overcurrent protection circuit |
| KR20000010965A (en) * | 1996-05-17 | 2000-02-25 | 데이비드 에스. 호이리스 | Cmos output driver with p-channel substrate tracking for cold spare capability |
| CN102394490A (en) * | 2011-09-05 | 2012-03-28 | 上海贝岭股份有限公司 | Protective circuit for analogue switch |
| CN103166616A (en) * | 2011-12-13 | 2013-06-19 | 无锡华润矽科微电子有限公司 | Simulative switch circuit structure |
| CN111585266A (en) * | 2020-04-20 | 2020-08-25 | 上海泓语电气技术有限公司 | DC distribution electronic soft start switch |
Non-Patent Citations (1)
| Title |
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| 机器人"章鱼保罗"的设计与实现;张晴;杨桂考;罗凯;;数字技术与应用(第11期);全文 * |
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