CN106067805B - Clock signal level shift circuit - Google Patents
Clock signal level shift circuit Download PDFInfo
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- CN106067805B CN106067805B CN201610631926.XA CN201610631926A CN106067805B CN 106067805 B CN106067805 B CN 106067805B CN 201610631926 A CN201610631926 A CN 201610631926A CN 106067805 B CN106067805 B CN 106067805B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The invention discloses a clock signal level shift circuit, which comprises an MOS (metal oxide semiconductor) switch circuit and a working circuit, wherein the working circuit comprises one or more load driving circuits for realizing level shift, the MOS switch circuit is respectively connected with each load driving circuit, and the equivalent capacitance of a load connected with the load driving circuits can not influence the MOS tube switch circuit. The invention provides a clock signal level shift circuit, which separates an MOS tube switch circuit from a working circuit for driving a load, so that the level shift is realized, the influence of an equivalent capacitor in the load on the MOS tube switch circuit can be avoided, and the whole clock signal level shift circuit works more stably.
Description
Technical Field
The invention relates to a clock signal level shift circuit.
Background
In a multi-power-supply analog signal processing circuit, a clock control signal is often required to be level shifted to realize control of analog signals with different common-mode levels, as shown in fig. 1, in a conventional level shift circuit, two capacitance level shift capacitors C10 and C20, two MOS transistors M10 and M20, and an inverter are used to form a level shift circuit, one end of a load is directly connected to a common end of drains of the capacitors C20 and M20, and the other end of the load is grounded to realize level shift, however, when an equivalent capacitance of the load Cload is large, a voltage division condition with the capacitor C20 exists, which causes a reduction in the level amplitude of the common end of the drains of the capacitors C20 and M20, and a poor conduction effect of the M1 transistor occurs under severe conditions, so that the circuit fails.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a clock signal level shift circuit.
The purpose of the invention is realized by the following technical scheme: a clock signal level shift circuit comprises an MOS switch circuit and a working circuit, wherein the working circuit comprises one or more load driving circuits for realizing level shift, and the MOS switch circuit is respectively connected with each load driving circuit;
the MOS switching circuit comprises a first MOS tube, a second MOS tube, a first capacitor, a second capacitor and an inverter; the source electrodes of the first MOS tube and the second MOS tube are connected with a first level end; the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, and the drain electrode of the first MOS tube is connected with the grid electrode of the second MOS tube; the drain electrode of the first MOS tube is also connected with a clock signal end through a first capacitor; the input end of the phase inverter is connected with the clock signal end, and the output end of the phase inverter is connected with the drain electrode of the second MOS tube through a second capacitor;
the load driving circuit comprises a third MOS tube and a third capacitor; and the source electrode of the third MOS tube is connected with the drive level end, the grid electrode of the third MOS tube is connected with the drain electrode of the first MOS tube, and the drain electrode of the third MOS tube is connected with the output end of the phase inverter through a third capacitor.
In the load driving circuit, a level after displacement is output by a drain electrode of a third MOS tube and a common end of a third capacitor for a load to work, a drain electrode of the third MOS tube M3 and the common end of the third capacitor C3 are connected with a first end of the load, a second end of the load is grounded, and a second end of the load is grounded.
When the working circuit comprises a plurality of load driving circuits, each load driving circuit is the same.
When the working circuit comprises a plurality of load driving circuits, each load driving circuit is connected with different driving level ends.
The beneficial effects of the invention are: this application separates MOS pipe switch circuit and drive load's work circuit for when realizing level shift, also can avoid equivalent capacitance in the load to MOS pipe switch circuit's influence, whole clock signal's level shift circuit work is more stable.
Drawings
FIG. 1 is a schematic diagram of a conventional level shifting circuit;
FIG. 2 is a schematic circuit diagram of a first embodiment of the present invention;
FIG. 3 is a graph showing the level shift effect according to one embodiment;
FIG. 4 is a schematic circuit diagram of a second embodiment of the present invention;
fig. 5 is a diagram illustrating the level shift effect according to the second embodiment of the present invention.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
A clock signal level shift circuit comprises an MOS switch circuit and a working circuit, wherein the working circuit comprises one or more load driving circuits for realizing level shift, and the MOS switch circuit is respectively connected with each load driving circuit;
the MOS switching circuit comprises a first MOS tube M1, a second MOS tube M2, a first capacitor C1, a second capacitor C2 and an inverter F; the source electrodes of the first MOS transistor M1 and the second MOS transistor M2 are connected with a first level end V1; the grid electrode of the first MOS tube M1 is connected with the drain electrode of the second MOS tube M2, and the drain electrode of the first MOS tube M1 is connected with the grid electrode of the second MOS tube M2; the drain electrode of the first MOS tube M1 is also connected with a clock signal end CLK through a first capacitor C1; the input end of the phase inverter F is connected with a clock signal end CLK, and the output end of the phase inverter F is connected with the drain electrode of a second MOS tube M2 through a second capacitor C2;
the load driving circuit comprises a third MOS transistor M3 and a third capacitor C3; the source electrode of the third MOS tube M3 is connected with the drive level end, the grid electrode of the third MOS tube M3 is connected with the drain electrode of the first MOS tube M1, and the drain electrode of the third MOS tube M3 is connected with the output end of the phase inverter F through a third capacitor C3.
In the load driving circuit, the level after displacement is output by the drain electrode of the third MOS transistor M3 and the common end of the third capacitor C3 for the load to work, the drain electrode of the third MOS transistor M3 and the common end of the third capacitor C3 are connected with the first end of the load, and the second end of the load is grounded.
As shown in fig. 2, in the first embodiment of the present invention, when the operating circuit includes one load driving circuit, a single level shift circuit is formed.
As shown in fig. 3, in the first embodiment of the present application, the clock signal level of the clock signal terminal CLK is 0 to vdd1, the power supply of the inverter is VDD1, and the output level of the inverter is 0 to vdd1
The clock signal is shifted to the voltage positions of V1-VDD 1+ V1, the obtained signals are S1 and S2, the S1 voltage signal is used for driving the M3 switching tube, the displacement of the output signal S3 of the load driving circuit is realized, and the S3 signal is shifted to the voltage positions of V2-VDD 1+ V2.
In the first embodiment, the first capacitor C1 requires the size of the driven M2/M3 to be very small, so the value of C1 is also small, and the specific value design satisfies the condition C1> (VT × (CS 1))/(VDD 1-VT); here, VT is a threshold voltage of the MOS device, CS1 is a Cds (source-drain capacitance) capacitance including M1, a gate capacitance including M2/M3, a parasitic capacitance after layout, and a value of C1 needs to be set larger;
the second capacitor C2 is required to drive M1, so C2 needs to satisfy the condition C2> (VT (CS 2))/(VDD 1-VT), where VT is the threshold voltage of M1, CS1 is the gate capacitor including M1, the Cds capacitor of M2, the parasitic capacitor after layout, and the value of C2 needs to be set larger.
As shown in FIG. 3, theoretically, the S3 signal is shifted to V2 to VDD1+ V2 voltage positions where it is reasonable.
In practice, the capacitor C3 is required to drive Cload (here, cload is the equivalent capacitance of the load circuit), and here, the output signal amplitude VX = (C3 × VDD 1)/(C3 + CS3+ Cload); the setting of C3 needs to meet the requirement of the amplitude of the load clock signal, if the requirement of the amplitude of the signal required to be output is VX, C3> (VX (CS 3+ Cload))/(VDD 1-VX) is required; the requirement of different output amplitudes can also be realized by adjusting the setting of C3 to limit the highest level of the S3 limit.
Because the MOS switch M1/M2/M3 is required to meet the compensation requirement of charge leakage, the charge leakage is very small, and the size of the M1/M2/M3 can be made very small.
As shown in fig. 4, in the second embodiment of the present application, when the operating circuit includes a plurality of load driving circuits, a multilevel shift circuit is formed; each load driving circuit is identical, and at the same time, each load driving circuit is connected to a driving level terminal of a different level.
Different load driving circuits are controlled by the driving level end to obtain different level displacement results so as to supply corresponding loads to work, and the level displacement results are shown in fig. 5, so that when one load driving circuit is connected with the driving level end with the level of V2, the level is displaced to V2-VDD 1+ V2, and a signal s3 is obtained to drive the corresponding loads to work; when the other load driving circuit is connected with a driving level end and is Vn, the level is shifted to Vn-VDD 1+ Vn, a signal sn is obtained, and the corresponding load is driven to work.
Claims (1)
1. A clock signal level shifting circuit, characterized by: the circuit comprises an MOS switch circuit and a working circuit, wherein the working circuit comprises one or more load driving circuits for realizing level displacement, and the MOS switch circuit is respectively connected with each load driving circuit;
the MOS switching circuit comprises a first MOS tube, a second MOS tube, a first capacitor, a second capacitor and an inverter; the source electrodes of the first MOS tube and the second MOS tube are connected with a first level end; the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, and the drain electrode of the first MOS tube is connected with the grid electrode of the second MOS tube; the drain electrode of the first MOS tube is also connected with a clock signal end through a first capacitor; the input end of the phase inverter is connected with the clock signal end, and the output end of the phase inverter is connected with the drain electrode of the second MOS tube through a second capacitor;
the load driving circuit comprises a third MOS tube and a third capacitor; the source electrode of the third MOS tube is connected with the drive level end, the grid electrode of the third MOS tube is connected with the drain electrode of the first MOS tube, and the drain electrode of the third MOS tube is connected with the output end of the phase inverter through a third capacitor; in the load driving circuit, a level after displacement is output by a drain electrode of a third MOS tube and a common end of a third capacitor for the load to work, the drain electrode of the third MOS tube and the common end of the third capacitor C3 are connected with a first end of a load, and a second end of the load is grounded;
when the operating circuit includes a load driving circuit, a single level shift circuit is formed; when the operation circuit includes a plurality of load driving circuits, a multi-level shift circuit is formed, each of the load driving circuits is the same, and at the same time, each of the load driving circuits is connected to a driving level terminal of a different level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610631926.XA CN106067805B (en) | 2016-08-04 | 2016-08-04 | Clock signal level shift circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610631926.XA CN106067805B (en) | 2016-08-04 | 2016-08-04 | Clock signal level shift circuit |
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| CN106067805A CN106067805A (en) | 2016-11-02 |
| CN106067805B true CN106067805B (en) | 2023-04-11 |
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| CN111541444B (en) * | 2020-05-09 | 2021-11-16 | 南京大学 | Multi-level potential shifting circuit based on composite dielectric gate double-transistor photosensitive detector |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6404270B1 (en) * | 2000-11-28 | 2002-06-11 | Cypress Semiconductor Corp. | Switched well technique for biasing cross-coupled switches or drivers |
| JP4193462B2 (en) * | 2002-10-16 | 2008-12-10 | 日本電気株式会社 | Booster circuit |
| JP4116001B2 (en) * | 2005-01-31 | 2008-07-09 | シャープ株式会社 | Level shifter circuit and display element driving circuit using the same |
| US7176742B2 (en) * | 2005-03-08 | 2007-02-13 | Texas Instruments Incorporated | Bootstrapped switch with an input dynamic range greater than supply voltage |
| TWI324443B (en) * | 2006-01-24 | 2010-05-01 | Au Optronics Corp | Transistor level shifter circuit |
| US7696805B2 (en) * | 2007-03-31 | 2010-04-13 | Sandisk 3D Llc | Level shifter circuit incorporating transistor snap-back protection |
| CN101944847B (en) * | 2010-09-07 | 2013-03-20 | 思瑞浦微电子科技（苏州）有限公司 | Bootstrap switch circuit |
| US8975942B2 (en) * | 2012-03-01 | 2015-03-10 | Analog Devices, Inc. | System for a clock shifter circuit |
| CN102723859B (en) * | 2012-06-14 | 2014-07-02 | 浙江大学 | Charge pump based on voltage multiplier cascade connection |
| US9634559B2 (en) * | 2014-02-07 | 2017-04-25 | The Hong Kong University Of Science And Technology | Charge pumping apparatus for low voltage and high efficiency operation |
| JP6354937B2 (en) * | 2014-03-20 | 2018-07-11 | セイコーエプソン株式会社 | Drive circuit, integrated circuit device, and charge pump circuit control method |
| CN103997326A (en) * | 2014-06-09 | 2014-08-20 | 上海华力微电子有限公司 | Bootstrap switching circuit with constant on resistance |
| CN105634461B (en) * | 2015-12-28 | 2018-11-20 | 上海数明半导体有限公司 | A kind of level shift circuit |
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