CN118041327A

CN118041327A - Integrated bootstrap switching circuit suitable for high-voltage GaN half-bridge gate driving chip

Info

Publication number: CN118041327A
Application number: CN202410258339.5A
Authority: CN
Inventors: 明鑫; 吴之久; 邵瑞洁; 庄春旺; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2024-03-07
Filing date: 2024-03-07
Publication date: 2024-05-14

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to an integrated bootstrap switch circuit suitable for a GaN half-bridge gate driving chip. The invention satisfies the requirements of the bootstrap capacitor for charging by the power tube under the power tube and supplying power to the bootstrap capacitor when the power tube is on through the time sequence control of the bootstrap large current path. Integrating the off-chip high voltage bootstrap diode into the on-chip provides a substantial improvement in the ease of application design, increasing power density. Meanwhile, the risk of overcharging the bootstrap capacitor is avoided.

Description

Integrated bootstrap switching circuit suitable for high-voltage GaN half-bridge gate driving chip

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to an integrated bootstrap switch circuit suitable for a GaN half-bridge gate driving chip.

Background

At present, a power device made of a third generation wide bandgap semiconductor GaN material plays an increasingly important role in high-speed and high-power electronic applications such as automobile electronics, consumer electronics, data centers, communication power supplies and the like. This presents a significant challenge for the performance, power density, and reliability of the gate drive circuit of the GaN power device.

The bootstrap circuit for supplying power to the high-side floating power supply rail is driven by a conventional GaN half-bridge, and is generally composed of an external discrete high-voltage diode and a small resistor, as shown in fig. 1. If the reverse recovery time of the high-voltage diode is too long, the requirement of the GaN half-bridge in high-frequency application cannot be met. During dead time, the switch node voltage becomes negative, creating a risk of overvoltage.

Thus, to increase power density and facilitate a fast design process of the PCB, reducing additional component overhead, bootstrap diodes may be integrated into the HVIC. However, the low sub-current of the high voltage diode may cause the malfunction of the surrounding circuit, the direct integration of the high voltage diode into the HVIC is not a reasonable method that can be implemented in bulk silicon technology, and as the bus voltage rises, many process platforms have no high voltage diode and have to find other voltage withstanding devices instead. Therefore, in order to avoid the influence of minority carriers, the on-chip circuit is used as a bootstrap diode, namely a bootstrap diode simulator, and the bootstrap charging path is actively controlled, so that the phenomenon that the GaN is damaged by the overcharge of the bootstrap capacitor is prevented, and the on-chip circuit has important significance in the application of high-voltage GaN half-bridge driving.

Disclosure of Invention

The present invention provides an on-chip bootstrap diode simulator, i.e. an on-chip bootstrap switch circuit, suitable for a GaN half-bridge gate driver chip. Together with off-chip bootstrap capacitors, form a bootstrap charging circuit. The circuit has the capability of controlling the bootstrap charging path, and provides a stable power supply for the high-side floating power supply rail under the condition of ensuring the reliability.

The technical scheme of the invention is as follows:

The bootstrap circuit of the on-chip integrated switch comprises a first high-voltage switch tube NLDMOS, a second high-voltage switch tube NLDMOS, a first low-voltage switch PMOS, a bootstrap capacitor, a gate control circuit of the switch tube, a comparator circuit and a logic circuit as shown in fig. 2.

The grid electrode of the first high-voltage switch tube NLDMOS is connected with the output of the grid control circuit, the drain electrode of the first high-voltage switch tube NLDMOS is connected with bootstrap voltage and the upper polar plate of the bootstrap capacitor, the source electrode of the first high-voltage switch tube NLDMOS is connected with power supply voltage through a first low-voltage switch PMOS, and the substrate end of the first high-voltage switch tube NLDMOS is grounded;

the grid electrode of the second high-voltage switch tube NLDMOS is connected with the output of the grid control circuit, the drain electrode of the second high-voltage switch tube NLDMOS is connected with bootstrap voltage and the upper polar plate of the bootstrap capacitor, the source electrode of the second high-voltage switch tube NLDMOS is connected with the non-inverting input end of the comparator module, and the substrate of the second high-voltage switch tube NLDMOS is grounded;

the source electrode of the first low-voltage switch PMOS is connected with the source electrode of the first high-voltage switch tube NLDMOS, the grid electrode of the first low-voltage switch PMOS is connected with the output of the logic circuit, and the drain electrode of the first low-voltage switch PMOS is connected with the power supply voltage;

the lower polar plate of the bootstrap capacitor is connected with the SW point voltage, and the upper polar plate of the bootstrap capacitor is connected with the bootstrap voltage, the drain electrode of the first high-voltage switch tube NLDMOS and the drain electrode of the second high-voltage switch tube NLDMOS;

The control circuit further comprises a first high-voltage switching tube NLDMOS gate control circuit, a second high-voltage switching tube NLDMOS gate control circuit, a comparator circuit and a logic module; the output of the grid control circuit is connected with the grid electrodes of the first high-voltage switching tube NLDMOS and the second high-voltage switching tube NLDMOS; the non-inverting input end of the comparator circuit is connected with the source electrode of the second high-voltage switching tube NLDMOS, and the inverting input end of the comparator circuit is connected with the power supply voltage; the first input of the logic circuit is connected with the output of the comparator circuit, and the output of the logic circuit is connected with the grid electrode of the first low-voltage switch PMOS; a second input of the logic circuit is connected with a low-side driving signal, and a third input of the logic circuit is connected with an enabling signal;

The technical scheme of the grid control circuit is shown in fig. 3, and the grid control circuit comprises a first low-voltage NMOS tube, a second low-voltage NMOS tube, a first capacitor, a second capacitor, a first nano tube, a first inverter and a second inverter;

the input of the first inverter is connected with the input of the grid control circuit, and the output of the first inverter is connected with the lower polar plate of the first capacitor and the input of the second inverter;

The input of the second inverter is connected with the output of the first inverter, and the output of the second inverter is connected with the lower polar plate of the second capacitor and the anode of the first nano tube;

The grid electrode of the first low-voltage NMOS tube is connected with the power supply voltage, the source electrode and the substrate of the first low-voltage NMOS tube are connected with the power supply voltage, and the drain electrode of the first low-voltage NMOS tube is connected with the upper polar plate of the first capacitor and the grid electrode of the second low-voltage NMOS tube;

The grid electrode of the second low-voltage NMOS tube is connected with the drain electrode of the first low-voltage NMOS tube and the upper polar plate of the first capacitor, the source electrode and the substrate of the second low-voltage NMOS tube are connected with the power supply voltage, the drain electrode of the second low-voltage NMOS tube is connected with the upper polar plate of the second capacitor and the cathode of the first nano tube, and the drain electrode of the second low-voltage NMOS tube is connected with the output of the grid control circuit;

The comparator module is a common-gate input comparator to match the common-mode input range of the application; the logic module is composed of digital logic gates such as an inverter, a NAND gate, a NOR gate and the like, the invention is not improved, and unnecessary description of the parts is omitted;

The beneficial effects of the invention are as follows: the time sequence of the bootstrap large current path is controlled to meet the requirements of the bootstrap capacitor for charging by the power tube under the power tube and supplying power to the bootstrap capacitor when the power tube is turned on. Integrating the off-chip high voltage bootstrap diode into the on-chip provides a substantial improvement in the ease of application design, increasing power density. Meanwhile, the risk of overcharging the bootstrap capacitor is avoided.

Drawings

FIG. 1 is a schematic diagram of a conventional half-bridge gate driver chip;

fig. 2 is a schematic diagram of a bootstrap circuit structure of an on-chip integrated switch according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a gate control circuit according to the present invention;

FIG. 4 is a timing diagram of an on-chip bootstrap switch of the present invention;

Fig. 5 is a schematic diagram of the body diode 1 and the body diode 2 forming a back-to-back diode structure to block the dead-zone charging current path.

Detailed Description

For a more complete understanding of the present invention, reference is now made to the accompanying drawings, in which is shown some embodiments of the invention, and it is to be understood that the invention may be embodied in different forms and is not limited to the specific embodiments described herein, but is provided for purposes of illustration of the invention in order that the disclosure may be more thorough and complete.

Fig. 2 shows a bootstrap circuit structure of a GaN half-bridge gate driving chip provided in an embodiment of the present invention, where the bootstrap circuit in the embodiment of the present invention includes: the on-chip bootstrap switch circuit 1 includes, but is not limited to, a GaN half-bridge gate drive on-chip bootstrap switch. The supply voltage VCC serves as an input to the on-chip bootstrap switching circuit 1.

In the present example, the on-chip bootstrap switching circuit 1 includes: the first high-voltage switch tube NLDMOS, the second high-voltage switch tube NLDMOS, the first low-voltage switch PMOS, the grid control circuit 11 of the switch tube, the comparator circuit 12 and the logic circuit 13.

In the embodiment of the present invention, the power supply voltage VCC connects the drain terminal of the first low-voltage switch PMOS and the inverting input terminal of the comparator module 12; the bootstrap voltage VBOOT is connected to the upper plate of the first capacitor CBOOT and is also connected to the drain of the first high-voltage switch tube NLDMOS and the second high-voltage switch tube NLDMOS.

If the conventional off-chip bootstrap circuit of fig. 1 is used. During the high-side GaN device off, low-side GaN device on state, the bootstrap capacitor lower plate, i.e., the switching node SW, is pulled down to approximately 0V by the down-tube, charging the bootstrap capacitor C _B from the fixed low-side power supply V _CC through the high-voltage bootstrap diode D _B, and the maximum voltage across the bootstrap capacitor can be represented by (1-1):

V_CBOOT＝V_DD-V_F-V_R+V_GaN2 (1-1)

wherein V _CBOOT is the voltage difference between the upper and lower polar plates of the bootstrap capacitor, V _CC is a low-side voltage source, V _F is the forward conduction voltage drop of the bootstrap diode, V _R is the voltage difference on the current limiting resistor R ₁, V _GaN2 is the voltage difference when the lower tube is conducted, the voltage difference is negligible in the conduction time of the lower tube, and the conduction voltage difference of the lower tube changes along with the change of the load current in dead time, which can reach-3V to-5V.

If the GaN half-bridge is applied in the CCM operation mode of Buck, in the dead zone, the inductor first extracts charge from the parasitic capacitance Csw of the switch node to follow current, then when the switch node Vsw is pulled down to negative pressure, that is, the GaN drain is pulled down to negative pressure, so that the voltage difference between the gate and the drain is greater than the threshold voltage Vth, and at this time, the gate and the source of GaN are shorted to 0V, which is equivalent to applying positive pressure between the source and the drain of GaN, so as to promote the GaN source-drain exchange, and the two-dimensional electron gas is conducted reversely, so that current flows from the GaN source to the drain. The voltage between the source and drain of the down-tube GaN in the dead zone can be expressed as formula (1-2), where V _GS,ML is 0V in the dead zone time, i _SD is reverse on-current, and R _{on_REV} represents GaN reverse on-resistance as the load current changes, and the reverse on-resistance and forward on-resistance of the GaN transistor in this state are approximately the same.

V_SD,ML＝(V_TH-V_GS,ML)+I_SD·R_{on_REV} (1-2)

In general, the reverse turn-on voltage V _SD of GaN can reach-2V and below, which is several times larger than-0.7V of the silicon power device, and the absolute value of the negative voltage increases with increasing load current. In a silicon MOSFET, a body diode is formed from the channel body to the transistor drain. While the enhancement mode GaN transistor does not have a PN junction, it does conduct in a manner similar to a reverse diode. At this time, the high voltage bootstrap diode D _B still charges the bootstrap capacitor C _B from the fixed low-side power supply V _CC. V _CC the power supply ground is GND, so the maximum voltage established on the bootstrap capacitor during the dead time is the sum of (V _DD-V_F) and the SW negative voltage magnitude. When the dead zone is over, the upper GaN power tube is turned back on, the voltage on C _B may have exceeded the maximum safe operating voltage of the upper tube, damaging the GaN gate.

In order to prevent the phenomenon that the dead zone high negative pressure is overcharged on the bootstrap capacitor and damage the upper power tube, the magnitude of the bootstrap voltage needs to be limited. The invention researches the high-reliability active switch bootstrap technology, and integrates the bootstrap switch in the high-voltage GaN half-bridge gate driving chip to realize the safe power supply of the bootstrap power supply.

The working principle of the invention is as follows: in a normal working mode of the GaN half-bridge gate driving chip, when the lower power tube is in an on state and the enable signal and the low-side driving signal are synchronous to be high, the voltage of a switch node is pulled down by the lower power tube, an on-chip bootstrap switch is started, and a current path is provided for the bootstrap capacitor to charge; when the lower power tube is in an off state and the upper power tube is in an on state, the enabling signal and the low-side driving signal are synchronous to be low, the on-chip bootstrap switch is turned off, and the bootstrap capacitor charging path is cut off. When the upper power tube and the lower power tube are in dead zone states, the bootstrap switch is in an off state, and overvoltage caused by charging of the bootstrap capacitor is avoided.

Referring to fig. 4, the bootstrap circuit of the on-chip integrated switch shown in fig. 2 operates as follows:

at the initial time of t0, the low-side driving signal LIN and the enabling signal EN are low, the on-chip bootstrap switch is not enabled, vgs of the first high-voltage switching tube NLDMOS is 0, and the grid electrode of the first low-voltage switching tube PMOS is VCC and is not opened. The bootstrap voltage is high at this time.

At time t1, the low side drive signal and the enable signal are turned high.

At time t2, after a delay, the output of the gate control circuit 11 turns high, vgs=vcc of the first high-voltage switching transistor NLDMOS and the second high-voltage switching transistor NLDMOS, and the second high-voltage switching transistor is ready to start sampling VBOOT.

During the time t2-t3, VBOOT drops at the same rate as the switch node voltage drops. When the VBOOT voltage is in the high-voltage domain, the second high-voltage switching tube cannot sample the VBOOT; when the VBOOT voltage is reduced to be near the power supply voltage VCC, the second high voltage switching tube can accurately sample the VBOOT, and the comparator judges whether the voltage on the bootstrap capacitor is low enough to start bootstrap charging according to comparison between the sampled value of the VBOOT and the power supply voltage VCC.

At time t3, VBOOT falls to a preset value (near VCC), the comparator module 12 compares the value of VBOOT with VCC, the output analog signal VCMP turns high, VCMP is sent to the logic module 13 for processing, and finally the output V1 of the logic module 13 turns low, and the first low-voltage switch PMOS is turned on.

In the time t3-t4, the first high-voltage switch tube NLDMOS and the first low-voltage switch PMOS are simultaneously turned on, and a bootstrap charging circuit is formed from the power supply voltage VCC to the first capacitor CBOOT, and continuous current exists in the bootstrap charging circuit to charge the bootstrap capacitor so as to meet the energy required by the next turn on of the high-side power tube.

In general, the on-chip bootstrap switch circuit 1 acts as an on-chip "diode emulator", and when the low-side drive signal and the enable signal turn high, the voltage signal of the bootstrap capacitor is detected, and whether the on-chip "diode emulator" acted by the on-chip bootstrap switch circuit 1 is turned on or not is controlled in an active manner, so as to open the bootstrap charging path.

In terms of reliability: in the on-chip bootstrap switch circuit 1 of the embodiment of the invention, only when the low-side driving signal turns high and the bootstrap voltage is detected to be reduced to the safety threshold value, two switches connected in series are started to form a bootstrap current charging path. Otherwise, if VBOOT is not detected, opening the charge path at the high voltage threshold by VBOOT risks current back-flow damaging the low-side circuit.

In dead time, the active switch first high-voltage switch tube NLDMOS and the low-voltage switch are not closed, a body diode 1 is formed by the source electrode of the first high-voltage switch tube NLDMOS and the substrate, the anode of the body diode 1 is the substrate of the first high-voltage switch tube, and the cathode of the body diode 1 is the source electrode of the first high-voltage switch tube. The drain electrode of the first high-voltage switch tube NLDMOS and the substrate form a body diode 2, the anode of the body diode 2 is the substrate of the first high-voltage switch tube, and the cathode of the body diode 2 is the drain electrode of the first high-voltage switch tube. The body diode 1 and the body diode 2 form a back-to-back diode structure, blocking the dead-zone charging current path, as shown in fig. 5.

In summary, compared with the traditional mode of using the off-chip high-voltage diode, the on-chip bootstrap switch circuit provided by the invention has the advantages that the design simplicity of the printed circuit board is greatly improved, the cost of additional elements is reduced, the power density of the half-bridge gate driving chip is improved, the parasitic effect of the printed circuit board is reduced, and the driving chip and power tube sealing scheme is easier to realize. In the aspect of reliability, the on-chip bootstrap switch circuit can avoid the problem that the conventional off-chip high-voltage diode charges the bootstrap capacitor in the dead zone, realizes the safe power supply of the bootstrap power supply, and is suitable for the high-voltage GaN half-bridge gate driving chip.

Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims

1. The integrated bootstrap switch circuit is suitable for a high-voltage GaN half-bridge gate driving chip and is characterized by comprising a first high-voltage switch tube NLDMOS, a second high-voltage switch tube NLDMOS, a first low-voltage switch PMOS, a bootstrap capacitor, a gate control circuit, a comparator circuit and a logic circuit;

The non-inverting input end of the comparator circuit is connected with the source electrode of the second high-voltage switching tube NLDMOS, and the inverting input end of the comparator circuit is connected with the power supply voltage; the first input of the logic circuit is connected with the output of the comparator circuit, and the output of the logic circuit is connected with the grid electrode of the first low-voltage switch PMOS; a second input of the logic circuit is connected with a low-side driving signal, and a third input of the logic circuit is connected with an enabling signal;

The grid control circuit comprises a first low-voltage NMOS tube, a second low-voltage NMOS tube, a first capacitor, a second capacitor, a first nano tube, a first inverter and a second inverter;

the input of the first inverter is connected with the input of the grid control circuit, and the output of the first inverter is connected with the lower polar plate of the first capacitor and the input of the second inverter; the input of the grid control circuit is a low-side driving signal;

The grid electrode of the second low-voltage NMOS tube is connected with the drain electrode of the first low-voltage NMOS tube and the upper polar plate of the first capacitor, the source electrode and the substrate of the second low-voltage NMOS tube are connected with the power supply voltage, the drain electrode of the second low-voltage NMOS tube is connected with the upper polar plate of the second capacitor and the cathode of the first nano tube, and the drain electrode of the second low-voltage NMOS tube is connected with the output of the grid control circuit.