CN113659966A - High-side double-NMOS tube sectional driving system for GaN power tube - Google Patents
High-side double-NMOS tube sectional driving system for GaN power tube Download PDFInfo
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Abstract
The invention discloses a double-NMOS (N-channel metal oxide semiconductor) segmented driving circuit for a high-side GaN power tube, wherein in the starting process of the high-side GaN power tube, a dVS/dt detection circuit is used for detecting a VS (voltage-to-noise ratio) rising slope and converting the VS rising slope into a control voltage Vctr, and the Vctr controls the grid voltage rising speed of a pull-up NMOS (N-channel metal oxide semiconductor) by controlling the output current of a voltage-controlled current source so as to further adjust the grid driving current of the GaN power tube during a miller platform; when the miller platform is detected to be finished, the grid voltage of the pull-up NMOS is raised through the charge pump, the grid driving current of the GaN power tube is maximized, the GaN power tube is completely started, small dv/dt noise is realized, the fast starting speed of the high-side GaN power tube is ensured, the circuit structure is easy to realize, and the occupied area is small.
Description
Technical Field
The invention relates to a drive circuit of a half-bridge drive middle-high side power device, in particular to a double NMOS tube sectional drive system for a high side GaN (potassium nitride) power tube, belonging to the technical field of electronic technology and integrated circuits.
Background
The half-bridge gate driving circuit is widely applied to motor driving, electronic ballasts and DC/DC voltage conversion circuits, and is used for driving two high-side and low-side power switching devices connected in a totem-pole manner to be alternately conducted to realize the regulation of output voltage. Compared with the traditional method of adopting a silicon-based MOSFET as a high-side power tube and a low-side power tube, the GaN power device has the advantages of high switching speed, high working frequency, small on resistance, good temperature characteristic and the like, and is an ideal switching device in a high-frequency, high-power-density and high-efficiency power system.
The ultra-fast turn-on speed of the GaN power device generates higher dVS/dt noise at the floating ground VS, and the high dVS/dt noise causes the high-side driving circuit to generate false response. In the prior art, a high-side driving circuit generally uses a PMOS and NMOS dual-transistor structure to drive a GaN power device, and the driving capability of the high-side driving circuit is proportional to the width-to-length ratio of a PMOS transistor and an NMOS transistor. As the mobility of electrons is about three times of that of holes, the driving capability of the NMOS tube with the same width-length ratio is about three times of that of the PMOS tube, the driving capability can be ensured and the layout area of a chip can be reduced by adopting the double-NMOS tube structure, but when high level is output, the grid-source voltage V of the pull-up NMOS tube in the double-NMOS tube structureGSWill decrease with increasing output voltage, resulting in a decrease of the driving current
The prior art reduces dVS/dt noise by increasing the GaN power device gate resistance to slow its turn-on speed. Increasing the gate resistance, while reducing dVS/dt noise, reduces the turn-off speed of the GaN power device, increases switching losses, and drive current cannot be adjusted as dVS/dt changes, when dVSWhen/dt is small, the driving capability of the driving circuit will be wasted. In the prior art, the dual NMOS transistor driving circuit using the bootstrap diode and the bootstrap capacitor can prevent the pull-up of the gate-source voltage V of the NMOS transistorGSDecreasing as the output voltage increases. The adoption of the bootstrap structure can solve the problem of pull-up NMOS tubeGate source voltage V ofGSThe problem of decreasing as the output voltage increases, but a level shift circuit needs to be added inside the high-side driving circuit, and the integrated bootstrap diode greatly increases the area of the chip.
Disclosure of Invention
In view of the above-mentioned shortcomings in the prior art, the present invention provides a dual NMOS segmented driving system for high-side GaN power transistor to alleviate the contradiction between the turn-on speed of high-side GaN power transistor and dVS/dt noise.
In order to realize the purpose, the invention adopts the following technical scheme: the utility model provides an adopt two NMOS pipe segmentation actuating system of high side of GaN power tube which characterized in that: the method comprises the following steps: dVS/dt detection circuit, voltage-controlled current source, falling edge trigger, inverter INV1, PMOS tube P1, NMOS tube N1, inverting Buffer1, in-phase Buffer2, charge pump capacitor Cp, switch tube Np, and pull-up NMOS tube Nup and pull-down NMOS tube Ndown in the dual NMOS tube;
the input of the inverter INV1 is connected with the output signal V of the high-voltage level shift circuit as the input end of the high-side double NMOS tube segmented driving systemGHThe output end of the inverter INV1 is connected to the gate of the PMOS transistor P1, the gate of the NMOS transistor N1 and the input end of the in-phase Buffer2, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are interconnected and connected to the R end of the falling edge flip-flop, the source of the switch transistor Np and the anode of the body diode Dp parasitized by the switch transistor Np, the cathode of the body diode Dp is connected to the drain of the switch transistor Np and the gate of the pull-up NMOS transistor Nup and one end of the charge pump capacitor Cp, the other end of the charge pump capacitor Cp is connected to the output end of the inverting Buffer1, the input end of the inverting Buffer1 is connected to the output end Q of the falling edge flip-flop, the drain of the pull-up NMOS transistor Nup is connected to the floating power supply VB, the dVS/dt detection circuit is connected between the floating power supply VB and the floating ground VS and the common ground GND, the dVS/dt detection circuit outputs two signals, one output voltage signal Vctr is connected to the input end of the voltage-controlled current source powered by the floating power supply VB, the other output pulse signal Vmp is connected with the input end S of the falling edge trigger, the output current Ictr of the voltage-controlled current source is connected with the source electrode of a PMOS tube P1, and the source electrode of an NMOS tube N1 is connected with the floating ground VSThe output end of the in-phase Buffer2 is connected with the grid of the switch tube Np and the grid of the pull-down NMOS tube Ndown, the source of the pull-down NMOS tube Ndown is connected with the floating ground VS, the source of the pull-up NMOS tube Nup is connected with the drain of the pull-down NMOS tube Ndown and used as the output end of the high-side double-NMOS tube subsection driving system, and the drive signal V is outputHOConnecting high-side GaN power tube MHA gate electrode of (1);
the high-side double NMOS tube sectional driving system is based on a high-side GaN power tube MHAt different stages of the start-up process, in the high-side GaN power tube MHThe grid electrodes use different grid electrode driving currents, and an input signal V of an inverter INV1 is generated during the starting process of a high-side GaN power tubeGHThe voltage-controlled current source output current Ictr sequentially passes through a PMOS tube P1 and a body diode Dp parasitized by a switch tube Np to charge the grid electrode of a pull-up NMOS tube Nup; the voltage change rate of a floating ground VS is detected through an dVS/dt detection circuit, the detected rising slope of the voltage at the VS is converted into a control voltage Vctr to control the magnitude of the output current Ictr of a voltage-controlled current source so as to control the rising speed of the grid voltage of a pull-up NMOS tube Nup, and further the grid driving current of a high-side GaN power tube during the Miller platform period is adjusted; dVS/dt detection circuit's output pulse signal Vmp represents high side GaN power tube Maitreya platform time quantum, the falling edge of pulse signal Vmp represents the end of GaN power tube Maitreya platform, falling edge trigger's output Q control inverting Buffer1 output end overturns, charge pump electric capacity Cp lifts the grid voltage of pulling up NMOS pipe Nup, maximize high side GaN power tube grid drive current, accelerate high side GaN power tube complete opening, when reducing dVS/dt noise, high side GaN power tube M has been acceleratedHThe opening speed of (c).
The dVS/dt detection circuit comprises diodes D1, D2, D3 and D4, resistors R1 and R3, a high-speed comparator CMP and a high-voltage LDMOS; the grid electrode of the high-voltage LDMOS is connected with the source electrode of the LDMOS and grounded, a parasitic capacitor Cpar is connected between the source electrode and the drain electrode of the LDMOS in a bridging mode, the drain electrode of the high-voltage LDMOS is connected with the anode electrode of a diode D1, the cathode electrode of a diode D2 and the cathode electrode of a diode D3, the cathode electrode of a diode D1 is connected with a floating power supply VB, the anode electrode of a diode D2 is a control voltage Vctr output end of a dVS/dt detection circuit and is connected with the inverting end of a high-speed comparator CMP and one end of a resistor R1, the other end of the resistor R1 is connected with the floating power supply VB, the anode electrode of the diode D3 is connected with a floating ground VS and one end of a resistor R3, the other end of the resistor R3 is connected with the cathode electrode of a diode D4 and the inverting end of the high-speed comparator, the anode electrode of the diode D4 is connected with the floating power supply VB, and the output end of the high-speed comparator CMP is a pulse signal Vmp output end of the dVS/dt detection circuit.
During the turn-on process of the high-side GaN power transistor, the floating ground VS voltage rises, the voltage of the floating power supply VB rises, the voltage across the parasitic capacitor Cpar of the high-side LDMOS rises, the resistor R1 and the diode D2 provide a charging path, and the voltage drop across the resistor R1 is measured as dVS/dt:
wherein dVS/dt is the voltage across the high-voltage LDMOS parasitic capacitance Cpar, i.e. the change rate of the noise signal, Cpar represents the capacitance value of the high-voltage LDMOS parasitic capacitance, and R1 represents the resistance value.
The voltage-controlled current source comprises an operational amplifier AMP, an NMOS transistor N2, PMOS transistors P2 and P3 and a resistor R2; the non-inverting end of the operational amplifier AMP is used as the input end of a voltage-controlled current source and is connected with the control voltage Vctr output by the dVS/dt detection circuit, the inverting end of the operational amplifier AMP is connected with one end of a resistor R2 and the source electrode of an NMOS tube N2, the other end of the resistor R2 is connected with a floating ground VS, the output end of the operational amplifier AMP is connected with the grid electrode of the NMOS tube N2, the drain electrode of the NMOS tube N2 is connected with the drain electrode and the grid electrode of a PMOS tube P2 and the grid electrode of the NMOS tube N2, the source electrode of the PMOS tube P2 and the source electrode of the PMOS tube P3 are both connected with a floating power supply VB, and the drain electrode of the PMOS tube P3 outputs the output current Ictr of the voltage-controlled current source.
The voltage-controlled current source regulates and controls an output current Ictr according to a control voltage Vctr output by the dVS/dt detection circuit, wherein the output current Ictr is in negative correlation with dVS/dt, and the expression is as follows:
the invention has the advantages and obvious effects that: compared with the prior art, the double-NMOS tube subsection driving circuit used by the invention can use different grid driving currents according to different stages in the starting process of the high-side GaN power tube, the grid driving current is adjusted according to dVS/dt during the period of the Miller platform, after the Miller platform is detected to be finished, the grid voltage of the pull-up NMOS tube is raised through the charge pump, the grid driving current of the GaN power tube is maximized, the complete starting of the GaN power tube is accelerated, the small dVS/dt noise is realized, the fast starting speed of the high-side GaN power tube is ensured, and meanwhile, the driving circuit of the double-NMOS tube can reduce the layout area of a chip while the driving capability is ensured.
Drawings
FIG. 1 is a topology diagram of the present invention applied to a half-bridge driving circuit;
FIG. 2 is a schematic diagram of a dual NMOS segmented drive circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of the dual NMOS segment driver circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an dVS/dt detection circuit according to an embodiment of the present invention;
FIG. 5 is a voltage waveform diagram of an dVS/dt detection circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a voltage controlled current source according to an embodiment of the present invention;
FIG. 7 is a graph of dVS/dt versus output current for a voltage controlled current source according to an embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, the examples given are intended to illustrate the invention and are not intended to limit the scope of the invention.
Fig. 1 is a topology diagram of the application of the present invention in a half-bridge driving circuit. The high-side double-NMOS tube sectional driving circuit is adopted to replace the high-side double-NMOS tube driving circuit in the prior art, and the rest is the same as the prior art. The input PWM signal firstly generates high-low non-overlapping signals and low-side signals V through a dead zone control circuitGLThe low-side GaN power tube is driven by the low-side drive circuit, and a high-side signal needs to pass through a high-voltage levelThe shift circuit is converted into a high-voltage domain signal and then drives a high-side GaN power tube and a diode D through a high-side double NMOS sectional drive circuitBAnd a capacitor CBForm a floating power supply for supplying power to a high-voltage domain, and the power supply voltage of the drive circuit is VDDThe bus voltage of the high-side and low-side GaN power tubes is VIN。
Referring to fig. 2, the present invention includes dVS/dt detection circuit, voltage controlled current source, falling edge flip-flop, inverter INV1, PMOS transistor P1, NMOS transistor N1, inverting Buffer1, in-phase Buffer2, charge pump capacitor Cp, switch transistor Np, pull-up NMOS transistor Nup, and pull-down NMOS transistor Ndown. Input end of inverter INV1 and high-side driving circuit input end VGHAn output end of the inverter INV1 is connected to a gate of the P1, a gate of the N1 and an input end of the in-phase Buffer2, a drain of the P1 is connected to a drain of the N1, an R end of the falling edge flip-flop and a source end of the switching tube Np, the diode Dp is a body diode of the switching tube Np, the diode Dp is not present in an actual circuit, an anode of the body diode Dp is connected to a source of the switching tube Np, a cathode of the body diode D1 is connected to a drain of the switching tube Np, an output end of the in-phase Buffer2 is connected to a gate of the switching tube Np and a gate of the pull-down NMOS tube Ndown, one output of the dVS/dt detection circuit is connected to an input end of the voltage-controlled current source, the other output of the falling edge flip-flop is connected to an S end, an output end of the voltage-controlled current source is connected to a source of the P1, a Q end of the falling edge flip-flop is connected to an input end of the inverting Buffer1, a charge pump capacitor Cp is connected to an output end of the inverting Buffer1, the other end is connected with the grid electrode of the pull-up NMOS tube Nup and the drain electrode of the switch tube Np, the drain electrode of the pull-up NMOS tube Nup is connected with a floating power supply VB, the source electrode of the pull-down NMOS tube Ndown is connected with the floating ground, and the source electrode of the pull-up NMOS tube Nup and the drain electrode of the pull-down NMOS tube Ndown are connected with a node VHONode VHOAnd the output end of the high-side driving circuit is used for driving the high-side GaN power tube.
In the process of turning on the high-side GaN power transistor, the timing diagram of the signal of the dual NMOS segmented driving circuit is shown in fig. 3, and first, a signal V is inputGHFrom low to high, the node V1 changes from high to low, the node V5 is in phase with the node V1, so that the pull-down NMOS transistor Ndown turns off,the switch transistor Np is turned off, but as the voltage at the node V2 increases, the body diode Dp is turned on to charge the gate parasitic capacitance of the charge pump capacitance Cp and the pull-up NMOS Nup, and the charging path is sequentially the voltage-controlled current source, the P1 transistor, the body diode Dp to the node V4, so that the voltage at the node V4 increases, and then the output voltage V is outputHO(namely the grid voltage of the high-side GaN power tube) is increased and the current I is outputG(i.e., high side GaN power tube gate drive current) increases. When V isHOAfter the voltage of the GaN power tube is increased to the Mailer platform voltage, the floating ground VS starts to rapidly increase, the rising slope of the VS is detected by the dVS/dt detection circuit and converted into a control voltage Vctr, the grid voltage rising speed of the pull-up NMOS tube Nup is controlled by the Vctr through the voltage-controlled current source, the grid driving current of the GaN power tube during the Mailer platform period is further adjusted, a closed-loop negative feedback is formed, and therefore dVS/dt noise is reduced.
Rising from GND to bus voltage V at VSINDuring the period, the dVS/dt detection circuit detects that a short pulse Vmp is correspondingly output, the falling edge of the short pulse Vmp indicates that the Mailer platform is finished, the falling edge trigger detects the falling of Vmp, and then the node V3 jumps to a high level through the inverted Buffer1, because the voltage at the two ends of the capacitor Cp cannot suddenly change, the voltage of the node V4 (the grid of the pull-up NMOS) is lifted to the maximum value by the charge pump capacitor Cp, the grid drive current of the GaN power tube is maximized, the complete opening of the GaN power tube is accelerated, and the contradiction between the fixed grid drive current drive efficiency and dVS/dt noise in the prior art is relieved.
In the turn-off process of the high-side GaN power tube, an input signal VGHThe high level is changed into the low level, the node V5 is changed from the low level into the high level, the switch tube Np is conducted, along with the change of the node V2 from the high level into the low level, the switch tube Np discharges the grid parasitic capacitance of the charge pump capacitor Cp and the pull-up NMOS tube Nup, the discharge path is the node V4, the switch tube Np, the N1 tube and the floating ground VS, the voltage of the node V4 is pulled down to the low level, the pull-up NMOS tube Nup is turned off, simultaneously, as the V2 is changed from the high level into the low level, the falling edge trigger is reset, the node V3 is changed into the low level, the voltage at two ends of the charge pump capacitor Cp is 0, the node V5 is changed into the high level, the pull-down NMOS tube Nup is conducted, and the output voltage V5 is changed into the low levelHOBecomes lowAnd the high-side GaN power tube is turned off.
An dVS/dt detection circuit according to an embodiment of the present invention is schematically illustrated in FIG. 4 and includes a diode D1、D2、D3、 D4Resistors R1, R3, high speed comparator CMP, high voltage LDMOS. The grid electrode and the source electrode of the high-voltage LDMOS are in short circuit with the ground, a parasitic capacitor Cpar is bridged between the drain electrode and the source electrode of the LDMOS, and the drain electrode of the high-voltage LDMOS and a diode D are connected1Anode, diode D2Cathode, diode D3Cathode connected, diode D1Cathode connected to floating power supply VB, diode D1Anode connected to floating ground VS, diode D2The anode is connected with a resistor R1 and a node Vctr, the other end of the resistor R1 is connected with a floating power supply VB, and a diode D4And the resistor R3 is connected between a floating power supply VB and a floating ground VS in series, wherein the series node is Vref, the non-inverting terminal of the high-speed comparator is connected with the node Vref, the inverting terminal of the high-speed comparator is connected with the node Vctr, and the high-speed comparator outputs a pulse signal Vmp.
FIG. 5 shows a voltage waveform diagram of an embodiment of the dVS/dt detection circuit of the present invention, wherein during the turn-on process of the high-side GaN power transistor, the floating ground VS rises rapidly, the floating power VB rises, the voltage across the parasitic capacitor Cpar of the high-voltage LDMOS rises, the resistor R1 and the diode D2Providing a charging path, a charging current proportional to dVS/dt flows through resistor R1, and therefore dVS/dt can be measured in terms of the voltage drop across R1, and node Vctr can be expressed as:
wherein dVS/dt is the voltage change rate of the two ends of the parasitic capacitance of the high-voltage LDMOS, Cpar represents the capacitance value of the parasitic capacitance of the high-voltage LDMOS, and R1 represents the resistance value.
Diode D3For clamping voltage, protecting high-speed comparator and circuit behind it, diode D4A resistor R3 connected between the floating power supply VB and the floating ground VS in series to generate a reference voltage Vref about 0.7V lower than VB, and a pulse signal Vmp is output by comparing the voltage of the node Vref with the voltage of the node Vctr to indicate that the high-side GaN power tube is filledA lux stage time period; when the high-side GaN power tube is turned off and the low-side GaN power tube is turned on, the floating ground VS is rapidly reduced, the voltage at the two ends of the parasitic capacitor Cpar is reduced, and the diode D1A discharge branch is provided for the parasitic capacitance Cpar.
Fig. 6 shows a schematic diagram of an embodiment of the voltage-controlled current source of the present invention, which is composed of an operational amplifier AMP, an NMOS transistor N2, PMOS transistors P2, P3, and a resistor R2; the operational amplifier AMP is connected with a node Vctr in a non-inverting mode, an inverting terminal of the operational amplifier AMP is connected with the upper end of a resistor R2 and the source electrode of an NMOS tube N2, the output end of the operational amplifier AMP is connected with the grid electrode of the NMOS tube N2, the lower end of the resistor R2 is connected with a floating ground VS, the grid electrode and the drain electrode of a PMOS tube P2 are connected with the drain electrode of an NMOS tube N2, the grid electrodes of the PMOS tubes P2 and P3 are connected to form a current mirror, and the drain electrode of the PMOS tube P3 is connected with an output control current Ictr.
The relationship between the output current of the voltage-controlled current source and dVS/dt according to the embodiment of the present invention is shown in FIG. 7. The operational amplifier and the N2 tube form a V-I conversion structure, the voltage-controlled current source can regulate and control the current Ictr according to the Vctr output by the dVS/dt detection circuit, the control current Ictr is negatively correlated with dVS/dt, and the expression is as follows:
wherein dVS/dt is the voltage change rate of the two ends of the parasitic capacitance of the high-voltage LDMOS, Cpar represents the capacitance value of the parasitic capacitance of the high-voltage LDMOS, and R1 and R2 represent resistance values.
The above description is only a preferred example of the present invention and is not limited to the present invention, and various modifications and changes may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A high-side double-NMOS tube subsection driving system for a GaN power tube is characterized in that: the method comprises the following steps: dVS/dt detection circuit, voltage-controlled current source, falling edge trigger, inverter INV1, PMOS tube P1, NMOS tube N1, inverting Buffer1, in-phase Buffer2, charge pump capacitor Cp, switch tube Np, and pull-up NMOS tube Nup and pull-down NMOS tube Ndown in the dual NMOS tube;
the input of the inverter INV1 is connected with the output signal V of the high-voltage level shift circuit as the input end of the high-side double NMOS tube segmented driving systemGHThe output terminal of the inverter INV1 is connected to the gate of the PMOS transistor P1, the gate of the NMOS transistor N1 and the input terminal of the in-phase Buffer2, the drain of the PMOS transistor P1 is interconnected with the drain of the NMOS transistor N1 and is connected to the R terminal of the falling edge flip-flop and the source of the switching transistor Np and the anode of the body diode Dp parasitic to the switching transistor Np, the cathode of the body diode Dp is connected to the drain of the switching transistor Np and to the gate of the pull-up NMOS transistor Nup and to one terminal of the charge pump capacitor Cp, the other terminal of the charge pump capacitor Cp is connected to the output terminal of the inverting Buffer1, the input terminal of the inverting Buffer1 is connected to the output terminal Q of the falling edge flip-flop, the drain of the pull-up NMOS transistor Nup is connected to the floating power supply VB, the dVS/dt detection circuit is connected between the floating power supply VB and the floating ground VS and common ground GND, one output voltage signal Vctr of the dVS/dt detection circuit is connected to the input terminal of the voltage-controlled current source powered by the floating power supply VB, the other path of output pulse signal Vmp is connected with an input end S of the falling edge trigger, the output current Ictr of the voltage-controlled current source is connected with the source electrode of a PMOS tube P1, the source electrode of an NMOS tube N1 is connected with a floating ground VS, the output end of the in-phase Buffer2 is connected with the grid electrode of a switch tube Np and the grid electrode of a pull-down NMOS tube Ndown, the source electrode of the pull-down NMOS tube Ndown is connected with the floating ground VS, the source electrode of the pull-up NMOS tube Nup and the drain electrode of the pull-down NMOS tube Ndown are connected with each other and used as the output end of a high-side double-NMOS tube sectional drive system, and a drive signal V is outputHOConnecting high-side GaN power tube MHA gate electrode of (1);
the high-side double NMOS tube sectional driving system is based on a high-side GaN power tube MHAt different stages of the start-up process, in the high-side GaN power tube MHThe grid electrodes use different grid electrode driving currents, and an input signal V of an inverter INV1 is generated during the starting process of a high-side GaN power tubeGHThe voltage-controlled current source output current Ictr sequentially passes through a PMOS tube P1 and a body diode Dp parasitized by a switch tube Np to charge the grid electrode of a pull-up NMOS tube Nup; tong (Chinese character of 'tong')The over dVS/dt detection circuit detects the voltage change rate at the VS position of the floating ground, converts the rising slope of the detected voltage at the VS position into a control voltage Vctr to control the magnitude of the output current Ictr of the voltage-controlled current source so as to control the rising speed of the grid voltage of the pull-up NMOS tube Nup, and further adjusts the grid driving current of the high-side GaN power tube during the Miller platform; dVS/dt detection circuit's output pulse signal Vmp represents high side GaN power tube Maitreya platform time quantum, the falling edge of pulse signal Vmp represents the end of GaN power tube Maitreya platform, falling edge trigger's output Q control inverting Buffer1 output end overturns, charge pump electric capacity Cp lifts the grid voltage of pulling up NMOS pipe Nup, maximize high side GaN power tube grid drive current, accelerate high side GaN power tube complete opening, when reducing dVS/dt noise, high side GaN power tube M has been acceleratedHThe opening speed of (c).
2. The high-side dual-NMOS transistor segment driving system for the GaN power transistor as claimed in claim 1, wherein: the dVS/dt detection circuit comprises diodes D1, D2, D3 and D4, resistors R1 and R3, a high-speed comparator CMP and a high-voltage LDMOS; the grid electrode of the high-voltage LDMOS is connected with the source electrode of the LDMOS and grounded, a parasitic capacitor Cpar is connected between the source electrode and the drain electrode of the LDMOS in a bridging mode, the drain electrode of the high-voltage LDMOS is connected with the anode electrode of a diode D1, the cathode electrode of a diode D2 and the cathode electrode of a diode D3, the cathode electrode of a diode D1 is connected with a floating power supply VB, the anode electrode of a diode D2 is a control voltage Vctr output end of a dVS/dt detection circuit and is connected with the inverting end of a high-speed comparator CMP and one end of a resistor R1, the other end of the resistor R1 is connected with the floating power supply VB, the anode electrode of the diode D3 is connected with a floating ground VS and one end of a resistor R3, the other end of the resistor R3 is connected with the cathode electrode of a diode D4 and the inverting end of the high-speed comparator CMP, the anode electrode of the diode D4 is connected with the floating power supply VB, and the output end of the high-speed comparator CMP is a pulse signal Vmp output by the dVS/dt detection circuit.
3. The high-side dual-NMOS transistor segment driving system for the GaN power transistor as claimed in claim 1 or 2, wherein: during the turn-on process of the high-side GaN power transistor, the floating ground VS voltage rises, the voltage of the floating power supply VB rises, the voltage across the parasitic capacitor Cpar of the high-side LDMOS rises, the resistor R1 and the diode D2 provide a charging path, and the voltage drop across the resistor R1 is measured as dVS/dt:
wherein dVS/dt is the voltage across the high-voltage LDMOS parasitic capacitance Cpar, i.e. the change rate of the noise signal, Cpar represents the capacitance value of the high-voltage LDMOS parasitic capacitance, and R1 represents the resistance value.
4. The high-side dual-NMOS transistor segment driving system for the GaN power transistor as claimed in claim 1, wherein: the voltage-controlled current source comprises an operational amplifier AMP, an NMOS transistor N2, PMOS transistors P2 and P3 and a resistor R2; the non-inverting end of the operational amplifier AMP is used as the input end of a voltage-controlled current source and is connected with the control voltage Vctr output by the dVS/dt detection circuit, the inverting end of the operational amplifier AMP is connected with one end of a resistor R2 and the source electrode of an NMOS tube N2, the other end of the resistor R2 is connected with a floating ground VS, the output end of the operational amplifier AMP is connected with the grid electrode of the NMOS tube N2, the drain electrode of the NMOS tube N2 is connected with the drain electrode and the grid electrode of a PMOS tube P2 and the grid electrode of the NMOS tube N2, the source electrode of the PMOS tube P2 and the source electrode of the PMOS tube P3 are both connected with a floating power supply VB, and the drain electrode of the PMOS tube P3 outputs the output current Ictr of the voltage-controlled current source.
5. The high-side dual NMOS transistor segment driving system for the GaN power transistor as claimed in claim 1 or 4, wherein: the voltage-controlled current source regulates and controls an output current Ictr according to a control voltage Vctr output by the dVS/dt detection circuit, wherein the output current Ictr is in negative correlation with dVS/dt, and the expression is as follows:
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