CN117879554A

CN117879554A - Control chip, intelligent electronic switch and automobile

Info

Publication number: CN117879554A
Application number: CN202311861375.2A
Authority: CN
Inventors: 宋朋亮; 白文利; 赵朴
Original assignee: Wuxi Wenxian Microelectronics Co ltd
Current assignee: Wuxi Wenxian Microelectronics Co ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-04-12

Abstract

The application provides a control chip, intelligent electronic switch and car, wherein, this control chip includes the power supply pin, the power ground pin, enable the pin, drive setting pin and drive circuit, this drive setting pin is except being used for interior drive circuit, still be used for external first resistance, this first resistance can set up the drive current who flows through drive pin, when first resistance is different promptly, drive current is different, thereby make switch's opening speed and/or turn-off speed by this drive current determine, realized the control to switch's opening speed and/or turn-off speed, guaranteed switch's opening speed and/or turn-off speed can satisfy the requirement.

Description

Control chip, intelligent electronic switch and automobile

Technical Field

The application relates to the technical field of intelligent semiconductor switches, in particular to a control chip, an intelligent electronic switch and an automobile.

Background

The intelligent electronic switch is generally used for coupling a load with a battery, is an electronic element for controlling the on-off of a load circuit, and is widely applied to the fields of automobile electronics, industrial automation, medical equipment and the like. Because the connected loads are various in types and severe in working environment, in practical application, strict requirements are placed on the on-off speed of the power switch in the intelligent electronic switch.

In the prior art, the power switch and the driving circuit for driving the power switch are usually integrated on the same chip, and at this time, the driving circuit drives the power switch to be turned on or off with a fixed driving capability (e.g., maximum driving capability).

However, in order to improve the versatility of the driving circuit, the application of the power switch and the driving circuit disposed on different chips separately is becoming wider, but when the driving circuit matches different power switches, the on speed or the off speed of the power switch may not meet the requirement due to the different input capacitances of the power switch.

Disclosure of Invention

The application provides a control chip, intelligent electronic switch and car for solve the unable problem that satisfies the requirement of opening speed and/or turn-off speed of power switch among the intelligent electronic switch.

In a first aspect, the present application provides a control chip of a power switch, configured to control on-off of the power switch, where the control chip includes a power supply pin, a power ground pin, an enable pin, a drive setting pin, and a drive circuit;

the power supply pin and the power supply grounding pin are used for being electrically connected with a battery, the driving circuit is respectively connected with the driving setting pin, the enabling pin and the driving pin, the driving setting pin is also used for being connected with a first resistor, and the driving pin is also used for being connected with a control end of a power switch; the first resistor is used for setting driving current flowing through the driving pin, the first resistors are different, and the driving current is different;

When the enabling pin receives a first signal, the driving circuit controls the power switch to be turned on, and when the enabling pin receives a second signal, the driving circuit controls the power switch to be turned off, and the turn-on speed and/or turn-off speed of the power switch are/is determined by the driving current.

In one possible design of the first aspect, the driving circuit includes an operational amplifier unit, a first NMOS transistor, and a current conversion unit;

the first input end of the operational amplifier unit is used for accessing reference voltage, the second input end of the operational amplifier unit is connected with the drive setting pin and the second end of the first NMOS tube, the output end of the operational amplifier unit is connected with the control end of the first NMOS tube, the first end of the first NMOS tube is connected with the current conversion unit, and the current conversion unit is also connected with the drive pin;

the operational amplifier unit is used for generating a control signal for conducting the first NMOS tube based on the reference voltage and the first resistor connected with the drive setting pin, the output current of the first NMOS tube is determined based on the reference voltage and the first resistor, the current conversion unit is used for converting the output current of the first NMOS tube into the driving current, and the smaller the first resistor is, the larger the output current of the first NMOS tube is, and the larger the corresponding driving current is.

Optionally, the driving current includes an on current, and the on current flows through the driving pin when the enabling pin receives the first signal, so as to control the on speed of the power switch;

the current conversion unit comprises a first PMOS tube, a second NMOS tube, a third PMOS tube and a fourth PMOS tube;

the first PMOS tube and the first NMOS tube are connected in series, the control end of the first PMOS tube is connected with the control end of the second PMOS tube, the first PMOS tube and the second PMOS tube are also connected with a first power supply end, the second PMOS tube and the second NMOS tube are connected in series, the control end of the second NMOS tube is connected with the control end of the third NMOS tube, the second NMOS tube and the third NMOS tube are also connected with the power supply grounding pin, the third NMOS tube and the third PMOS tube are connected in series, the control end of the third PMOS tube is connected with the control end of the fourth PMOS tube, the third PMOS tube and the fourth PMOS tube are also connected with a second power supply end, and the fourth PMOS tube is also connected with the driving pin;

the output current of the first PMOS tube is equal to the output current of the first NMOS tube, the first mirror current of the second PMOS tube is mirror image with the output current of the first PMOS tube, the output current of the second NMOS tube is equal to the first mirror current of the second PMOS tube, the second mirror current of the third NMOS tube is mirror image with the output current of the second NMOS tube, the output current of the third PMOS tube is equal to the second mirror current of the third NMOS tube, the third mirror current of the fourth PMOS tube is mirror image with the output current of the third PMOS tube, and the starting current is equal to the third mirror current.

Optionally, the driving current includes an off current, and the off current flows through the driving pin when the enabling pin receives a second signal, so as to control the off speed of the power switch;

the current conversion unit comprises a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube;

the control end of the third PMOS tube is also connected with the control end of the fifth PMOS tube, the fifth PMOS tube is also connected with a second power supply end, the fifth PMOS tube and the fourth NMOS tube are connected in series, the control end of the fourth NMOS tube is connected with the control end of the fifth NMOS tube, the fourth NMOS tube and the fifth NMOS tube are also connected with the second end of the power switch, and the fifth NMOS tube is also connected with the driving pin;

the fourth mirror current of the fifth PMOS tube is mirrored with the output current of the third PMOS tube, the output current of the fourth NMOS tube is equal to the fourth mirror current of the fifth PMOS tube, the fifth mirror current of the fifth NMOS tube is mirrored with the output current of the fourth NMOS tube, and the turn-off current is equal to the fifth mirror current.

Optionally, the ratio of the off current to the on current is in the range of (10-1): 1.

Optionally, the ratio of the off current to the on current is equal to the ratio of the voltage variation of the driving pin corresponding to the complete turn-off of the power switch to the on threshold voltage, wherein the voltage variation of the driving pin corresponding to the complete turn-off of the power switch is equal to the difference between the voltage of the driving pin and the on threshold voltage when the power switch is completely turned on.

In another possible design of the first aspect, the drive current includes an off current flowing through the drive pin when the enable pin receives a second signal to control an off speed of the power switch;

the current conversion unit comprises a first PMOS tube, a second NMOS tube, a third PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube;

the first PMOS tube and the first NMOS tube are connected in series, the control end of the first PMOS tube is connected with the control end of the second PMOS tube, the first PMOS tube and the second PMOS tube are also connected with a first power supply end, the second PMOS tube and the second NMOS tube are connected in series, the control end of the second NMOS tube is connected with the control end of the third NMOS tube, the second NMOS tube and the third NMOS tube are also connected with a power supply grounding pin, the third NMOS tube and the third PMOS tube are connected in series, the control end of the third PMOS tube and the control end of the fifth PMOS tube are also connected with a second power supply end, the fifth PMOS tube and the fourth NMOS tube are connected in series, the control end of the fourth NMOS tube and the control end of the fifth NMOS tube are connected, the fourth NMOS tube and the fifth NMOS tube are also connected with the second power switch end, and the fifth NMOS tube are also connected with the fifth power switch pin;

The output current of the first PMOS tube is equal to the output current of the first NMOS tube, the first mirror current of the second PMOS tube is mirror image with the output current of the first PMOS tube, the output current of the second NMOS tube is equal to the first mirror current of the second PMOS tube, the second mirror current of the third NMOS tube is mirror image with the output current of the second NMOS tube, the output current of the third PMOS tube is equal to the second mirror current of the third NMOS tube, the fourth mirror current of the fifth PMOS tube is mirror image with the output current of the third PMOS tube, the output current of the fourth NMOS tube is equal to the fourth mirror current of the fifth PMOS tube, the fifth mirror current of the fifth NMOS tube is mirror image with the output current of the fourth NMOS tube, and the turn-off current is equal to the fifth mirror current.

In a second aspect, the present application provides an intelligent electronic switch, including a control chip, a power supply terminal, a power ground terminal, a load output terminal and a power switch as described in the first aspect and its possible designs;

the power supply end of the power switch is connected with the battery, the control end of the power switch is connected with the driving pin of the control chip, the first end of the power switch is connected with the power supply end or the power ground end, the second end of the power switch is connected with the load output end, the load output end is connected with the load, and the control chip is used for controlling the power switch to be turned on, turned off and/or turned on.

Optionally, the power switch is any one of an NMOS tube, a PMOS tube, and a JFET, and/or the power switch is implemented as a silicon device, silicon carbide, gallium arsenide, or gallium nitride.

Optionally, the power switch is located on a first chip other than the control chip;

the power supply end is a power supply pin, the power supply grounding end is a power supply grounding pin, the load output end is a load output pin, and the load output pin is located on the first chip.

In a third aspect, the present application provides an automobile comprising the first aspect and the possible design of the control chip, or the intelligent electronic switch according to the second aspect;

the power supply circuit comprises a control chip, and is characterized by further comprising a battery, a first resistor, a load and a microprocessor, wherein the positive electrode and the negative electrode of the battery are correspondingly connected with a power supply pin and a power ground pin of the control chip, the first resistor is connected with a drive setting pin of the control chip, the load is connected with the power switch, and the microprocessor is connected with the control chip.

Optionally, the vehicle is an electric vehicle, a hybrid vehicle or a fuel vehicle, and the load includes at least one of a resistive load, an inductive load and a capacitive load.

The control chip, intelligent electronic switch and car that this application provided, on control chip, except including power supply pin, power ground pin, enable pin, drive pin and drive circuit, still add the drive on this control chip and set up the pin, and this drive sets up the pin and still is used for external first resistance, this first resistance can set up the drive current who flows through drive pin, when first resistance is different promptly, drive current is different, thereby make power switch's on-speed and/or off-speed by this drive current determine, realized the control to power switch's on-speed and/or off-speed, guaranteed power switch's on-speed and/or off-speed can satisfy the requirement.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic circuit block diagram of a control chip and peripheral components thereof according to a first embodiment of the present application;

fig. 2 is a schematic circuit block diagram of a control chip and peripheral components thereof according to a second embodiment of the present application;

fig. 3 is a schematic circuit block diagram of a control chip and peripheral components thereof according to a third embodiment of the present application;

Fig. 4 is a schematic circuit block diagram of a control chip and peripheral components thereof according to a fourth embodiment of the present application;

fig. 5 is a schematic circuit block diagram of a control chip and its peripheral components according to a fifth embodiment of the present application.

Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "comprising" and "having" and any variations thereof, as used in the specification, claims and drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or units listed but may alternatively include other steps or units not listed or inherent to such process, method, article, or apparatus.

Furthermore, the terms "first," "second," and "third," etc. are used for distinguishing between different objects and not for describing a particular sequential order. The electrical connection of the present application includes a direct electrical connection and an indirect electrical connection, where an indirect electrical connection refers to that other electronic components, pins, etc. may also exist between two components that are electrically connected. The XX end referred to in this application may or may not be an actual terminal, for example, only one end of a component or one end of a wire. The term "and/or" as referred to herein encompasses three situations, for example, three situations, a and/or B encompasses A, B, A and B.

In recent years, with the growth of automobile markets, particularly the explosion of electric automobile markets, such as electric passenger car markets and electric business car markets, the demands for automobile electronic components are increasing. The electronic component in the automobile with relatively high demands is a relay for switching on or off a load line. However, the relay itself has some drawbacks such as long on and off delay time, expensive and bulky. Thus, with the development of semiconductor technology, intelligent electronic switches have been developed to replace conventional relays, which generally include a power switch and a driving circuit for driving the power switch, which generally controls the on-off of the power switch with a fixed driving capability.

In the related art, as the application of separate deployment of the power switch and the driving circuit is more and more widespread, one driving circuit can be used for matching different power switches, so as to improve the universality of the driving circuit. However, due to the different power switches having different input capacitances, when the driving circuit drives the different power switches with the same driving capability, the on-speed and the off-speed of the different power switches may be different, so that the on-speed and/or the off-speed of some power switches cannot meet the requirements, for example, the intelligent electronic switch cannot pass an electromagnetic compatibility (Electro Magnetic Compatibility, EMC) test, for example, an electromagnetic interference (Electromagnetic Interference, EMI) test or an electromagnetic tolerance (Electro Magnetic Susceptibility, EMS) test when the system is tested.

In view of the above technical problems, the inventor of the present application has provided a technical concept through long-term research, when a driving circuit and a power switch are separately deployed, if the driving circuit can provide different driving capabilities based on the requirements of different power switches, the opening speed and/or the closing speed of the power switch can be controlled, so as to ensure that the opening speed and/or the closing speed of the power switch can meet the requirements.

Based on the technical conception, the embodiment of the application provides a control chip, which can comprise a power supply pin, a power supply grounding pin, an enabling pin, a driving setting pin and a driving circuit, wherein the driving setting pin is used for externally connecting a first resistor except for an internal driving circuit, and the first resistor can set driving current flowing through the driving pin, namely, when the first resistors are different, the driving current is different, so that the opening speed and/or the closing speed of a power switch are determined by the driving current, the control of the opening speed and/or the closing speed of the power switch is realized, and the opening speed and/or the closing speed of the power switch can meet the requirements.

The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

The first embodiment of the application provides a control chip of a power switch, which is used for controlling the on-off of the power switch. Fig. 1 is a schematic circuit block diagram of a control chip and its peripheral components according to a first embodiment of the present application. As shown in fig. 1, the control chip 20 includes a power supply pin VCC, a power ground pin GND, an enable pin EN, a drive pin GATE, a drive set pin RT, and a drive circuit 200.

Referring to fig. 1, a power supply pin VCC and a power ground pin GND are used for electrically connecting with a battery 10, and the driving circuit 200 is respectively connected with a driving setting pin RT, an enabling pin EN and a driving pin GATE, wherein the driving setting pin RT is also used for connecting with a first resistor Rx, and the driving pin GATE is also used for connecting with a control end of a power switch Q1; the first resistor Rx is used for setting the driving current flowing through the driving pin GATE, and the first resistor Rx is different and the driving current is different.

In this embodiment, the driving circuit 200 controls the power switch Q1 to be turned on when the enable pin EN receives the first signal, and controls the power switch Q1 to be turned off when the enable pin EN receives the second signal, and the turn-on speed and/or turn-off speed of the power switch Q1 are determined by the driving current.

Optionally, in fig. 1, the power supply pin VCC is electrically connected to the positive electrode of the battery 10, the power ground pin GND is electrically connected to the negative electrode of the battery 10, and the battery 10 is used for supplying power to the control chip 20, so as to ensure that the control chip 20 can work normally.

In this embodiment, the driving circuit 200 is connected to the control terminal of the power switch Q1 through the driving pin GATE, so that the driving circuit 200 can control the power switch Q1 to be turned on or turned off based on the Input signal received by the enable pin EN. It can be appreciated that the embodiment of the present application is explained with the state change of the driving circuit 200 controlling the power switch Q1, that is, the power switch Q1 may be turned from the off state to the on state, and may be turned from the on state to the off state. Of course, the driving circuit 200 may also control the power switch Q1 to be maintained in the on state when the Input signal received by the enable pin EN is the first signal, and may control the power switch Q1 to be maintained in the off state when the Input signal received by the enable pin EN is the second signal, which is not limited in this embodiment.

Optionally, in this embodiment, the control chip 20 is additionally provided with a driving setting pin RT, and the driving setting pin RT is used for connecting the first resistor Rx, so that a certain relationship exists between the first resistor Rx connected to the driving setting pin RT and the driving current flowing through the driving pin GATE by designing the circuit structure of the driving circuit 200. The specific relationship between the driving current and the first resistor Rx can be referred to the description in the following embodiments, and will not be described herein.

As an example, if the first resistor Rx is used to set the driving current flowing through the driving pin GATE when the power switch Q1 is turned on, the turn-on speed of the power switch Q1 is determined by the driving current. As another example, if the first resistor Rx is used to set the driving current flowing through the driving pin GATE when the power switch Q1 is turned off, the turn-off speed of the power switch Q1 is determined by the driving current. As yet another example, the first resistor Rx may be used to simultaneously set a driving current flowing through the driving pin GATE when the power switch Q1 is turned on and off, and then the turn-on speed and the turn-off speed of the power switch Q1 are both determined by the driving current.

It will be appreciated that the embodiment shown in fig. 1 is illustrated with the power switch Q1 connected as a high side switch (high side switch), i.e., the power switch Q1 is connected between the positive pole of the battery 10 and the load R0. In other embodiments of the present application, the power switch Q1 may also be connected as a low-side switch (low-side switch), that is, the power switch Q1 is connected between the negative electrode of the battery 10 and the load R0, which is not described herein.

Alternatively, in this embodiment, the power switch Q1 may be an N-type Metal-Oxide-semiconductor field-Effect Transistor (NMOS FET, NMOS for short), a PMOS transistor, a junction field-effect transistor (Junction Field Effect Transistor, JFET for short), or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT for short), which is illustrated as an N-type MOS transistor. In yet another possible design of the present embodiment, the power switch Q1 may be implemented as a silicon device, or may be implemented using other semiconductor materials, for example, silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like, and the present embodiment does not limit the expression form of the power switch Q1.

According to the control chip provided by the embodiment of the application, the driving setting pin is additionally arranged and used for being connected with the first resistor, and the first resistor can set the driving current flowing through the driving pin through the driving circuit, so that the opening speed and/or the closing speed of the power switch can be controlled. Therefore, when the control chip is matched with different power switches, the opening speed or the closing speed of the corresponding power switch can meet the requirement by setting different first resistors.

Optionally, a fuse (not shown) may be connected in series between the battery 10 and the power supply pin VCC to prevent a fault caused by excessive current on the line. Other components, such as a reverse connection preventing diode and a current limiting resistor connected in parallel, may be disposed between the power ground pin GND and the negative electrode of the battery 10, so as to improve the stability of the intelligent electronic switch.

Alternatively, in the schematic diagram shown in fig. 1, the connection relationship between the driving circuit 200 and the power supply unit is not shown, but in practical application, the power supply unit may be disposed inside the control chip 20, and the internal power supply unit is connected to the power supply pin VCC, so as to step down the voltage of the power supply pin VCC and provide the voltage to the driving circuit 200 or other circuits. In other embodiments, the control chip 20 may not be provided with a power supply unit, and a voltage reduction unit needs to be disposed between the power supply pin VCC and the positive electrode of the battery 10 to reduce the voltage input to the power supply pin VCC to the rated operating voltage of the control chip 20, so that the voltage at the power supply pin VCC can directly supply power to the circuit inside the control chip 20.

The above embodiments have been generally described with respect to the control chip 20, and the following description will explain the specific implementation of the driving circuit 200 through different embodiments. It will be appreciated that the following embodiments are described on the basis of the embodiment shown in fig. 1 described above.

Fig. 2 is a schematic circuit block diagram of a control chip and its peripheral components according to a second embodiment of the present application. As shown in fig. 2, in the present embodiment, the driving circuit 200 includes an operational amplifier unit DP, a first NMOS transistor N1, and a current converting unit 201.

The first input end of the operational amplifier unit DP is used for accessing the reference voltage Vref, the second input end thereof is connected with the drive setting pin RT and the second end of the first NMOS transistor N1, the output end thereof is connected with the control end of the first NMOS transistor N1, the first end of the first NMOS transistor N1 is connected with the current converting unit 201, and the current converting unit 201 is also connected with the drive pin GATE.

In this embodiment, the operational amplifier unit DP is configured to generate a control signal for turning on the first NMOS transistor N1 based on the reference voltage Vref and the first resistor Rx connected to the drive setting pin RT, the output current of the first NMOS transistor N1 is determined based on the reference voltage Vref and the first resistor Rx, the current converting unit 201 is configured to convert the output current of the first NMOS transistor N1 into the driving current, and the smaller the first resistor Rx, the larger the output current of the first NMOS transistor N1, and the larger the corresponding driving current.

For example, referring to fig. 2, the first input terminal of the op-amp unit DP is a positive terminal, the second input terminal of the op-amp unit DP is an opposite terminal, and the opposite terminal is connected to a driving setting pin RT and the second terminal of the first NMOS transistor N1, the driving setting pin RT is used for being connected to the first resistor Rx, and the output current of the first NMOS transistor N1 can be determined according to the first resistor Rx and the reference voltage Vref, for example, the output current i1 of the first NMOS transistor N1 is equal to the ratio of the reference voltage Vref to the first resistor Rx, i.e. i1=vref/Rx.

In this embodiment of the present application, the first NMOS transistor N1 works in the saturation region, at this time, if the voltage at the positive end of the op-amp unit DP is greater than the voltage at the negative end, the op-amp unit DP will output a high-level control signal, so that the first NMOS transistor N1 is turned on or in a conducting state, and, because the reference voltage Vref remains unchanged, the smaller the first resistor Rx, the larger the output current of the first NMOS transistor N1, and accordingly, the larger the driving current processed by the current conversion unit 201.

In other embodiments of the present application, the first NMOS transistor N1 may be replaced by a PMOS transistor, and at this time, the first input end of the op-amp unit DP may be an inverting end, the second input end thereof may be a non-inverting end, and the driving current flowing through the driving pin GATE may also be changed by adjusting the first resistor Rx, which is not described herein.

Based on the embodiment shown in fig. 2, the following describes how the first resistor Rx affects the turn-on speed and/or turn-off speed of the power switch Q1 by 3 different embodiments, respectively.

As an example, fig. 3 is a schematic circuit block diagram of a control chip and its peripheral components according to a third embodiment of the present application. In this example, the driving current includes an on current Ion flowing through the driving pin GATE when the enable pin EN receives the first signal, the on current Ion being used to control an on speed of the power switch Q1.

Referring to fig. 3, the current conversion unit 201 includes a first PMOS transistor P1, a second PMOS transistor P2, a second NMOS transistor N2, a third NMOS transistor N3, a third PMOS transistor P3, and a fourth PMOS transistor P4. The first PMOS tube P1 and the first NMOS tube N1 are connected in series, the control end of the first PMOS tube P1 is connected with the control end of the second PMOS tube P2, the first PMOS tube P1 and the second PMOS tube P2 are also connected with the first power supply end, the second PMOS tube P2 and the second NMOS tube N2 are connected in series, the control end of the second NMOS tube N2 is connected with the control end of the third NMOS tube N3, the second NMOS tube N2 and the third NMOS tube N3 are also connected with the power supply grounding pin GND, the third NMOS tube N3 and the third PMOS tube P3 are connected in series, the control end of the third PMOS tube P3 is connected with the control end of the fourth PMOS tube P4, the third PMOS tube P3 and the fourth PMOS tube P4 are also connected with the second power supply end, and the fourth PMOS tube P4 is also connected with the driving pin GATE.

In this embodiment, based on the circuit connection relationship shown in fig. 3, the output current of the first PMOS transistor P1 is equal to the output current of the first NMOS transistor N1, the first mirror current of the second PMOS transistor P2 is a mirror image of the output current of the first PMOS transistor P1, the output current of the second NMOS transistor N2 is equal to the first mirror current of the second PMOS transistor P2, the second mirror current of the third NMOS transistor N3 is a mirror image of the output current of the second NMOS transistor N2, the output current of the third PMOS transistor P3 is equal to the second mirror current of the third NMOS transistor N3, the third mirror current of the fourth PMOS transistor P4 is a mirror image of the output current of the third PMOS transistor P3, and the on current Ion is equal to the third mirror current.

Optionally, in this embodiment, the first power supply terminal is a power supply terminal inside the control chip, and a voltage of the first power supply terminal is generally smaller than a voltage of the power supply terminal VCC. When the power switch Q1 is an NMOS transistor and is connected to a high-side switch, the second power supply end connected to the third PMOS transistor P3 and the fourth PMOS transistor P4 is an output end of a boost circuit (not shown in the figure), an input end of the boost circuit may be a power supply pin VCC, and a main function of the boost circuit is to boost a driving capability of the driving circuit and to boost a voltage at the GATE of the driving pin, so that the power switch Q1 can be turned on and turned on. For example, the boost circuit is illustrated as a Charge Pump (CP) circuit, and in fig. 3, the second power supply terminal is identified by CP.

It can be appreciated that in other embodiments of the present application, when the power switch Q1 is a PMOS transistor or the power switch Q1 is an NMOS transistor and is connected to be a low-side switch, the second power supply terminal may be an internal power supply terminal that is equipotential with the power supply pin VCC, which is not described herein.

In one possible design, it is assumed that the ratio of the output current i1 of the first PMOS transistor P1 to the first image current i2 of the second PMOS transistor P2 is 1:k1, the ratio of the output current i2 of the second NMOS transistor N2 to the second image current i3 of the third NMOS transistor N3 is 1:k2, and the ratio of the output current i3 of the third PMOS transistor P3 to the third image current i4 of the fourth PMOS transistor P4 is 1:k3, so that if the output current of the first NMOS transistor N1 is i1, the third image current i4 of the fourth PMOS transistor P4 is equal to k1 x k2 x k3 x Vref/Rx. Therefore, when the enable pin EN receives the first signal, the on current ion=k1×k2×k3×vref/Rx flowing through the driving pin GATE can be changed by replacing the first resistor Rx or adjusting the resistance value of the first resistor Rx, so that the on speed of the power switch Q1 can be controlled. Wherein, k1, k2, k3, etc. can be set according to actual requirements, and will not be described herein.

Optionally, in this embodiment, the circuit conversion unit 201 may further include an on switch, where the on switch may include a switch M1 connected to an output terminal of the current conversion unit 201, and may also include at least one switch connected inside the current conversion unit 201, for example, a switch M3 connected between the second power supply terminal and a control terminal of the fourth PMOS transistor P4. The on-switch is illustrated in fig. 3 as including switch M1 and switch M3. In fig. 3, when the enable pin EN receives the first signal, the switch M1 is turned on and the switch M3 is turned off.

In other embodiments of the present application, the on switch may further include other switches connected inside the current conversion unit 201, for example, a switch connected between the first power supply terminal VDD and the first PMOS transistor P1 and/or the second PMOS transistor P2, and/or a switch connected between the second power supply terminal and the third PMOS transistor P3, and/or a switch connected between the power ground pin GND and the second NMOS transistor N2 and/or the third NMOS transistor N3, which are not limited in this application.

In this embodiment, when the control chip matches different power switches, the on current flowing through the driving pin may be set through the first resistor, so as to control the on speed of the power switch, so as to ensure that the on speed of the power switch can meet the requirement.

Fig. 4 is a schematic circuit block diagram of a control chip and peripheral components thereof according to a fourth embodiment of the present application, based on the embodiment shown in fig. 3. In this example, the driving current further includes an off current Ioff flowing through the driving pin GATE when the enable pin EN receives the second signal to control the off speed of the power switch Q1.

As shown in fig. 4, in the present embodiment, the current conversion unit 201 includes a fifth PMOS transistor P5, a fourth NMOS transistor N4, and a fifth NMOS transistor N5.

The control end of the third PMOS transistor P3 is further connected to the control end of the fifth PMOS transistor P5, the fifth PMOS transistor P5 is further connected to the power supply pin VCC, the fifth PMOS transistor P5 and the fourth NMOS transistor N4 are connected in series, the control end of the fourth NMOS transistor N4 is connected to the control end of the fifth NMOS transistor N5, the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are further connected to the second end of the power switch Q1, and the fifth NMOS transistor N5 is further connected to the driving pin GATE.

In this embodiment, based on the circuit connection relationship shown in fig. 4, the fourth mirror current of the fifth PMOS transistor P5 is mirrored with the output current of the third PMOS transistor P3, the output current of the fourth NMOS transistor N4 is equal to the fourth mirror current of the fifth PMOS transistor P5, the fifth mirror current of the fifth NMOS transistor N5 is mirrored with the output current of the fourth NMOS transistor N4, and the off current Ioff is equal to the fifth mirror current.

In this embodiment, on the basis that the ratio of the output current i1 of the first PMOS transistor P1 to the first image current i2 of the second PMOS transistor P2 is 1:k1, the ratio of the output current i2 of the second NMOS transistor N2 to the second image current i3 of the third NMOS transistor N3 is 1:k2, the ratio of the output current i3 of the third PMOS transistor P3 to the third image current i4 of the fourth PMOS transistor P4 is 1:k3, the ratio of the output current i3 of the third PMOS transistor P3 to the fourth image current i5 of the fifth PMOS transistor P5 is 1:k4, and the ratio of the output current i5 of the fourth NMOS transistor N4 to the fifth image current i6 of the fifth NMOS transistor N5 is 1:k5, so that if the output current of the first NMOS transistor N1 is i1, the fifth image current i6 of the fifth NMOS transistor N5 is equal to k1×k2×k4×k5/Vref. Therefore, when the enable pin EN receives the second signal, the off current ioff=k1×k2×k4×k5×vref/Rx flowing through the drive pin GATE can be changed by replacing the first resistor Rx or adjusting the resistance value of the first resistor Rx, so that the off speed of the power switch Q1 can be controlled. Wherein, k1, k2, k4, k5, etc. can be set according to actual requirements, and will not be described herein.

Optionally, in this embodiment, the circuit conversion unit 201 may further include an off switch, where the off switch may include a switch M2 connected to an output terminal of the current conversion unit 201, and may further include at least one switch connected inside the current conversion unit 201, for example, a switch M4 connected between a second terminal of the power switch Q1 and a control terminal of the fifth NMOS transistor N5. The off switch is illustrated in fig. 4 as including switch M2 and switch M4. In fig. 4, when the enable pin EN receives the second signal, the switch M2 is turned on and the switch M4 is turned off.

In other embodiments, the turn-off switch may further include a switch connected between the first power supply terminal VDD and the first PMOS transistor P1 and/or the second PMOS transistor P2, and/or a switch connected between the power ground pin GND and the second NMOS transistor N2 and/or the third NMOS transistor N3, and/or a switch connected between the second power supply terminal and the third PMOS transistor P3 and/or the fifth PMOS transistor P5, and/or a switch connected between the second terminal of the power switch Q1 and the fourth NMOS transistor N4, which is not limited in this application.

It can be understood that, in this embodiment, for a certain control chip 20, the internal structure of the control chip 20 has been determined that, if the first resistor Rx is replaced or the resistance value of the first resistor Rx is adjusted, the third mirror current i4 of the fourth PMOS transistor P4 and the fifth mirror current i6 of the fifth NMOS transistor N5 are changed at the same time, that is, when the enable pin EN receives the first signal, the on current Ion flowing through the driving pin GATE is changed, so that the on speed of the power switch Q1 is changed, and when the enable pin EN receives the second signal, the off current Ioff flowing through the driving pin GATE is changed, so that the off speed of the power switch Q1 is changed. Therefore, in the embodiment of the present application, in order to balance the on speed and the off speed of the power switch Q1, when designing the control chip 20, by setting the relationship of k3 and (k4+k5), a ratio range of the off current Ioff to the on current Ion may be set, for example, the ratio range of the off current Ioff to the on current Ion is (10 to 1): 1.

Optionally, the ratio of the off current Ioff to the on current Ion may be 10:1,9:1,8:1,7:1,6:1,5:1,4:1,3:1,2:1,1:1, etc., however, in other embodiments of the present application, the ratio of the off current Ioff to the on current Ion may be other values, which is not limited herein.

As an example, the ratio of the off current Ioff to the on current Ion is equal to the ratio of the voltage variation of the drive pin GATE corresponding to the power switch Q1 being completely turned off to the on threshold voltage, wherein the voltage variation of the drive pin GATE corresponding to the power switch Q1 being completely turned off is equal to the difference between the voltage of the drive pin GATE and the on threshold voltage when the power switch Q1 is completely turned on.

In practical application, when the power switch Q1 is turned from the off state to the on state, the GATE-source variation V1 of the power switch Q1 is equal to the on threshold voltage Vth, that is, the voltage of the driving pin GATE increases from 0V to the on threshold voltage Vth, so that when the power switch Q1 is turned on, the voltage variation V1 of the driving pin GATE is equal to the on threshold voltage Vth; since the gate-source voltage of the power switch Q1 is equal to the voltage of the power supply terminal (e.g., VCC) to which the power switch Q1 is connected when the power switch Q1 is fully turned on, and the gate-source voltage of the power switch Q1 is maximally equal to the on threshold voltage Vth when the power switch Q1 is turned off, if the power switch Q1 is turned from the on state to the off state, the gate-source variation V2 of the power switch Q1 is equal to the difference between the voltage VCC of the power supply terminal and the on threshold voltage Vth. Since the input capacitance C between the gate and the source of the power switch Q1 is unchanged, according to the charge amount formula i×t=c×v=q, if the on time ton is to be equal to the off time toff, c×v1/ion=c×v2/Ioff, i.e. Ioff/ion=v2/V1.

In this embodiment, when the control chip matches different power switches, the on current and the off current flowing through the driving pin can be set through the first resistor, so that the on speed and the off speed of the power switch can be controlled, and on the basis that the on speed and the off speed of the power switch are ensured to meet the requirements, the peripheral circuit of the control chip is simple, and the cost is low.

As yet another example, fig. 5 is a schematic circuit block diagram of a control chip and its peripheral components according to a fifth embodiment of the present application. As shown in fig. 5, the driving current includes an off current Ioff flowing through the driving pin GATE when the enable pin EN receives the second signal to control the off speed of the power switch Q1.

Referring to fig. 5, the current conversion unit 201 includes a first PMOS transistor P1, a second PMOS transistor P2, a second NMOS transistor N2, a third NMOS transistor N3, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a fourth NMOS transistor N4. The first PMOS tube P1 and the first NMOS tube N1 are connected in series, the control end of the first PMOS tube P1 is connected with the control end of the second PMOS tube P2, the first PMOS tube P1 and the second PMOS tube P2 are also connected with the first power supply end, the second PMOS tube P2 and the second NMOS tube N2 are connected in series, the control end of the second NMOS tube N2 is connected with the control end of the third NMOS tube N3, the second NMOS tube N2 and the third NMOS tube N3 are also connected with a power supply grounding pin GND, the third NMOS tube N3 and the third PMOS tube P3 are connected in series, the control end of the third PMOS tube P3 is connected with the control end of the fifth PMOS tube P5, the third PMOS tube P3 and the fifth PMOS tube P5 are also connected with the second power supply end, the fifth NMOS tube P5 and the fourth NMOS tube N4 are connected in series, the control end of the fourth NMOS tube N4 and the control end of the fifth NMOS tube N5 are connected with the control end of the fifth NMOS tube N4, the fourth NMOS tube N4 and the fifth NMOS tube N5 are also connected with the fifth power switch Q1, and the fifth switch Q is connected with the fifth power switch Q5.

In the embodiment of the application, the output current of the first PMOS transistor P1 is equal to the output current of the first NMOS transistor N1, the first mirror current of the second PMOS transistor P2 is the mirror image of the output current of the first PMOS transistor P1, the output current of the second NMOS transistor N2 is equal to the first mirror current of the second PMOS transistor P2, the second mirror current of the third NMOS transistor N3 is the mirror image of the output current of the second NMOS transistor N2, the output current of the third PMOS transistor P3 is the mirror image of the second mirror current of the third NMOS transistor N3, the fourth mirror current of the fifth PMOS transistor P5 is the mirror image of the output current of the third PMOS transistor P3, the output current of the fourth NMOS transistor N4 is the mirror image of the fourth mirror image of the fifth PMOS transistor P5, the fifth mirror image of the fifth NMOS transistor N5 is the mirror image of the output current of the fourth NMOS transistor N4, and the off current Ioff is equal to the fifth mirror image current.

In this embodiment, the first resistor Rx is only used to set the fifth mirror current flowing through the fifth NMOS transistor N5, that is, when the enable pin EN receives the second signal, the off current ioff=k1×k2×k4×k5×vref/Rx flowing through the driving pin GATE, so that the off current Ioff flowing through the driving pin GATE can be changed by changing the first resistor Rx or adjusting the resistance of the first resistor Rx, and the turn-off speed of the power switch Q1 can be controlled.

It can be understood that the embodiment shown in fig. 5 is merely an explanation of how the first resistor Rx controls the off current flowing through the driving pin, and the other parts not described in this embodiment can be referred to above including the description in the embodiment shown in fig. 4, which is not repeated here.

In this embodiment, when the control chip matches different power switches, the off current flowing through the driving pin can be set through the first resistor, so as to control the turn-off speed of the power switch, thereby ensuring that the turn-off speed of the power switch can meet the requirement.

It can be appreciated that in the embodiments of the present application, the on-switch and the off-switch may be implemented in various forms, for example, a field effect transistor, a triode, etc., and the embodiments of the present application do not limit the forms of the switches, and they may be selected according to actual requirements.

It can be understood that the circuit structure of the current conversion unit 201 is not limited in the embodiments of the present application, and a specific implementation of the current conversion unit 201 may be designed according to actual requirements, so long as a scheme capable of indirectly or directly controlling the on-speed and/or the off-speed of the power switch based on the first resistor belongs to the protection scope of the present application.

Optionally, on the basis of the foregoing embodiments, the present embodiment further provides an intelligent electronic switch, and referring to descriptions in the embodiments, the intelligent electronic switch includes the control chip 20, the power supply terminal, the power ground terminal, the load output terminal OUT, and the power switch Q1 in the foregoing embodiments.

The power supply end and the power ground end are used for being connected with the battery 10, the control end of the power switch Q1 is connected with the driving pin GATE of the control chip 20, the first end of the power switch Q1 is connected with the power supply end or the power ground end, the second end of the power switch Q1 is connected with the load output end OUT, the load output end OUT is used for being connected with the load R0, and the control chip 20 is used for controlling the on-off of the power switch Q1.

In this embodiment, the power supply end of the power supply may be directly or indirectly connected to the positive electrode of the battery 10, the ground end of the power supply may be directly or indirectly connected to the negative electrode of the battery 10, the on/off of the power switch Q1 is controlled by the control chip 20, the power switch Q1 may be connected to a high-side switch, i.e. connected between the power supply end of the power supply and the load R0, and the power switch Q1 may also be connected to a low-side switch, i.e. connected between the load R0 and the ground end of the power supply, which may be set according to actual requirements, which will not be described herein.

Optionally, the power switch Q1 is any one of an NMOS transistor, a PMOS transistor, and a JFET, and/or the power switch Q1 is implemented as a silicon device, silicon carbide, gallium arsenide, or gallium nitride.

In one possible design of the present application, the power switch Q1 is located on a first chip other than the control chip 20, where the power supply terminal is a power supply pin, the power ground terminal is a power ground pin, and the load output terminal OUT is a load output pin, and accordingly, the load output pin is located on the first chip.

It can be appreciated that in the embodiments of the present application, the first chip, the control chip 20, and the like may further add other pins, omit related pins, or combine related pins as needed. Here, the first chip, the control chip 20, may be packaged as one product.

In addition, in other embodiments of the present application, an automobile is also provided, and the automobile may be an electric automobile, for example, an electric passenger car or an electric business car, or may be a hybrid automobile or a fuel automobile, where the automobile may include the control chip 20 in each of the foregoing embodiments, or the intelligent electronic switch in the foregoing embodiments, and may further include the battery 10, the first resistor Rx, the load R0, and the microprocessor (not shown). The positive electrode and the negative electrode of the battery 10 are correspondingly connected with a power supply pin VCC and a power ground pin GND of the control chip 20, the first resistor Rx is connected with a drive setting pin RT of the control chip 20, the load R0 is connected with the power switch Q1, and the microprocessor is connected with the control chip 20.

Alternatively, the battery 10 may be a single battery or a battery pack, which is not limited in this embodiment. The battery 10 is typically a secondary battery, and the secondary battery provides voltages of 12V, 24V, 48V, etc., but may be other types of batteries such as a lithium battery. The first resistor Rx is connected to the driving setting pin RT of the control chip 20, and is used for setting a driving current flowing through the driving pin GATE of the control chip 20. The load R0 comprises at least one of a resistive load, such as a seat adjustment device, an auxiliary heating device, a window heating device, a Light Emitting Diode (LED), a rear lighting or other resistive load, an inductive load, such as a pump, an actuator, a motor, an Antilock Brake System (ABS), an Electronic Brake System (EBS), a fan or other system comprising an inductive load, such as a lighting element, such as a xenon arc lamp, for one or more wiper systems.

The microcontroller is connected with the intelligent electronic switch and is used for controlling the intelligent electronic switch, and meanwhile, the intelligent electronic switch feeds back the state and related parameter information, such as diagnostic related parameter information, to the microprocessor for processing by the microprocessor.

It can be understood that the control chip, the intelligent electronic switch and the like in this embodiment are not limited to be used in automotive electronics, but can also be used in the fields of industrial automation, aerospace and the like, and will not be described here.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. The control chip is used for controlling the on-off of the power switch and is characterized by comprising a power supply pin, a power ground pin, an enabling pin, a driving setting pin and a driving circuit;

2. The control chip of claim 1, wherein the driving circuit comprises an operational amplifier unit, a first NMOS transistor, and a current conversion unit;

the first input end of the operational amplifier unit is used for accessing reference voltage, the second input end of the operational amplifier unit is connected with the drive setting pin and the second end of the first NMOS tube, the output end of the operational amplifier unit is connected with the control end of the first NMOS tube, the first end of the first NMOS tube is connected with the current conversion unit, and the current conversion unit is also connected with the setting pin;

3. The control chip of claim 2, wherein the drive current comprises an on current that flows through the drive pin when the enable pin receives a first signal to control an on speed of the power switch;

4. The control chip of claim 3, wherein the drive current comprises an off current that flows through the drive pin when the enable pin receives a second signal to control an off speed of the power switch;

5. The control chip of claim 4, wherein the ratio of the off current to the on current ranges from (10-1): 1.

6. The control chip of claim 5, wherein the ratio of the off current to the on current is equal to the ratio of the drive pin voltage variation corresponding to the power switch being fully off to the on threshold voltage, wherein the drive pin voltage variation corresponding to the power switch being fully off is equal to the difference between the voltage of the drive pin and the on threshold voltage when the power switch is fully on.

7. The control chip of claim 2, wherein the drive current comprises an off current that flows through the drive pin when the enable pin receives a second signal to control an off speed of the power switch;

8. An intelligent electronic switch, characterized by comprising the control chip, the power supply end, the power ground end, the load output end and the power switch according to any one of claims 1 to 7;

9. The intelligent electronic switch of claim 8, wherein the power switch is any one of an NMOS transistor, a PMOS transistor, a JFET, and/or the power switch is implemented as a silicon device, silicon carbide, gallium arsenide, or gallium nitride.

10. The intelligent electronic switch of claim 8 or 9, wherein the power switch is located on a first chip other than the control chip;

11. An automobile comprising the control chip according to any one of claims 1 to 7, or the intelligent electronic switch according to any one of claims 8 to 10;

12. The vehicle of claim 11, wherein the vehicle is an electric vehicle, a hybrid vehicle, or a fuel vehicle, and the load comprises at least one of a resistive load, an inductive load, and a capacitive load.