CN116015023A

CN116015023A - Driving circuit, related control chip circuit, power adapter and electronic equipment

Info

Publication number: CN116015023A
Application number: CN202210170572.9A
Authority: CN
Inventors: 张涛
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2021-10-22
Filing date: 2021-10-22
Publication date: 2023-04-25
Also published as: WO2023065789A1; CN113676026A; CN113676026B

Abstract

The application provides drive circuit and relevant control chip circuit, power adapter and electronic equipment, drive circuit includes: the first section driving circuit is connected with the second section driving circuit; the second section driving circuit is used for driving the external power tube to realize a driving function; the driving current of the second section driving circuit is E times of the driving current of the first section, and E is larger than 1. According to the embodiment of the application, as the first section of driving circuit adopts small current driving and the second section of driving circuit adopts a large current driving method, di/dt change can be reduced, driving voltage of the power tube is smoothly increased, and the EMI effect of the chip is improved.

Description

Driving circuit, related control chip circuit, power adapter and electronic equipment

Technical Field

The application relates to the technical field of electronics, in particular to a driving circuit, a related control chip circuit, a power adapter and electronic equipment.

Background

The switching power supply has dv/dt and di/dt change in the switching process, so that the electromagnetic interference noise of the switching power supply generated by parasitic inductance and capacitance existing in a circuit is difficult to eliminate, and the switching power supply mainly has the following noise sources: power MOS, output diode, inductor and transformer. The PD (power delivery) fast charge currently popular in the market requires a wider output voltage range. Therefore, the chip design requires a wide operating range for the chip input operating voltage, and the wide input voltage range presents challenges for the design of the driving circuit.

In the prior art, the driving control is usually performed by a larger current, which results in a larger di/dt, and the electromagnetic interference (electromagnetic interference, EMI) effect is poor, so the problem of how to reduce the EMI in the driving process is needed to be solved.

Disclosure of Invention

The embodiment of the application provides a driving circuit, a related control chip circuit, a power adapter and electronic equipment, which can reduce the EMI effect in the driving process.

In a first aspect, embodiments of the present application provide a driving circuit, including: a first segment driving circuit and a second segment driving circuit, wherein,

the first section driving circuit is connected with the second section driving circuit; the second section driving circuit is used for driving the external power tube to realize a driving function; the driving current of the second section driving circuit is E times of the driving current of the first section, and E is larger than 1.

In a second aspect, embodiments of the present application provide a control chip circuit comprising a drive circuit as described in the first aspect above.

In a third aspect, embodiments of the present application provide a power adapter comprising a driving circuit as described in the first aspect, or a control chip circuit as described in the second aspect.

In a fourth aspect, embodiments of the present application provide an electronic device comprising a driving circuit as described in the first aspect, or a control chip circuit as described in the second aspect, or a power adapter as described in the third aspect.

By implementing the embodiment of the application, the following beneficial effects are achieved:

as can be seen, the driving circuit and the related products described in the embodiments of the present application, the driving circuit includes: the first section driving circuit and the second section driving circuit, wherein the first section driving circuit is connected with the second section driving circuit, the second section driving circuit is used for driving the external power tube to realize the driving function, the driving current of the second section driving circuit is E times of that of the first section driving circuit, E is larger than 1, and as the first section driving circuit adopts small current driving, the second section driving circuit adopts a large current driving method, the di/dt change can be reduced, the driving voltage of the power tube is smoothly increased, and the EMI effect of the chip is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an NMOS transistor according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a PMOS tube according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a driving circuit according to an embodiment of the present application;

fig. 4 is a schematic waveform diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 5 is another schematic structural diagram of a driving circuit according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a first stage driving circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a second stage driving circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic waveform diagram of another driving circuit according to an embodiment of the present application.

Detailed Description

For better understanding of the technical solutions of the present application by those skilled in the art, the technical solutions of the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art without the exercise of inventive faculty, are intended to be within the scope of protection of the present application based on the description of the embodiments herein.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, software, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Embodiments of the present application will be described with reference to the accompanying drawings, in which the crossing points of intersecting conductors have dots to indicate that the conductors are connected, and the non-dots at the crossing points indicate that the conductors are not connected.

In this embodiment, as shown in fig. 1, for an NMOS transistor, a first end of the NMOS transistor is a gate, a second end is a source, a third end is a drain, a fourth end is a substrate, and a fourth end is grounded; as shown in fig. 2, for the PMOS transistor, the first end of the PMOS transistor is a gate, the second end is a source, the third end is a drain, the fourth end is a substrate, and the fourth end is used for accessing power, such as VCC and VDD.

In the related art, as shown in fig. 3, the driving circuit adopts a one-stage control mode, the waveform diagram of the driving signal is shown in fig. 4, and di/dt in the switching process is changed greatly, so that the EMI effect is poor. Meanwhile, the output voltage is about VDD-VGS, wherein VGS is about 1.2V, when the chip is used as PD for fast charging, the output voltage is limited and is as low as about 5.3V when the VDD voltage is as low as 6.5V, and the threshold value of the traditional output high-voltage power tube is between 3 and 4V. The high-voltage MOS power tube outputting the driving voltage of 5.3V to drive the threshold value of 3-4V can cause insufficient driving capability and incomplete power tube opening, and has low switching efficiency.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present application, where the driving circuit includes: a first segment driving circuit and a second segment driving circuit, wherein,

The first section driving circuit is driven by small current, the second section driving circuit is driven by large current, and the two sections of circuits realize the transition of the current from small to large so as to reduce di/dt change, thereby improving the EMI effect.

As can be seen, the driving circuit described in the embodiments of the present application includes: the first section driving circuit and the second section driving circuit, wherein the first section driving circuit is connected with the second section driving circuit, the second section driving circuit is used for driving the external power tube to realize the driving function, the driving current of the second section driving circuit is E times of that of the first section driving circuit, E is larger than 1, and as the first section driving circuit adopts small current driving, the second section driving circuit adopts a large current driving method, the di/dt change can be reduced, the driving voltage of the power tube is smoothly increased, and the EMI effect of the chip is improved.

Further, as shown in fig. 6 and 7, fig. 6 shows a schematic structural diagram of the first driving circuit, and fig. 7 shows a schematic structural diagram of the second driving circuit, specifically as follows:

optionally, as shown in fig. 7, the second stage driving circuit includes a BOOST circuit (BOOST circuit), a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5; the booster circuit includes: the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the second NMOS transistor N2, the bipolar junction transistor (Bipolar Junction Transistor, BJT), the first inverter group, the first capacitor C, the first resistor R1 and the second resistor R2;

the first end of the first PMOS tube P1 is connected with the first end of the first NMOS tube N1; the third end of the first PMOS tube P1 is connected with the negative electrode (-) of the first capacitor C and the third end of the first NMOS tube N1; the third end of the first PMOS tube P1 is connected with a first power supply VCC and the BJT; the BJT is connected with the positive pole (+) of the first capacitor C and the second end of the second PMOS tube P2;

the first end of the second PMOS tube P2 is connected with the first end of the second NMOS tube N2 and the output ends of a first a1 inverters in the first inverter group, the first inverter group comprises a plurality of a inverters, a1 is smaller than a, and a1 and a are both odd numbers; the second end of the second PMOS tube P2 is also connected with the positive electrode (+) of the first capacitor C; the third end of the second PMOS transistor P2 is connected to the first end of the third NMOS transistor N3 and the third end of the second NMOS transistor N2; the output end of the first inverter group is connected with the first end of the fourth NMOS tube N4; the third end of the second PMOS tube P2 is grounded;

the second end of the third NMOS transistor N3 is connected to the third end of the fourth NMOS transistor N4 and the second end of the fifth NMOS transistor N5; the first end of the fifth NMOS transistor N5 is used for accessing the output signal DU2 of the first segment driving circuit; the third end of the third NMOS tube N3 and the third end of the fifth NMOS tube N5 are connected to a second power supply VDD; the second end of the fifth NMOS tube N5 is connected with one end of the first resistor R1 and a drive port GATE; the other end of the first resistor R1 is connected with one end of a second resistor R2 and is used for outputting a comparison voltage VO_ADOPT, and the other end of the second resistor R2 is grounded;

the first end of the first NMOS tube N1 is used for accessing a second input signal VCON2, the second input signal VCON2 is an output signal obtained by a signal output by the output end of the AND gate circuit after passing through the second inverter group y2, and one input end of the AND gate circuit is input by the first input signal VCON1 after passing through the third inverter group y 1; the other input end of the AND gate circuit is used for inputting a driving signal PWM, and the second inverter group y2 comprises b inverters; the first input signal is an output signal of the comparator, the third inverter group y1 comprises c inverters, and b and c are both odd numbers; the second end of the first NMOS tube N1 is grounded.

The first inverter group may include a inverters, a1 is smaller than a, and a1 and a are all odd numbers, for example, in the embodiment of the present application, 3 inverters are used for description, that is, an inverter x1, an inverter x2, and an inverter x3. The inverter can promote driving capability on the one hand, and on the other hand can realize the time delay effect.

Wherein VCC voltage is the chip internal power supply voltage of the drive circuit, and VDD is the chip external power supply voltage of the drive circuit. The drive port GATE is used for connecting a power tube, and the power tube is used for charging the outside.

Optionally, as shown in fig. 6, the first stage driving circuit includes: the comparator, the third inverter group, the first current amplifying circuit, the second current amplifying circuit, the sixth NMOS tube N6 and the seventh NMOS tube N7; the fourth inverter group comprises d inverters, and d is an odd number; the first current amplifying circuit comprises a third PMOS tube P3, a fourth PMOS tube P4, a third resistor R3 and a fourth resistor R4; the second current amplifying circuit comprises an eighth NMOS tube N8 and a ninth NMOS tube N9;

the non-inverting input end (+) of the comparator is connected with a third power supply, and the inverting input end (-) of the comparator inputs the comparison voltage VO_ADOPT; the output end of the comparator is connected with the first end of the sixth NMOS tube N6 and the input end of the third inverter group; the output end of the third inverter group is connected with the first end of the seventh NMOS tube N7;

the second end of the sixth NMOS tube N6 is connected with the third end of the ninth NMOS tube N9; a third end of the sixth NMOS tube N6 is connected with one end of the third resistor R3, and the other end of the third resistor R3 is connected with a third end and a first end of the third PMOS tube P3; the first end of the third PMOS tube P3 is connected with the first end of the fourth PMOS tube P4; the second end of the third PMOS transistor P3 and the second end of the fourth PMOS transistor P4 are both connected to the second power supply VDD; the third end of the fourth PMOS tube P4 is connected with one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected with the third end of the seventh NMOS tube N7 and outputs the output signal of the first section driving circuit; the second end of the seventh NMOS tube N7 is grounded;

the first end of the ninth NMOS tube N9 is connected with the first end of the eighth NMOS tube N8; the first end and the third end of the eighth NMOS transistor N8 are used for connecting a current bias module to introduce a bias current I1; the second end of the ninth NMOS transistor N9 and the third end of the eighth NMOS transistor N8 are all grounded.

The fourth inverter group may include d inverters, where d is an odd number, and in the embodiment of the present application, 3 inverters are used for explanation, that is, the inverter x4, the inverter x5, and the inverter x6. The third power supply is used for providing a reference voltage VREF inside the power chip. The bias current is a bias circuit inside the chip. The first current amplifying circuit and the second current amplifying circuit are used for realizing a current amplifying function.

Optionally, the comparator is configured to compare the comparison voltage vo_adopt with a reference voltage VREF of the third power supply V1 to obtain a first segment of driving control signal, where the comparison voltage vo_adopt is a voltage obtained by dividing the voltage by the first resistor R1 and the second resistor R2;

when the first section driving control signal is at a high level, the sixth NMOS tube N6 is turned on, the input current at the first end of the ninth NMOS tube N9 is M times of the bias current, and meanwhile, the seventh NMOS tube N7 is turned off, and M is greater than 1;

after the fourth PMOS P4 is turned on, driving the first end of the fifth NMOS N5 to quickly raise the voltage of the first end of the fifth NMOS N5, where the set value is a bias current m×n, and N is greater than 1;

and driving the first end of the fifth NMOS tube N5 to quickly rise the voltage of the fifth NMOS tube N5.

Where M is greater than 1, e.g., m=5. N is greater than 1, for example, n=40. Specifically, P4 is turned on, so that the output signal DU of the first stage driving circuit rises to reach the set value, so as to drive the first end of the fifth NMOS transistor N5, so that the voltage of the first end of the fifth NMOS transistor N5 rises rapidly.

Optionally, when the voltage GATE of the output signal of the second stage driving circuit rises to a first preset threshold, the first input signal becomes low, and the sixth NMOS transistor N6 is turned off to close the charging path; simultaneously, the seventh NMOS tube N7 is pulled down to be opened, the voltage of the output signal of the first section driving circuit is pulled down, and the fifth NMOS tube N5 is turned off and driven, so that the first section driving process is completed.

The first preset threshold may be preset or default, for example, the first preset threshold is vgs_n5+ (r1+r2)/r2×vref, and VGS is the voltage between the gate and the source.

Optionally, the first PMOS transistor P1 and the first NMOS transistor N1 form a first inverter; the second PMOS transistor P2 and the second NMOS transistor N2 form a second inverter.

Optionally, in the second stage driving process, the first PMOS transistor P1 of the upper tube of the first inverter is turned on, and the first NMOS transistor N1 of the lower tube is turned off; the positive electrode initial state voltage of the first capacitor is a first voltage value, and the first voltage value is equal to the difference value between the voltage value of the first power supply and the voltage of the VBE electrode of the BJT;

when the first PMOS transistor P1 is turned on, the negative electrode of the first capacitor is charged until the absolute value of the difference between the voltage of the negative electrode of the first capacitor and the voltage value of the first power supply is smaller than a second preset threshold, and the positive electrode of the first capacitor is lifted to a second voltage value, wherein the second voltage value is equal to 2 times the difference between the voltage value of the first power supply and the voltage of the VBE electrode of the BJT, namely 2VV-VBE; meanwhile, the second PMOS tube P2 of the upper tube of the second inverter is conducted, and the second NMOS tube N2 of the lower tube is closed; and starting and driving the third NMOS tube N3.

Wherein the second preset threshold may be preset or default to the system, the second preset threshold may be close to 0, for example, the second preset threshold=0, or, for example, the second preset threshold=0.01.

Wherein, the above-mentioned P1 and N1 constitute a first inverter INV1, and P2 and N2 constitute a second inverter INV2.INV1, C, INV2, BJT have become a simple BOOST circuit, namely BOOST circuit, adopt BOOST control technique, ensure that the drive voltage of power tube is in a reasonable drive voltage range, and then, can be for improving when the chip input voltage is low, output drive voltage and switching efficiency, the drive ability when reinforcing input voltage is low also can satisfy PD wide range input voltage requirement.

In specific implementation, the driving circuit described in the embodiment of the present application has a specific working principle:

(1) When the driving signal (Pulse Width Modulation, PWM) is high and the VCON1 signal is low, the upper tube P1 of the first inverter INV1 is turned on, the lower tube N1 is turned off, and the positive initial voltage of the capacitor is VCC-VBE, where VBE is the voltage of the VBE pole of the BJT, and the voltage is typically about 0.6-0.7V. When the P1 pipe is conducted, the negative electrode of the capacitor is charged to VCC, and the positive electrode of the capacitor is lifted to 2VCC-VBE. Meanwhile, the upper pipe P2 of the second inverter INV2 is turned on, and the lower pipe N2 is turned off, and the output voltage DU1 is 2VCC-VBE, so as to turn on the driving N3 pipe.

(2) When the driving signal PWM is low and the VCON1 signal is high, the upper pipe P1 of the first inverter INV1 is turned off, the lower pipe N1 is turned off, the negative electrode of the capacitor is pulled to 0, and the positive electrode of the capacitor becomes VCC-VBE. Meanwhile, the upper pipe P2 of the second inverter INV2 is closed and the lower pipe N2 is turned on. The drive N-pipe N3 is turned off. Simultaneously, pull-down N3 is turned on to pull down the GATE voltage, turning off the drive.

In addition, the specific sectional driving working principle is as follows: the driving tubes N3 and N5 are respectively started by sampling the magnitude of the output driving GATE, so that the output driving current is changed from small to large, and the driving voltage is slowly increased, thereby achieving the effect of improving the EMI.

Specifically, as shown in fig. 7: the output driving voltage GATE is divided by the resistors R1 and R2, and the output voltage vo_adopt is outputted. The first stage driving control signal VCON1 is output by comparing the comparator COMP with the reference voltage VREF. When the control signal VCON1 output by the comparator COMP is high, the tube N6 is turned on, and the driving current of the branch N9 is m×i1, that is, the ratio between the driving current of the branch N8 and the driving current of the branch N9 is: 1:M. At the same time, the N7 tube is closed. The driving current of the P4 tube is m×n×i1, and the ratio between the driving current of the P3 and the driving current of the P4 tube is 1: n; further, the gate of N5 is driven, and the N5 gate voltage is rapidly increased. When the driving voltage DU2 of N5 rises to vgs_n5+ (r1+r2)/r2×vref, the comparator COMP output VCON1 immediately goes low, and N6 is turned off, i.e. the charging path is turned off, and vgs_n5 is the voltage value between the gate and the source of N5. Simultaneously, the pull-down pipe N7 is opened, and the voltage of DU2 is pulled down to turn off the driving pipe N5, thereby completing the first section driving.

When the first segment driving is completed, the comparator COMP1 output VCON1 goes low. At this time, the vo_adopt output voltage is (r1+r2)/r2×vref. After the inverse of the PWM signal and the VCON1 signal goes through and logic, the output voltage VCON2 controls INV1 and the inverter X1. And the upper tube P1 of the INV1 is conducted, and the lower tube N1 is closed, so that the initial voltage of the positive electrode of the capacitor is VCC-VBE. When the P1 pipe is conducted, the negative electrode of the capacitor is charged to VCC, and the positive electrode of the capacitor is lifted to 2VCC-VBE. Meanwhile, the upper pipe P2 of the INV2 is conducted, and the lower pipe N2 is closed. And outputting the voltage 2VCC-VBE. The driving N pipe N3 is started, the driving current is increased, and the output GATE voltage is rapidly increased from (R1+R2)/R2 to 2VCC-VBE-VGS_N3. Thus, the driving current is changed from small to large, the driving voltage is gradually changed from low to high, so that di/dt spike is reduced, and the EMI effect is improved.

In specific implementation, the width-to-length ratio of N3 to N5 is E: 1. Thus, the drive current of N3 is E times that of the N5 tube. I.e. the second segment drive current is E times the first segment drive current. In the embodiment of the application, the second-stage driving circuit uses a BOOST circuit to raise the voltage of the N3 gate to 2VCC-VBE at the highest. When the external power supply voltage is lower than the 2VCC-VBE voltage due to the low output load, the output GATE voltage is changed into VDD at maximum, and the VGS voltage is improved compared with the prior art without a booster circuit. The output driving voltage and the switching efficiency when the input voltage is low are improved, and the driving capability when the VDD is low is enhanced.

According to the embodiment of the application, the two-stage driving control and BOOST driving grid voltage technology is adopted, so that the EMI is improved, and the minimum chip driving voltage is also improved. The driving capability of the low input voltage is improved, and meanwhile, the switching efficiency of the power tube is improved.

In the embodiment of the application, in order to improve the EMI effect, a segment driving method may be used in the driving circuit of the power control chip to improve the EMI effect. The method mainly adopts a sectional driving method: the first section is driven by small current; the second section of large current driving method can reduce di/dt change, smoothly increase the driving voltage of the power tube and improve the EMI effect of the chip. In addition, by adopting a BOOST control technology, the driving voltage of the power tube can be ensured to be within a reasonable driving voltage range.

In the embodiment of the application, segment driving and BOOST technology are adopted. The EMI effect of the chip is improved, and the output driving voltage is not lower than the input voltage when the input voltage of the chip is lower. And the driving capability and efficiency of the power tube are improved.

The first power supply, the second power supply, and the third power supply may be an AC/DC power supply, a DC/DC power supply, a stabilized voltage power supply, a communication power supply, a module power supply, a variable frequency power supply, an inverter power supply, an AC stabilized voltage power supply, a DC stabilized voltage power supply, or the like. The first power source and the second power source may be the same power source or different power sources.

Further, the power tube is output to the electric equipment, so that the electric equipment can be charged, the electric equipment can be understood as equipment needing to be charged by a user, and the user equipment can include but is not limited to: smart phones, tablet computers, smart robots, smart elevators, car devices, wearable devices, smart home devices, computing devices or other processing devices connected to wireless modems, as well as various forms of User Equipment (UE), mobile Stations (MS), terminal devices (terminals), etc.

In a specific implementation, as shown in fig. 8, where waveforms of PWM, VCON1, VCON2 and GATE signals are shown, it can be seen that the driving current can be changed from small to large, and the driving voltage has a gradual change from low to high. The di/dt spike is reduced, and the EMI effect is improved.

Further, the driving circuit may be applied to a control chip circuit, and the control chip circuit may include at least one of the following: the AC-DC chip control circuit, the DC-DC chip control circuit, the linear power supply and the like are not limited herein, and the AC-DC chip control circuit can be a flyback AC-DC chip control circuit or a non-flyback AC-DC chip control circuit, so that the problems of insufficient driving voltage and EMI in the power supply can be better improved.

Based on the embodiment of the application, the driving circuit provided by the application can meet the requirement of the PD on fast filling and widening of the input voltage and improve the EMI of the chip, so that the purposes of improving the EMI effect of the power chip and meeting the requirement of the PD on wide-range input voltage are achieved, and the driving capability of the chip in low input voltage, the output driving voltage, the switching efficiency and the enhancement in low input voltage can be improved.

Still further, the driving circuit and the control chip circuit may be applied to a power adapter.

Of course, the embodiment of the present application also provides an electronic device, which may include the driving circuit or the chip control circuit or the power adapter as described in fig. 5, and for example, the electronic device may be a charger or a charger.

The foregoing is a description of embodiments of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles of the embodiments of the present application, and these improvements and modifications are also considered as the protection scope of the present application.

Claims

1. A driving circuit, characterized in that the driving circuit comprises: a first segment driving circuit and a second segment driving circuit, wherein,

the first section driving circuit is connected with the second section driving circuit; the second section driving circuit is used for driving the external power tube to realize a driving function; the driving current of the second section driving circuit is E times of the driving current of the first section.

2. The driving circuit according to claim 1, wherein the second stage driving circuit comprises a boost circuit, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5; the booster circuit includes: the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2, the bipolar junction transistor BJT, the first inverter group, the first capacitor C, the first resistor R1 and the second resistor R2;

the first end of the P1 is connected with the first end of the N1; the third end of the P1 is connected with the negative electrode of the C and the third end of the N1; the third end of the P1 is connected with a first power supply VCC and the BJT; the BJT is connected with the positive electrode of the C and the second end of the P2;

the first end of the P2 is connected with the first end of the N2 and the output ends of a first a1 inverters in the first inverter group, the first inverter group comprises a number a of inverters, a1 is smaller than a, and a1 and a are both odd numbers; the second end of the P2 is also connected with the positive electrode of the C; the third end of the P2 is connected with the first end of the N3 and the third end of the N2; the output end of the first inverter group is connected with the first end of the N4; the third end of the P2 is grounded;

the second end of the N3 is connected with the third end of the N4 and the second end of the N5; the first end of the N5 is used for accessing the output signal of the first section of driving circuit; the third end of the N3 and the third end of the N5 are connected to a second power supply VDD; the second end of the N5 is connected with one end of the R1 and a driving port; the other end of the R1 is connected with one end of the R2 and is used for outputting a comparison voltage VO_ADOPT, and the other end of the R2 is grounded;

the first end of the N1 is used for accessing a second input signal VCON2, the VCON2 is an output signal obtained by the output end of the AND gate circuit after the signal output by the output end passes through the second inverter group, and one input end of the AND gate circuit is input by the first input signal VCON1 through the third inverter group; the other input end of the AND gate circuit is used for inputting a driving signal, and the second inverter group comprises b inverters; the first input signal is an output signal of the comparator, the third inverter group comprises c inverters, and b and c are both odd numbers; the second end of the N1 is grounded.

3. The drive circuit of claim 2, wherein the first stage drive circuit comprises: the comparator, the fourth inverter group, the first current amplifying circuit, the second current amplifying circuit, the sixth NMOS tube N6 and the seventh NMOS tube N7; the fourth inverter group comprises d inverters, and d is an odd number; the first current amplifying circuit comprises a third PMOS tube P3, a fourth PMOS tube P4, a third resistor R3 and a fourth resistor R4; the second current amplifying circuit comprises an eighth NMOS tube N8 and a ninth NMOS tube N9;

the non-inverting input end of the comparator is connected with a third power supply, and the inverting input end of the comparator inputs the VO_ADOPT; the output end of the comparator is connected with the first end of the N6 and the input end of the third inverter group; the output end of the third inverter group is connected with the first end of the N7;

the second end of the N6 is connected with the third end of the N9; the third end of the N6 is connected with one end of the R3, and the other end of the R3 is connected with the third end and the first end of the P3; the first end of the P3 is connected with the first end of the P4; the second end of the P3 and the second end of the P4 are both connected to the VDD; the third end of the P4 is connected with one end of the R4, and the other end of the R4 is connected with the third end of the N7 and outputs the output signal of the first section driving circuit; the second end of the N7 is grounded;

the first end of the N9 is connected with the first end of the N8; the first end and the third end of the N8 are used for being connected with a current bias module so as to introduce bias current; the second end of the N9 and the third end of the N8 are grounded.

4. A driving circuit according to claim 3 or 2, wherein,

the comparator is used for comparing the VO_ADOPT with the reference voltage VREF of the third power supply to obtain a first section of driving control signal, wherein the VO_ADOPT is a voltage obtained by dividing the R1 and the R2;

when the first section driving control signal is at a high level, the N6 is started, the input current of the first end of the N9 is M times of the bias current, and meanwhile, the N7 is closed, and M is larger than 1;

after the output signal of the first section of driving circuit rises to a set value, driving the first end of N5 to enable the voltage of the first end of N5 to rise rapidly, wherein the set value is bias current which is M times N, and N is larger than 1;

and driving the first end of the N5 to quickly rise the voltage of the N5.

5. The driving circuit according to claim 4, wherein,

when the voltage GATE of the output signal of the second stage driving circuit rises to a first preset threshold value, the first input signal becomes low, and the N6 is closed to close a charging path; and simultaneously, pulling down the N7 to be started, pulling down the voltage of the output signal of the first section driving circuit, and turning off the driving N5 to finish the first section driving process.

6. The drive circuit according to claim 5 or 4 or 3 or 2, wherein the P1 and the N1 pipe constitute a first inverter; the P2 and the N2 constitute a second inverter.

7. The driving circuit according to claim 6, 5 or 4, wherein during the second stage driving, the first inverter is used for conducting the upper pipe P1, and the lower pipe N1 is closed; the positive initial state voltage of the C is a first voltage value which is equal to the difference value between the voltage value of the first power supply and the voltage of the VBE pole of the BJT;

when the P1 is conducted, the negative electrode of the first capacitor is charged until the absolute value of the difference between the voltage of the negative electrode of the first capacitor and the voltage value of the first power supply is smaller than a second preset threshold value, and the positive electrode of the first capacitor is lifted to a second voltage value which is equal to 2 times the difference between the voltage value of the first power supply and the voltage of the VBE electrode of the BJT; meanwhile, the P2 of the upper tube of the second inverter is conducted, and the N2 of the lower tube of the second inverter is closed; and starting to drive the N3.

8. A control chip circuit, characterized in that the control chip circuit comprises a drive circuit as described in any of claims 1-7.

9. A power adapter comprising a drive circuit as described in any one of claims 1-7 or a control chip circuit as described in claim 8.

10. An electronic device comprising a drive circuit as described in any of claims 1-7, or a control chip circuit as described in claim 8, or a power adapter as described in claim 9.