CN115314033B

CN115314033B - Quick charging driving circuit and related product

Info

Publication number: CN115314033B
Application number: CN202211229534.2A
Authority: CN
Inventors: 张涛; 江力; 杜德喜
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2022-10-09
Filing date: 2022-10-09
Publication date: 2023-03-07
Anticipated expiration: 2042-10-09
Also published as: CN115314033A; WO2024077839A1

Abstract

The embodiment of the application provides a quick charge driving circuit and a related product, and the quick charge driving circuit comprises a booster circuit, a driving circuit and a sampling circuit; the driving circuit is connected with the first power supply and the pulse circuit, and is used for receiving the input voltage output by the first power supply and the driving signal output by the pulse circuit, outputting corresponding driving voltage according to the driving signal and driving the external power tube to realize the driving function; the sampling circuit is connected with the driving circuit and is used for sampling the driving voltage and outputting a boosting control signal to the boosting circuit when the driving voltage is lower than a first preset value; and the boosting circuit is connected with the driving circuit and used for outputting a boosting voltage to the driving circuit to increase the driving voltage when receiving the boosting control signal. Therefore, when the driving voltage is lower, the driving voltage is lifted, the driving capability of the quick charge driving circuit is improved, and the switching efficiency is improved.

Description

Quick charging driving circuit and related product

Technical Field

The application belongs to the technical field of electronics, and in particular relates to a quick charge driving circuit and a related product.

Background

At present, in the traditional drive circuit control method, because the voltage raising function is not adopted, the maximum drive voltage is VDD-VGS. When the input supply voltage is too low, the switching efficiency is affected. For example: when the input power supply voltage VDD is as low as 6V, the driving voltage is limited to be reduced to about 5V due to the fact that the VGS voltage is about 1V; and the threshold value of the traditional output high-voltage power tube is between 3 and 4V. When a 5V driving voltage drives a high-voltage MOS tube with a threshold value of 3-4V, the driving capability is insufficient, the power tube is not completely opened, and the switching efficiency is low.

Disclosure of Invention

The embodiment of the application provides a quick charge driving circuit and a related product, so that when the driving voltage is lower, the driving voltage is raised, and the switching efficiency is improved.

In a first aspect, an embodiment of the present application provides a fast charging driving circuit, which is characterized by including a boost circuit, a driving circuit, and a sampling circuit;

the driving circuit is connected with the first power supply and the pulse circuit, is used for outputting an input voltage output by the first power supply and a driving signal output by the pulse circuit, outputting a corresponding driving voltage according to the driving signal and driving the external power tube to realize a driving function;

the sampling circuit is connected with the driving circuit and is used for sampling the driving voltage and outputting a boosting control signal to the boosting circuit when the driving voltage is lower than a first preset value;

and the boosting circuit is connected with the driving circuit and used for outputting a boosting voltage to the driving circuit to increase the driving voltage when receiving the boosting control signal.

In a second aspect, an embodiment of the present application provides a control chip circuit, where the control chip circuit includes the fast charge driving circuit according to the first aspect.

In a third aspect, an embodiment of the present application provides a power adapter, where the power adapter includes the fast charge driving circuit according to the first aspect, or the control chip circuit according to the second aspect.

In a fourth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes the fast charge driving circuit according to the first aspect, or the control chip circuit according to the second aspect, or the power adapter according to the third aspect.

In the embodiment of the present application, it can be seen that, firstly, the input voltage output by the first power supply and the driving signal output by the pulse circuit are received by the driving circuit, outputting corresponding driving voltage according to the driving signal, and driving the external power tube to realize the driving function; the driving voltage is sampled through the sampling circuit, and when the driving voltage is lower than a first preset value, a boosting control signal is output to the boosting circuit; and finally, outputting boosted voltage to the driving circuit by the boosting circuit when the boosting control signal is received so as to increase the driving voltage. Therefore, when the driving voltage is lower, the driving voltage is lifted, the driving capability of the quick charge driving circuit is improved, and the switching efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1a is a circuit schematic of a conventional driver circuit;

FIG. 1b is a diagram of comparing the driving signal PWM with the GATE voltage in a conventional driving circuit;

fig. 2a is a schematic structural diagram of an NMOS transistor according to an embodiment of the present disclosure;

fig. 2b is a schematic structural diagram of a PMOS transistor according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a fast charge driving circuit according to an embodiment of the present disclosure;

FIG. 4 is a circuit diagram of a sampling circuit provided in an embodiment of the present application;

FIG. 5 is a circuit schematic of a voltage boost circuit provided by an embodiment of the present application;

FIG. 6 is a circuit diagram of a driving circuit provided in an embodiment of the present application;

FIG. 7 is a waveform diagram of various signals provided by embodiments of the present application;

fig. 8 is a waveform diagram of a driving voltage varying with VDD according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, system, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Due to the switching action of the switching power supply, du/dt and di/dt changes exist in the switching process, so that parasitic inductance existing in a circuit is difficult to eliminate, and electromagnetic interference noise of the switching power supply generated by (removing) a capacitor is difficult to eliminate, and the following noise sources are mainly adopted: power MOS, output diode, inductance and transformer.

The traditional driving method usually adopts a section of driving control, which is a large current driving at the beginning, resulting in large di/dt and poor EMI effect.

Moreover, the conventional driving circuit does not employ the boosting technique when the power supply voltage is low, so that the driving voltage of the driving circuit becomes lower when the input voltage VDD is lower. The lower driving voltage affects the driving capability and efficiency of the power tube. An excessive driving voltage may damage the output power transistor.

As shown in fig. 1a, fig. 1a is a circuit schematic diagram of a conventional driving circuit. The driving module drives step by step through the reverser chain. In order to rapidly turn on or off the drain current, a large current is required to drive the gate voltage to rise or fall.

FIG. 1b is a diagram showing a comparison between the driving signal PWM and the GATE voltage (i.e., the driving voltage VGATE) in the conventional driving circuit, as shown in FIG. 1 b. When the PWM signal is 0, the grid voltage position of the NMOS tube N1 is high. Meanwhile, N1 is started to output large current, parasitic capacitance of a grid electrode of the external power tube is charged, and GATE voltage is rapidly increased. Similarly, when the PWM signal is 1, the NMOS transistor N3 is turned on, and the GATE voltage is pulled down instantaneously.

The traditional control method adopts a direct drive mode, namely, high-current drive at the beginning, so that di/dt in the switching process is large in change, and the EMI effect is poor. Meanwhile, the maximum driving voltage is VDD-VGS because the voltage raising function is not adopted. When the input supply voltage is too low, switching efficiency is affected. For example: when the input power supply voltage VDD is as low as 6V (VGS is about 1V), the output voltage is limited to be as low as about 5V, and the threshold value of the traditional output high-voltage power tube is between 3V and 4V. The high-voltage MOS tube outputting the driving voltage of 5V to drive the threshold value of 3-4V can cause insufficient driving capability and incomplete opening of the power tube, and the switching efficiency is low.

In order to solve the above problem, an embodiment of the present application provides a fast charging driving circuit, where the fast charging driving circuit includes a voltage boosting circuit, a driving circuit, and a sampling circuit. The quick charge driving circuit can be applied to the scene that the switching efficiency of an external switching tube is low due to too low driving voltage. The driving circuit can receive the input voltage output by the first power supply and the driving signal output by the pulse circuit, and output corresponding driving voltage according to the driving signal to drive the external power tube to realize the driving function; the driving voltage is sampled through the sampling circuit, and when the driving voltage is lower than a first preset value, a boosting control signal is output to the boosting circuit; and finally, outputting boosted voltage to the driving circuit by the boosting circuit when the boosting control signal is received so as to increase the driving voltage. Therefore, when the driving voltage is lower, the driving voltage is lifted, the driving capability of the quick charge driving circuit is improved, and the switching efficiency is improved. The present solution may be applicable to a variety of scenarios, including but not limited to the application scenarios mentioned above.

The embodiments of the present application are described below with reference to the accompanying drawings, in which a dot at the intersection of intersecting wires indicates that the wires are connected, and no dot at the intersection indicates that the wires are not connected.

In the embodiment of the present application, as shown in fig. 2a, fig. 2a is a schematic structural diagram of an NMOS transistor provided in the embodiment of the present application. For an NMOS tube, a first end of the NMOS tube is a grid electrode, a second end of the NMOS tube is a source electrode, a third end of the NMOS tube is a drain electrode, a fourth end of the NMOS tube is a substrate, and the fourth end of the NMOS tube is grounded. As shown in fig. 2b, fig. 2b is a schematic structural diagram of a PMOS transistor according to an embodiment of the present disclosure. Aiming at the PMOS tube, the first end of the PMOS tube is a grid electrode, the second end of the PMOS tube is a source electrode, the third end of the PMOS tube is a drain electrode, the fourth end of the PMOS tube is a substrate, and the fourth end of the PMOS tube is used for being connected with a power supply, such as VCC and VDD.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a fast charge driving circuit 30 according to an embodiment of the present disclosure, where the fast charge driving circuit 30 includes: a booster circuit 303, a drive circuit 301, and a sampling circuit 302; the driving circuit 301 is connected to the first power supply and the pulse circuit, and configured to receive an input voltage output by the first power supply and a driving signal DR _ N output by the pulse circuit, output a corresponding driving voltage according to the driving signal DR _ N, and drive the external power tube 31 to implement a driving function; the sampling circuit 302 is connected to the driving circuit 301, and is configured to sample the driving voltage, and output a boost control signal DR _2 to the boost circuit 303 when the driving voltage is lower than a first preset value; the boosting circuit 303 is connected to the driving circuit 301, and configured to output a boosted voltage to the driving circuit 301 to increase the driving voltage when receiving the boosting control signal DR _2.

It can be seen that, in this embodiment, the driving circuit 301 receives the input voltage output by the first power supply and the driving signal DR _ N output by the pulse circuit, and outputs a corresponding driving voltage according to the driving signal DR _ N to drive the external power tube 31 to implement the driving function; the driving voltage is sampled by the sampling circuit 302, and when the driving voltage is lower than a first preset value, a boosting control signal DR _2 is output to the boosting circuit 303; finally, when receiving the boost control signal DR _2, the boost circuit 303 outputs a boost voltage to the driving circuit 301 to increase the driving voltage. Therefore, when the driving voltage is lower, the driving voltage is raised, the driving capability of the quick charge driving circuit 30 is improved, and the switching efficiency is improved.

In one possible embodiment, please refer to fig. 4, in which fig. 4 is a circuit diagram of a sampling circuit 302 according to an embodiment of the present disclosure. The sampling circuit 302 comprises a fifth PMOS transistor PM5, a sixth PMOS transistor HPM6, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, a fourth current source I4, a fifth current source I5, and a second inverter INV2;

a source electrode of the fifth PMOS transistor PM5 is connected to a second power VCC, and a gate electrode of the fifth PMOS transistor PM5 is connected to a gate electrode of the sixth PMOS transistor HPM6, a drain electrode of the fifth PMOS transistor PM5, a drain electrode of the eighth NMOS transistor NM8, and a gate electrode of the eighth NMOS transistor NM 8; the source electrode of the eighth NMOS tube NM8 is connected with the drain electrode and the grid electrode of the ninth NMOS tube NM 9; the source of the sixth PMOS transistor HPM6 is connected to the driving output terminal, and the drain of the sixth PMOS transistor HPM6 is connected to the gate of the tenth NMOS transistor NM10 and the input terminal of the fifth current source I5; the drain of the tenth NMOS transistor NM10 is connected to the output terminal of the fourth current source I4 and the input terminal of the second inverter INV2; the input end of the fourth current source I4 is connected with the second power supply VCC; the source electrode of the ninth NMOS transistor NM9, the source electrode of the tenth NMOS transistor NM10, and the output terminal of the fifth current source I5 are all grounded; the output end of the second inverter INV2 is connected to the gate of the third NMOS transistor and the voltage boost circuit to output a voltage boost control signal DR _2.

In a possible embodiment, said sixth PMOS transistor HPM6 is adapted to sample said driving voltage;

when the driving voltage VGATE is less than the sum of the gate-source voltage VGS _ HPM6 of the sixth PMOS transistor, the gate-source voltage VGS _ NM8 of the eighth NMOS transistor NM8 and the gate-source voltage VGS _ NM9 of the ninth NMOS transistor NM9, the sixth PMOS transistor HPM6 is turned off, the gate voltage of the tenth NMOS transistor NM10 is pulled down to a low level by the fifth current source I5, the tenth NMOS transistor NM10 is turned off, the drain voltage of the tenth NMOS transistor NM10 is increased to a high level by the fourth current source I4, and the second inverter INV2 inverts the drain voltage of the tenth NMOS transistor NM10 to obtain the low-level boost control signal DR _2.

When the driving voltage is greater than the sum of the gate-source voltage of the sixth PMOS transistor, the gate-source voltage of the eighth NMOS transistor NM8, and the gate-source voltage of the ninth NMOS transistor NM9, the sixth PMOS transistor HPM6 is turned on, the gate voltage of the tenth NMOS transistor NM10 is pulled up to a high level by the sixth PMOS transistor HPM6, the tenth NMOS transistor NM10 is turned on and pulls down the drain voltage of the tenth NMOS transistor NM10 to a low level, and the second inverter INV2 inverts the drain voltage of the tenth NMOS transistor NM10 to obtain the high-level boost control signal DR _2.

In a specific implementation, the sixth PMOS transistor HPM6 samples the driving voltage, and when the driving voltage VGATE < VGS _ NM9+ VGS _ NM8+ VGS _ HPM6, the second inverter INV2 outputs a low-level boost control signal DR _2; when VGATE > VGS _ NM9+ VGS _ NM8+ VGS _ HPM6, the second inverter INV2 outputs the boosting control signal DR _2 of a high level. Through the level height of boost control signal DR _2 controls boost circuit's operating condition, and then be in drive voltage is crossed low-time lifting drive voltage avoids drive circuit is the not enough problem of driving ability when voltage is crossed low.

It can be seen that, in this embodiment, the technique of raising the driving voltage is adopted when the high input power supply voltage is high and the clamp driving voltage and the input power supply voltage are low; not only improves EMI, but also improves the lowest driving voltage of the chip; the driving capability when the input power supply voltage is low is increased, and meanwhile, the switching efficiency of the power tube is improved.

In one possible embodiment, please refer to fig. 5, in which fig. 5 is a circuit diagram of the boost circuit 303 according to an embodiment of the present disclosure. The boost circuit 303 comprises a third inverter INV3, a first AND gate AND1, a fourth inverter INV4, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a second capacitor C2 AND a seventh diode DZ7;

the input end of the third inverter INV3 is connected to the pulse circuit to access the driving signal, AND the output end of the third inverter INV3 is connected to the first input end of the first AND gate AND 1; a second input end of the first AND gate AND1 is connected with an output end of the second inverter, AND an output end of the first AND gate AND1 is connected with an input end of the fourth inverter INV 4; an output end of the fourth inverter INV4 is connected to the gate of the seventh PMOS transistor PM7, the gate of the eleventh NMOS transistor NM11, the gate of the eighth PMOS transistor PM8 and the gate of the twelfth NMOS transistor NM 12; the source electrode of the seventh PMOS transistor PM7 and the anode of the seventh diode DZ7 are both connected to the second power supply VCC; the drain electrode of the seventh PMOS transistor PM7 is connected to the cathode of the second capacitor C2 and the drain electrode of the eleventh NMOS transistor NM 11; the cathode of the seventh diode DZ7 is connected to the anode of the second capacitor C2 and the source of the eighth PMOS transistor PM 8; the drain electrode of the eighth PMOS transistor PM8 is connected to the drain electrode of the twelfth NMOS transistor NM12, the gate electrode of the seventh NMOS transistor, and the cathode electrode of the sixth diode; the source electrode and the substrate of the eleventh NMOS transistor NM11 are grounded, and the source electrode and the substrate of the twelfth NMOS transistor NM12 are grounded.

In a possible embodiment, the third inverter INV3 is configured to invert the driving signal DR _ N to obtain an inverted driving signal DR _ N; the first AND gate AND1 is configured to perform AND operation on the inverted driving signal DR _ N AND the boost control signal DR _2, AND output an initial driving signal; the fourth inverter INV4 is configured to invert the initial driving signal to obtain a target driving signal;

if the driving signal DR _ N is low and the boosting control signal DR _2 is high, the target drive signal is at a low level; when the target driving signal is at a low level, the seventh PMOS transistor PM7 is turned on, the eleventh NMOS transistor NM11 is turned off, the voltage of the positive electrode of the second capacitor C2 is increased, the eighth PMOS transistor PM8 is turned on, and the boosted voltage is output to the driving circuit to increase the driving voltage;

if the driving signal DR _ N is at a high level, the target driving signal is at a high level; when the target driving signal is at a high level, the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are both turned off, the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 are turned on, the negative electrode of the second capacitor C2 is grounded through the eleventh NMOS transistor NM11, and the boost voltage is changed to a low level to stop boosting the driving voltage before the voltage of the positive electrode of the second capacitor C2 is restored to an increased level.

In a specific implementation, in an initial state, the voltage of the positive electrode of the second capacitor C2 is the second power voltage minus the voltage of the seventh diode DZ7, i.e., VCC-VDZ6. The seventh PMOS transistor PM7 and the eleventh NMOS transistor NM11 form an inverter, and when the output of the fourth inverter INV4 is at a low level, the seventh PMOS transistor PM7 is turned on, so that the voltage of the negative electrode of the second capacitor C2 is charged to VCC, and the voltage of the positive electrode of the second capacitor C2 is raised to 2VCC-VDZ6; at this time, the eighth PMOS transistor PM8 is turned on, the twelfth NMOS transistor NM12 is turned off, and the boosted voltage V8 is output to the driving circuit, so that the driving voltage is boosted. Wherein V8=2VCC-VDZ6, VCC being an internal supply voltage.

When the output of the fourth inverter INV4 is at a high level, the seventh PMOS transistor PM7 is turned off, the eleventh NMOS transistor NM11 is turned on, and the negative electrode voltage of the second capacitor C2 is pulled down to zero, so that the positive electrode voltage of the second capacitor C2 is restored to VCC-VDZ6; at this time, the eighth PMOS transistor PM8 is turned off, and the twelfth NMOS transistor NM12 is turned on, so that the step-up voltage is pulled down instantaneously, and the pull-up of the driving voltage is cancelled.

It is to be understood that the fourth inverter INV4 outputs a low level only when the driving signal DR _ N is a low level and the boost control voltage is a high level, and the fourth inverters INV4 all output a high level in other cases.

It can be seen that in this embodiment, through the mechanisms of the first inverter, the first AND gate AND1, AND the fourth inverter INV4, only when the boost control voltage generated by the sampling circuit is at a high level, the output of the inverter controlled boost voltage formed by the seventh PMOS transistor PM7 AND the eleventh NMOS transistor NM11 can be generated, AND further, when the driving voltage is too low, the driving voltage is boosted.

In one possible embodiment, please refer to fig. 6, which is a circuit diagram of a driving circuit 301 according to an embodiment of the present application. The driving circuit 301 includes a first NMOS transistor HNM1, a second NMOS transistor HNM2, a third NMOS transistor HNM3, a fourth NMOS transistor HNM4, a fifth NMOS transistor HNM5, a sixth NMOS transistor HNM6, a seventh NMOS transistor HNM7, a first PMOS transistor HPM1, a second PMOS transistor HPM2, a third PMOS transistor HPM3, a fourth PMOS transistor HPM4, a first diode DZ1, a second diode DZ2, a third diode DZ3, a fourth diode DZ4, a fifth diode DZ5, a sixth diode DZ6, a first current source I1, a second current source I2, a third current source I3, a first inverter INV1, a first capacitor C1, a first resistor R1, and a driving output end; the source electrode of the first PMOS transistor HPM1, the source electrode of the second PMOS transistor HPM2, the drain electrode of the first NMOS transistor HNM1, the drain electrode of the fourth NMOS transistor HNM4, and the drain electrode of the seventh NMOS transistor HNM7 are all connected to the first power supply to access the input voltage, the gate electrode of the first PMOS transistor HPM1 is connected to the drain electrode of the first PMOS transistor HPM1, the gate electrode of the second PMOS transistor HPM2, and the input end of a first current source I1, and the output end of the first current source I1 is grounded; the drain electrode of the second PMOS transistor HPM2 is connected to the gate electrode of the first NMOS transistor HNM1, the cathode of the first diode DZ1 and the cathode of the second diode DZ2, the anode of the first diode DZ1 is connected to the cathode of the third diode DZ3, the anode of the third diode DZ3 is connected to the cathode of the fourth diode DZ4, the anode of the fourth diode DZ4 and one end of the first capacitor C1 are both grounded, and the other end of the first capacitor C1 is connected to the anode of the second diode DZ2, the source electrode of the first NMOS transistor HNM1, the source electrode of the third PMOS transistor HPM3 and the source electrode of the fourth PMOS transistor HPM 4; the grid electrode of the third PMOS tube HPM3 is connected with the grid electrode of the fourth PMOS tube HPM4, the drain electrode of the third PMOS tube HPM3, the drain electrode of the second NMOS tube HNM2 and the drain electrode of the third NMOS tube HNM 3; the grid electrode of the second NMOS tube HNM2 is connected with the output end of the first inverter INV1, and the input end of the first inverter INV1 is connected with the pulse circuit; the source electrode of the second NMOS tube HNM2 is connected with the input end of the second current source I2; a source electrode of the third NMOS tube HNM3 is connected to an input end of the third current source I3, and a gate electrode of the third NMOS tube HNM3 is connected to the sampling circuit to access the boost control signal DR _2; the drain electrode of the fourth PMOS transistor HPM4 is connected to the gate electrode of the fourth NMOS transistor HNM4, the drain electrode of the fifth NMOS transistor HNM5 and the cathode electrode of the fifth diode DZ 5; a source electrode of the fourth NMOS tube HNM4 is connected to an anode of the fifth diode DZ5, a drain electrode of the sixth NMOS tube HNM6, a source electrode of the seventh NMOS tube HNM7, an anode of the sixth diode DZ6, one end of the first resistor R1, and the driving output end; the grid electrode of the seventh NMOS tube HNM7 is connected to the cathode of the sixth diode DZ6 and the voltage boost circuit; the grid electrode of the fifth NMOS tube HNM5 and the grid electrode of the sixth NMOS tube HNM6 are both connected with the pulse circuit; the driving output end is used for being connected with the external power tube and outputting the driving voltage to the external power tube; the output end of the second current source I2, the output end of the third current source I3, the source electrode of the fifth NMOS tube HNM5, the source electrode of the sixth NMOS tube HNM6 and the other end of the first resistor R1 are all grounded.

In specific implementation, the voltage of the boosted voltage V8 is up to 2VCC-VDZ6, the driving voltage corresponding to the voltage is 2VCC-VDZ6-VGS _ HNM7, and VGS _ HNM7 is the gate-source voltage of the seventh NMOS transistor HNM 7. When the input voltage VDD is less than 2VCC-VDZ6-VGS _ HNM7, the driving voltage VGATE can reach VDD to the maximum (the maximum of the traditional circuit is VDD-VGS); when 2VCC-VDZ6-VGS _ HNM7< VDD <3 × VDZ _ CLAMP-VGS _ HNM1-VGS _ HNM4 (VDZ _ CLAMP is the voltage of the first diode DZ1, the third diode DZ3, and the fourth diode DZ4, VGS _ HNM1 is the gate-source voltage of the first NMOS transistor HNM1, and VGS _ HNM4 is the gate-source voltage of the fourth NMOS transistor HNM 4), the seventh NMOS transistor HNM7 is turned off, and the maximum VGATE voltage is VDD-VGS _ HNM1-VGS _ HNM4; when VDD >3VDZ _ CLAMP-VGS _ HNM1-VGS _ HNM4, the output drive voltage VGATE is clamped to 3 × VDZ _ CLAMP-VGS _ HNM1-VGS _ HNM4. The grid electrode of the external power tube is prevented from being damaged due to overhigh output driving voltage.

In the driving module, the grid-source current of the first PMOS tube HPM1 is equal to the current of the first current source I1, the HPM2 tube mirrors the current of the HPM1 (the mirror ratio of the HPM1 to the HPM2 is N: 1), and therefore the clamping current provided by the HPM2 is I1/N. When the VDD voltage is higher than 3 x vdz _clamp, the V1 voltage is clamped to 3 x vdz _clamp. The diodes DZ1, DZ3, DZ4 are clamping diodes. Diode DZ2 clamps the gate and source of the first NMOS tube HNM1, preventing the tube gate from breakdown. The first NMOS tube HNM1 provides a driving current for the third PMOS tube HPM3 and the fourth PMOS tube HPM 4. When the driving signal DR _ N is high, the pull-down tube fifth NMOS tube HNM5 quickly pulls down the voltage V3 to a low level, and turns off the fourth NMOS tube HNM4. Similarly, when the driving signal DR _ N is high, the pull-down sixth NMOS transistor HNM6 quickly pulls down the voltage of VGATE to a low level, and turns off the external power transistor driven later. Diode DZ5 clamps the gate and source of the fourth NMOS transistor HNM4 and diode DZ6 clamps the gate and source of the seventh NMOS transistor HNM7, preventing the transistor gate from being broken down.

It can be seen that, in the present embodiment, both the chip EMI is improved and the chip driving minimum voltage is increased. The driving capability when the input voltage is low is increased, and the switching efficiency of the power tube is improved. When the power supply voltage is input at a high level, the output voltage is clamped, and the damage caused by overhigh grid voltage of the output power is prevented.

In a possible embodiment, the current magnitude of the fourth PMOS transistor HPM4 is K times that of the third PMOS transistor HPM 3;

the third NMOS tube HNM3 is turned off when receiving the boost control signal DR _2 of a low level, so that the driving voltage is slowly increased, and the maximum charging current of the fourth PMOS tube HPM4 is K times of a second current, which is much smaller than a third current, the second current being the current of the second current source I2, and the third current being the current of the third current source I3;

the third NMOS tube HNM3 is turned on when receiving the boost control signal DR _2 of high level, so that the driving voltage rapidly rises, and the maximum charging current of the fourth PMOS tube HPM4 is K times the sum of the second current and the third current.

In a specific implementation, when the boost control signal DR _2 is at a low level, the third NMOS transistor HNM3 is turned off, and at this time, the charging current I6 of the third PMOS transistor HPM3 is equal to I2; therefore, the maximum charging current driving the fourth PMOS transistor HPM4 is K × I6= K × I2. Since I2< < I3, the maximum driving current of the fourth PMOS transistor HPM4 is small at this time, and the voltage V3 slowly rises, and VGATE also slowly rises, where VAGTE = V3-VGS _ HNM2.

When the boost control signal is at a high level, the third NMOS tube HNM3 is turned on. At this time, the charging current I6 of the third PMOS transistor HPM3 is equal to I2+ I3; therefore, the maximum charging current driving the fourth PMOS transistor HPM4 is K × I6= K (I2 + I3). Due to I2< < I3, the maximum driving current of the fourth PMOS transistor HPM4 is larger at this time, so that the voltage V3 rises rapidly, and VGATE also rises rapidly, where VAGTE = V3-VGS _ HNM4. Therefore, the driving current is changed from small to large, and the driving voltage has a slowly gradual change process from low to high. The di/dt sharp impact is reduced, and the EMI effect is improved.

It can be seen that, in the embodiment, the change rate of the voltage of VAGTE can be controlled by the boost control voltage, so that di/dt spike is reduced, and the EMI effect is improved.

The principle of the embodiments of the present application will be described below with reference to waveform diagrams.

Fig. 7 is a waveform diagram of various signals provided by an embodiment of the present application. As can be seen from fig. 7, when the GATE voltage (i.e., VGATE) is too low, the DR _2 signal is low, the GATE voltage rises slowly, and when the GATE voltage rises to a certain value and the DR _2 signal is high, the GATE voltage rises rapidly. Fig. 8 is a waveform diagram of a driving voltage varying with VDD according to an embodiment of the present application. As can be seen from the waveform diagram of fig. 8: when VDD < VL =2VCC-VDZ6-VGS _ HNM7, the output driving voltage amplitude is the highest VDD; when VL =2VCC-VDZ6-VGS _ HNM7< VDD < VH =3VDZ _CLAMP-VGS _ HNM1-VGS _ HNM4, the output driving voltage amplitude is at most VDD-VGS _ HNM1-VGS _ HNM4; VDD > VH =3vdz _clamp-VGS _ HNM1-VGS _ HNM4, the output is clamped to 3 x vdz _clamp-VGS _ HNM1-VGS _ HNM4.

The embodiment of the application provides a control chip circuit, the control chip circuit includes foretell drive circuit that fills soon. The quick charging driving circuit can be applied to the control chip so as to apply the driving circuit to corresponding scenes and realize corresponding functions.

The embodiment of the application provides a power adapter, and the quick charge driving circuit and the control chip circuit can be applied to the power adapter.

The embodiment of the application provides an electronic device, which may include the above-mentioned fast charging driving circuit or chip control circuit or power adapter, for example, the electronic device may be a charger or a charger.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications can be easily made by those skilled in the art without departing from the spirit and scope of the present invention, and it is within the scope of the present invention to include different functions, combination of implementation steps, software and hardware implementations.

Claims

1. A quick charge driving circuit is characterized by comprising a booster circuit, a driving circuit and a sampling circuit;

the driving circuit is connected with the first power supply and the pulse circuit, and is used for receiving the input voltage output by the first power supply and the driving signal output by the pulse circuit, outputting corresponding driving voltage according to the driving signal and driving the external power tube to realize the driving function;

the boosting circuit is connected with the driving circuit and used for outputting a boosting voltage to the driving circuit to increase the driving voltage when receiving the boosting control signal;

the sampling circuit comprises a fifth PMOS tube, a sixth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a fourth current source, a fifth current source and a second reverser;

a source electrode of the fifth PMOS tube is connected with a second power supply VCC, and a grid electrode of the fifth PMOS tube is connected with a grid electrode of the sixth PMOS tube, a drain electrode of the fifth PMOS tube, a drain electrode of the eighth NMOS tube and a grid electrode of the eighth NMOS tube; the source electrode of the eighth NMOS tube is connected with the drain electrode and the grid electrode of the ninth NMOS tube; the source electrode of the sixth PMOS tube is connected with the driving output end of the driving circuit, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the tenth NMOS tube and the input end of the fifth current source; the drain electrode of the tenth NMOS tube is connected with the output end of the fourth current source and the input end of the second inverter; the input end of the fourth current source is connected with the second power supply VCC; the source electrode of the ninth NMOS transistor, the source electrode of the tenth NMOS transistor and the output end of the fifth current source are all grounded; the output end of the second inverter is connected with the driving circuit and the boosting circuit to output a boosting control signal.

2. The fast charge driving circuit according to claim 1, wherein the driving circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a first current source, a second current source, a third current source, a first inverter, a first capacitor, a first resistor, and the driving output terminal;

the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the drain electrode of the first NMOS tube, the drain electrode of the fourth NMOS tube and the drain electrode of the seventh NMOS tube are all connected with the first power supply to be connected with the input voltage, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the input end of the first current source, and the output end of the first current source is grounded;

the drain electrode of the second PMOS tube is connected with the grid electrode of the first NMOS tube, the cathode of the first diode and the cathode of the second diode, the anode of the first diode is connected with the cathode of the third diode, the anode of the third diode is connected with the cathode of the fourth diode, the anode of the fourth diode and one end of the first capacitor are both grounded, and the other end of the first capacitor is connected with the anode of the second diode, the source electrode of the first NMOS tube, the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube;

the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube; the grid electrode of the second NMOS tube is connected with the output end of the first reverser, and the input end of the first reverser is connected with the pulse circuit; the source electrode of the second NMOS tube is connected with the input end of the second current source; the source electrode of the third NMOS tube is connected with the input end of the third current source, and the grid electrode of the third NMOS tube is connected with the output end of the second reverser so as to access the boosting control signal; the drain electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube and the cathode of the fifth diode; the source electrode of the fourth NMOS tube is connected with the anode of the fifth diode, the drain electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the anode of the sixth diode, one end of the first resistor and the drive output end; the grid electrode of the seventh NMOS tube is connected with the cathode of the sixth diode and the booster circuit; the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are both connected with the pulse circuit;

the driving output end is used for being connected with the external power tube and outputting the driving voltage to the external power tube;

the output end of the second current source, the output end of the third current source, the source electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube and the other end of the first resistor are all grounded.

3. The fast charging driving circuit according to claim 2, wherein the boost circuit comprises a third inverter, a first and gate, a fourth inverter, a seventh PMOS transistor, an eighth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a second capacitor, and a seventh diode;

the input end of the third inverter is connected with the pulse circuit to access the driving signal, and the output end of the third inverter is connected with the first input end of the first AND gate; the second input end of the first AND gate is connected with the output end of the second inverter, and the output end of the first AND gate is connected with the input end of the fourth inverter; the output end of the fourth inverter is connected with the grid electrode of the seventh PMOS tube, the grid electrode of the eleventh NMOS tube, the grid electrode of the eighth PMOS tube and the grid electrode of the twelfth NMOS tube; the source electrode of the seventh PMOS tube and the anode of the seventh diode are both connected with the second power supply VCC; the drain electrode of the seventh PMOS tube is connected with the cathode of the second capacitor and the drain electrode of the eleventh NMOS tube; the cathode of the seventh diode is connected with the anode of the second capacitor and the source electrode of the eighth PMOS tube; the drain electrode of the eighth PMOS tube is connected with the drain electrode of the twelfth NMOS tube, the grid electrode of the seventh NMOS tube and the cathode of the sixth diode; the source electrode and the substrate of the eleventh NMOS transistor are grounded, and the source electrode and the substrate of the twelfth NMOS transistor are grounded.

4. A fast charge driving circuit according to claim 3,

the third inverter is used for inverting the phase of the driving signal to obtain an inverted driving signal; the first AND gate is used for performing AND operation on the inverted driving signal and the boosting control signal and outputting an initial driving signal; the fourth inverter is used for inverting the initial driving signal to obtain a target driving signal;

if the driving signal is at a low level and the boost control signal is at a high level, the target driving signal is at a low level; when the target driving signal is at a low level, the seventh PMOS transistor is turned on, the eleventh NMOS transistor is turned off, the voltage of the positive electrode of the second capacitor is increased, the eighth PMOS transistor is turned on, and the boosted voltage is output to the driving circuit to increase the driving voltage;

if the driving signal is at a high level, the target driving signal is at a high level; when the target driving signal is at a high level, the seventh PMOS transistor and the eighth PMOS transistor are both turned off, the eleventh NMOS transistor and the twelfth NMOS transistor are turned on, the negative electrode of the second capacitor is grounded through the eleventh NMOS transistor, and the boost voltage is changed to a low level to stop boosting the driving voltage before the voltage of the positive electrode of the second capacitor is restored to an increased level.

5. A fast charge driving circuit according to claim 3,

the sixth PMOS tube is used for sampling the driving voltage;

when the driving voltage is smaller than the sum of the gate-source voltage of the sixth PMOS transistor, the gate-source voltage of the eighth NMOS transistor, and the gate-source voltage of the ninth NMOS transistor, the sixth PMOS transistor is turned off, the gate voltage of the tenth NMOS transistor is pulled down to a low level by the fifth current source, the tenth NMOS transistor is turned off, the drain voltage of the tenth NMOS transistor is increased to a high level by the fourth current source, and the drain voltage of the tenth NMOS transistor is inverted by the second inverter to obtain the low-level boost control signal;

when the driving voltage is greater than the sum of the gate-source voltage of the sixth PMOS transistor, the gate-source voltage of the eighth NMOS transistor, and the gate-source voltage of the ninth NMOS transistor, the sixth PMOS transistor is turned on, the gate voltage of the tenth NMOS transistor is pulled up to a high level by the sixth PMOS transistor, the tenth NMOS transistor is turned on and pulls down the drain voltage of the tenth NMOS transistor to a low level, and the second inverter inverts the drain voltage of the tenth NMOS transistor to obtain the high-level boost control signal.

6. A fast charge driving circuit according to claim 3,

the current of the fourth PMOS tube is K times of that of the third PMOS tube;

the third NMOS tube is turned off when receiving the low-level boost control signal, so that the driving voltage is slowly increased, and the maximum charging current of the fourth PMOS tube is K times of a second current, wherein the second current is far less than a third current, the second current is the current of the second current source, and the third current is the current of the third current source;

and the third NMOS tube is conducted when receiving the high-level boosting control signal, so that the driving voltage is quickly increased, and the maximum charging current of the fourth PMOS tube is K times of the sum of the second current and the third current.

7. A control chip circuit, characterized in that the control chip circuit comprises a fast charging driving circuit according to any one of claims 1 to 6.

8. A power adapter, characterized in that the power adapter comprises a fast charging driving circuit as claimed in any one of claims 1 to 6, or a control chip circuit as claimed in claim 7.

9. An electronic device, characterized in that the electronic device comprises a fast charge driving circuit according to any one of claims 1 to 6, or a control chip circuit according to claim 7, or a power adapter according to claim 8.