JPH04108215A - Booster circuit - Google Patents
Booster circuitInfo
- Publication number
- JPH04108215A JPH04108215A JP2227593A JP22759390A JPH04108215A JP H04108215 A JPH04108215 A JP H04108215A JP 2227593 A JP2227593 A JP 2227593A JP 22759390 A JP22759390 A JP 22759390A JP H04108215 A JPH04108215 A JP H04108215A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- mosfet
- boosting
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 238000010586 diagram Methods 0.000 description 6
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
Lt上立肌■立五
この発明は昇圧回路に関し、特に昇圧回路の昇圧スピー
ドを速くする回路に関する。DETAILED DESCRIPTION OF THE INVENTION This invention relates to a booster circuit, and more particularly to a circuit that increases the boosting speed of a booster circuit.
従来囚伎1
従来、この種の昇圧回路は、第4図に示すように、ダイ
オードD8とMOS F E T T4− Taで
構成されるインバータの出力を、ダイオードD2.D、
を直列接続したダイオードD2のアノードである一端に
接続し、ダイオードD3のカソードである他端は昇圧回
路の出力端とし、ダイオードD2のアノードにコンデン
サC1の一端を、ダイオードD2のカソードとダイオー
ドD3のアノードの接続点にコンデンサC2の一端を接
続し、コンデンサC1の他端を発振器6の第1の出力φ
に接続し、コンデンサC2の他端を発振器すの第1の出
力φと逆位相の第2の出力φに接続し、昇圧回路の出力
端とGND間に昇圧回路がON→OFF時の放電用のM
OSFET T3を接続し、ダイオードD3のカソー
ドとMO8FETT3のドレインの接続点をゲート抵抗
R,を介して、電源端子と出力端子OUT間にドレイン
ソースを接続したMOSFET T2のゲートに接続
し5、さらにMOSFET Ta、T7で構成される
インバータの出力を、前述のMO3FETT4.T5で
構成されるインバータの入力に接続し、昇圧信号V工に
より昇圧回路を動作させるという回路になっている。Conventional Problem 1 Conventionally, as shown in FIG. 4, this type of booster circuit connects the output of an inverter composed of a diode D8 and a MOS FET T4-Ta to a diode D2. D.
is connected to one end which is the anode of the diode D2 connected in series, the other end which is the cathode of the diode D3 is used as the output terminal of the booster circuit, one end of the capacitor C1 is connected to the anode of the diode D2, and the cathode of the diode D2 and the diode D3 are One end of capacitor C2 is connected to the connection point of the anode, and the other end of capacitor C1 is connected to the first output φ of oscillator 6.
Connect the other end of the capacitor C2 to the second output φ that is in opposite phase to the first output φ of the oscillator, and connect the output terminal of the booster circuit to GND for discharging when the booster circuit turns from ON to OFF. M of
Connect OSFET T3, and connect the connection point between the cathode of diode D3 and the drain of MOSFET T3 via a gate resistor R, to the gate of MOSFET T2 whose drain source is connected between the power supply terminal and the output terminal OUT. The output of the inverter composed of Ta and T7 is connected to the aforementioned MO3FET T4. The circuit is connected to the input of the inverter made up of T5, and operates the boost circuit using the boost signal V.
この昇圧回路は、第5図囚に示すように、昇圧信号V
s カL = Hニ変化t ルト、MO5FETT、、
T7で構成されるインバータのMOSFET T、が
ONL、応じてMOSFET T4tT5で構成され
るインバータのMOSFET T。As shown in FIG. 5, this booster circuit uses a booster signal V
s L=H change t, MO5FETT,,
The inverter MOSFET T, consisting of T7, is ONL, and accordingly the inverter MOSFET T, consisting of MOSFET T4tT5.
がONするため、昇圧回路の出力VO3は、第5図(B
)に示すように、D□→T4→D2→D3の経路でV。is turned on, the output VO3 of the booster circuit is as shown in Fig. 5 (B
), V on the path D□→T4→D2→D3.
C3VFまで速く立上がった後、発振回路すの等価内部
インピーダンスとコンデンサC11C2の時定数により
、ゆっくりと電源電圧VCC以上の飽和電圧V。Pに昇
圧されていくという動作となっていた。After quickly rising to C3VF, the saturation voltage V slowly rises to be higher than the power supply voltage VCC due to the equivalent internal impedance of the oscillation circuit and the time constant of the capacitor C11C2. The operation was such that the voltage was increased to P.
Il イ 。Il .
ところで、上記の従来の昇圧回路は、ダイオードD1と
ダイオードD2.D3が直列回路となっているため、昇
圧信号がL−Hに変化すると、昇圧回路の出力VO3は
、Vcc 3Vpまでは速く立上がるが、その後、飽
和電圧V。Pに昇圧される時間TRQ(。わが長く、ダ
イオードD、〜D3の順方向電圧の和であるaVp分、
昇圧速度が遅くなるという欠点があった。By the way, the above-mentioned conventional booster circuit includes a diode D1, a diode D2 . Since D3 is a series circuit, when the boost signal changes from L to H, the output VO3 of the boost circuit rises quickly up to Vcc 3Vp, but then reaches the saturation voltage V. The time TRQ (aVp, which is the sum of the forward voltages of diodes D and D3,
There was a drawback that the pressure increase rate was slow.
−の
この発明の昇圧回路は、ソースを前記昇圧回路の出力端
に、ドレインを電源端子に接続したMOSFET T
、を設け、昇圧信号を微分する微分回路の出力端にゲー
トを接続した構成となっている。- The booster circuit of the present invention includes a MOSFET T whose source is connected to the output terminal of the booster circuit and whose drain is connected to the power supply terminal.
, and the gate is connected to the output terminal of a differentiating circuit that differentiates the boosted signal.
作l−
上記の構成によると、微分回路の出力電圧が昇圧信号の
変化と同時に変化し、前記電圧がソースを昇圧回路の出
力端にドレインを電源端子に接続したMOSFET
’TIのゲートを駆動し、昇圧回路の出力電圧を、ダイ
オードの順方向電圧に影響されることなく、電源電圧ま
で速く立上がらせることができる。According to the above configuration, the output voltage of the differentiating circuit changes simultaneously with the change in the boost signal, and the voltage is applied to the MOSFET whose source is connected to the output terminal of the boost circuit and whose drain is connected to the power supply terminal.
'By driving the gate of TI, the output voltage of the booster circuit can be quickly raised to the power supply voltage without being affected by the forward voltage of the diode.
災胤桝
以下、この発明について図面を参照して説明する。第1
図は、この発明の一実施例の回路図、第2図は第1図に
示す回路の各部波形である。図において、T、、T2.
T3.T5.T7.TsはNチャンネルMO8FET1
T4− T6.TsはPチャンネルMOS F E T
lD 0. D2− D3はダイオード、R1はM O
S F E T T 2のゲート抵抗、ClIC2は
コンデンサ、bは発振器、aはコンデンサC3と抵抗R
2で構成される微分回路、Vlは昇圧信号、VILは微
分回路aの出力電圧、Vbは微分回路aの入力電圧、V
arは昇圧回路の出力電圧である。Below, this invention will be explained with reference to the drawings. 1st
The figure is a circuit diagram of an embodiment of the present invention, and FIG. 2 shows waveforms of various parts of the circuit shown in FIG. 1. In the figure, T, , T2.
T3. T5. T7. Ts is N-channel MO8FET1
T4-T6. Ts is P channel MOS FET
lD 0. D2-D3 are diodes, R1 is MO
S F E T T 2 gate resistance, ClIC2 is the capacitor, b is the oscillator, a is the capacitor C3 and resistor R
2, Vl is the boost signal, VIL is the output voltage of the differentiator a, Vb is the input voltage of the differentiator a, V
ar is the output voltage of the booster circuit.
次に、上記の実施例の動作について説明する。Next, the operation of the above embodiment will be explained.
昇圧信号v1が第2図(2)のようにL−4−Hに変化
すると、微分回路aの入力電圧vbが第2図(B)のよ
うにL−Hに変化し、応じて微分回路aのコンデンサC
3が充電され、微分回路出力V、が、第2図(C)に示
すように変化し、この電圧がMOS F ET T、
のゲートを駆動し、MOSFET T。When the boost signal v1 changes to L-4-H as shown in Fig. 2 (2), the input voltage vb of the differentiating circuit a changes to L-H as shown in Fig. 2 (B), and the differentiating circuit changes accordingly. a capacitor C
3 is charged, the differential circuit output V, changes as shown in FIG. 2(C), and this voltage
MOSFET T.
がコンデンサC3の放電が終わるまでONする。remains ON until capacitor C3 finishes discharging.
この放電時間をT’nt+。1以下の時間にコントロー
ルし、MOSFET T+のバックゲートをGNDに
接続することにより、昇圧回路の出力電圧voIはMO
SFET T、のON電圧をVTIとすると、第2図
CD)に示すように、Voo−V丁、まで急峻に立上が
り、VCC−VTI以上に昇圧された後、MOSFET
T、がOFFするため、電源への流れ込みが防げる
。This discharge time is T'nt+. By controlling the time to be less than 1 and connecting the back gate of MOSFET T+ to GND, the output voltage voI of the booster circuit is
If the ON voltage of SFET T is VTI, as shown in Figure 2 (CD), it rises steeply to Voo-Vd, and after being boosted to VCC-VTI or higher, the MOSFET
Since T is turned off, the flow into the power supply can be prevented.
ここで、vT□<3Vpで、かつ昇圧速度が一定である
ため、昇圧回路の出力電圧V。1がVCC−飽和電圧を
v。Pとすると、Vcp (Vcc Vt1)(V
cp (V cc 3 V p )となり、昇圧
回路出力の飽和電圧V。pに達するまでの飽和時間T
RI+。N]が、従来のTR2+ONIよりも格段に短
くなる。Here, since vT□<3Vp and the boosting speed is constant, the output voltage of the booster circuit is V. 1 is VCC - saturation voltage v. When P, Vcp (Vcc Vt1) (V
cp (V cc 3 V p ), which is the saturation voltage V of the booster circuit output. Saturation time T until reaching p
RI+. N] is much shorter than the conventional TR2+ONI.
なお、負論理入力とする場合は、微分回路aの前段に設
けたMOS F E T To 、T7で構成される
インバータはなくてもよい。Note that in the case of negative logic input, the inverter composed of MOS FET To and T7 provided at the front stage of the differentiating circuit a may not be provided.
災胤阻2
第3図は、この発明の第2の実施例の回路図である。こ
の実施例は、MOSFET T、のバックゲートを微
分回路aの入力7秒に接続した点を除いては第1の実施
例と同様であるため説明を省略する。この実施例では、
上記の構成により、MOSFET T1のON電圧V
T t カ低くなり、昇圧速度をなおいっそう速くする
ことができる。Disaster prevention 2 FIG. 3 is a circuit diagram of a second embodiment of the present invention. This embodiment is the same as the first embodiment except that the back gate of MOSFET T is connected to the 7-second input of the differentiating circuit a, so a description thereof will be omitted. In this example,
With the above configuration, the ON voltage V of MOSFET T1
T t becomes lower, and the pressure increase rate can be made even faster.
!肌Ω立果
以上説明したように、本発明は、昇圧信号により制御さ
れるダイオードとコンデンサと発振器とインバータで構
成される昇圧回路において、ソースを前記昇圧回路の出
力端に、ドレインを電源端子に接続したMOSFETを
設け、昇圧信号を微分する微分回路の出力端にゲートを
接続することにより、昇圧回路の出力電圧をダイオード
の順方向電圧に影響されることなく電源電圧まで速く立
上がらせることができるため、昇圧回路の出力電圧の飽
和時間が短くなり、昇圧速度が速くできる効果がある。! Results As explained above, the present invention provides a booster circuit that is controlled by a booster signal and includes a diode, a capacitor, an oscillator, and an inverter, in which the source is connected to the output terminal of the booster circuit and the drain is connected to the power supply terminal. By providing a connected MOSFET and connecting the gate to the output terminal of the differentiating circuit that differentiates the boost signal, the output voltage of the boost circuit can be quickly raised to the power supply voltage without being affected by the forward voltage of the diode. This has the effect of shortening the saturation time of the output voltage of the booster circuit and increasing the boosting speed.
第1図はこの発明の実施例1の回路図、第2図は第1図
の回路の各部波形図、第3図はこの発明の実施例2の回
路図、第4図は従来技術の回路図、第5図は第4図の各
部波形図である。
a・・・微分回路、
b・・・発振器、
T1〜T8・・・MOS F E T1C1〜C3・・
・コンデンサ、
D、〜D3・・・ダイオード、
R□I R2・・・抵抗、
VCC・・・電源電圧、
OUT・・・出力端子、
■F・・・ダイオード順方向電圧、
VI・・・昇圧信号、
φ、φ・・・発振器出力、
TDHON)・・・ターンオン時間、
vctt Vc21 VO3・・・昇圧回路出力電圧、
Vb・・・微分回路入力電圧、
■、・・・微分回路出力電圧、
TRI(。N l t T R2F。、・・・昇圧時間
、vcp・・・飽和電圧、
V1□・・・MOSFET T、のしきい値電圧。Fig. 1 is a circuit diagram of Embodiment 1 of the present invention, Fig. 2 is a waveform diagram of each part of the circuit of Fig. 1, Fig. 3 is a circuit diagram of Embodiment 2 of this invention, and Fig. 4 is a circuit of the prior art. 5 are waveform diagrams of various parts of FIG. 4. a... Differential circuit, b... Oscillator, T1-T8... MOS F E T1C1-C3...
・Capacitor, D, ~D3...Diode, R□I R2...Resistor, VCC...Power supply voltage, OUT...Output terminal, ■F...Diode forward voltage, VI...Step up Signal, φ, φ...Oscillator output, TDHON)...Turn-on time, vctt Vc21 VO3...Booster circuit output voltage,
Vb...Differentiator circuit input voltage, ■,...Differentiator circuit output voltage, TRI(.N l t T R2F.,...Boost time, vcp...Saturation voltage, V1□...MOSFET T, threshold voltage.
Claims (1)
振器とインバータで構成される昇圧回路において、 ソースを前記昇圧回路の出力端に、ドレインを電源端子
に接続したMOSFETを設け、昇圧信号を微分する微
分回路の出力端にゲートを接続したことを特徴とする昇
圧回路。[Scope of Claims] In a booster circuit including a diode, a capacitor, an oscillator, and an inverter that are controlled by a booster signal, a MOSFET whose source is connected to the output terminal of the booster circuit and whose drain is connected to a power supply terminal is provided, and the booster circuit is controlled by a booster signal. A booster circuit characterized in that a gate is connected to the output terminal of a differentiating circuit that differentiates the voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2227593A JPH04108215A (en) | 1990-08-28 | 1990-08-28 | Booster circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2227593A JPH04108215A (en) | 1990-08-28 | 1990-08-28 | Booster circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04108215A true JPH04108215A (en) | 1992-04-09 |
Family
ID=16863355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2227593A Pending JPH04108215A (en) | 1990-08-28 | 1990-08-28 | Booster circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04108215A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000008759A1 (en) * | 1998-08-03 | 2000-02-17 | Hitachi, Ltd. | Mos integrated circuit |
CN115314033A (en) * | 2022-10-09 | 2022-11-08 | 深圳英集芯科技股份有限公司 | Quick charging driving circuit and related product |
-
1990
- 1990-08-28 JP JP2227593A patent/JPH04108215A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000008759A1 (en) * | 1998-08-03 | 2000-02-17 | Hitachi, Ltd. | Mos integrated circuit |
CN115314033A (en) * | 2022-10-09 | 2022-11-08 | 深圳英集芯科技股份有限公司 | Quick charging driving circuit and related product |
CN115314033B (en) * | 2022-10-09 | 2023-03-07 | 深圳英集芯科技股份有限公司 | Quick charging driving circuit and related product |
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