WO2000008759A1

WO2000008759A1 - Mos integrated circuit

Info

Publication number: WO2000008759A1
Application number: PCT/JP1998/003440
Authority: WO
Inventors: Toshiro Tsukada; Keiko Fukuda; Masanori Otsuka; Akihiro Kitagawa; Shuzo Ichiki
Original assignee: Hitachi, Ltd.
Priority date: 1998-08-03
Filing date: 1998-08-03
Publication date: 2000-02-17

Abstract

A MOS integrated circuit for driving an analog circuit, e.g. an analog switch, with a low power supply voltage by outputting a control voltage of high signal level exceeding the differential voltage (full scale) between the power supply voltage and the ground voltage, wherein a semiconductor element for blocking reverse current flow is provided in any one of a current path comprising a pMOS transistor formed between a first power supply and the output terminal or a current path comprising an nMOS transistor formed between a second power supply and the output terminal, and a circuit means for shifting the voltage through capacitive coupling is provided at the output terminal.

Description

Specification

MOS integrated circuit

Technical field

The present invention relates to a MOS (Metal Oxide Semiconductor) integrated circuit, and more particularly to a MOS integrated circuit provided with a drive circuit for driving an analog circuit.

Background art

Complementary MOS 'ICs (hereinafter referred to as "CMOS' ICs") that use a combination of a p-channel MOS transistor and an n-channel MOS transistor as a basic element have their logic gates (invar, NAND, NOR, etc.) Can output a signal amplitude up to the full scale, which is the difference voltage between the power supply voltage Vdd and the ground voltage Vss, and very little current flows when the output signal is at the power supply voltage Vdd or the ground voltage Vss Therefore, it has the advantage of low power consumption, and is most often used in MOS ICs.

The degree of integration of MOS and IC is increasing year by year, and accordingly, the dimensions of transistors are becoming finer, and the CMOS process is becoming finer. Since miniaturization of transistor dimensions inevitably causes a decrease in the withstand voltage of the transistor, the power supply voltage Vdd of the CMOS IC has been steadily decreasing, and it has been 5 V for a long time to 3 V. Recently it has become lower. Therefore, the output amplitude of the logic gate is also reduced.

In the case where a logic gate of a CMOS IC using the above miniaturization process is used as a drive circuit for driving an analog circuit such as a MOS analog switch, the drive becomes insufficient due to insufficient amplitude. There is. It is necessary to apply a drive voltage sufficiently exceeding Vgs-Vth to the MOS gate terminal of the analog switch, with the gate-source voltage being Vgs and the threshold voltage being Vth. It is necessary, but it cannot be secured.

As a circuit for increasing the output amplitude of the logic gate, a circuit for shifting the signal level (for example, refer to Japanese Patent Application Laid-Open No. Hei 7-'2162) or a voltage conversion is performed to increase the amplitude. There has been proposed a circuit (for example, see Japanese Patent Application Laid-Open No. 8-87008).

The former circuit uses a step-down circuit and a step-up circuit to expand the voltage range supplied to the MOS gate of the analog switch. However, the step-down circuit and the step-up circuit are configured using switches that cannot be realized with ordinary CMOS ICs. The latter circuit uses a voltage conversion circuit that uses a separate power supply, in addition to a circuit that combines bipolar and CMOS circuits. As described above, the conventional drive circuit requires a separate circuit and a separate power supply, which further increases the cost, and is difficult to apply to recent miniaturized and low-cost CMOS ICs. . Disclosure of the invention

Fig. 17 shows a general example in which a CMOS circuit mounted on a CMOS IC is used as a drive circuit for driving a MOS analog switch. The CMOS inverter includes an n-channel MOS transistor (hereinafter simply referred to as “nMOS transistor”) 1 and a p-channel MOS transistor (hereinafter simply referred to as “pMOS transistor”) 2. The gate terminals of both transistors are connected to each other to become input terminal 6, a current path is formed by the pMOS transistor 2 between the power supply and the output terminal 20, and an nMOS transistor is connected between the ground and the output terminal 20. A current path is formed by the transistor 1.

In such a CMOS circuit, the control signal Vc is output by inverting the input signal Φ at the input terminal 6. The voltage Vc is supplied to the MOS gate terminal of the analog switch SW as a drive voltage, and controls on / off of the analog switch SW. When the analog switch SW is turned on, the switch SW A voltage Vout equal to the voltage Vin input to one terminal is output to the other terminal.

When the switch SW is an nMOS transistor, in order for the switch SW to perform a sufficient on-off operation, the effective gate voltage Vgs—Vth is

Vgs- Vth »0 (ON operation)

Vgs-Vth «0 (OFF operation)

Need to be In this case, Vgs is Vc—Vin, so

Vgs-Vth = Vc-Vin-Vth »0 (ON operation)

Vgs-Vth = Vc-Vin-Vth «0 (OFF operation)

That is,

Vc »Vin + Vth (ON operation)

Vc «Vin + Vth (OFF operation)

The analog switch SW requires that the control voltage Vc be sufficiently higher than Vin + Vth to be turned on, and that Vc be sufficiently lower than Vin + Vth to be turned off.

In normal CMOS circuits, the high level of Vc is limited by the power supply voltage Vdd. Therefore, if Vdd decreases with the miniaturization process, Vc also decreases. As a result, the high level of the effective gate voltage (Vgs-Vth) of the analog switch SW decreases, and the ON operation becomes insufficient. Now, consider the case where the switch SW switches (turns on) the input voltage Vin of the intermediate voltage (Vdd + Vss) / 2 by the control voltage Vc of the power supply voltage Vdd. 5 V, Vss2 0 V, Vth = 1.0 V)

Vgs— Vth = Vc— (Vin + Vth) = 1.5 V

However, miniaturized CMOS (e.g., Vdd = 2 V, Vss = 0 V, Vth = 0. 6 V)

Vgs-Vth = Vc- (Vin + Vth) = 0.4 V

It can be seen that the high level of the effective gate voltage (Vgs-Vth) drops from 1.5 V to 0.4 V, and the ON operation of the switch SW becomes extremely insufficient.

On the other hand, in a normal CMOS inverter, the low level of Vc is limited by the ground voltage Vss.

Consider the case where the switch SW switches (turns off) the input voltage Vin of the ground voltage Vss by the control voltage Vc of the ground voltage Vss. In the case of a conventional CMOS (eg, Vdd = 5 V, Vss = 0) V, Vth = 1.0 V)

Vgs-Vth = Vc-(Vin + Vth) = ー 1.0 V

On the other hand, in a miniaturized CMOS (eg, Vdd = 2 V, Vss−20 V, Vth = 0.6 V),

Vgs— Vth = Vc— (Vin + Vth) = — 0.6 V

And the low level of the effective gate voltage (Vgs-Vth) is from -1.0 to -0.0.

Go up to 6 V. However, the reduction of the effective gate voltage amplitude is not as large as in the case of ON, and therefore, the effect is smaller than in the case of ON.

In the above, the case where the analog switch SW is an nMOS transistor has been described.However, the case where the switch SW is a pMOS transistor can be similarly described. And it becomes difficult to drive the analog switch in a normal CMOS chamber.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art, and to output a control signal having a high signal level exceeding a difference voltage (full scale) between a power supply voltage and a ground voltage, thereby achieving low power supply voltage. An object of the present invention is to provide a MOS integrated circuit capable of driving an analog circuit such as an analog switch. The object of the present invention is to reduce a current path formed by a pMOS transistor formed between a first power supply and an output terminal and a current path formed by an nMOS transistor formed between a second power supply (for example, ground) and an output terminal. Both can be achieved by a drive circuit in which a semiconductor element for preventing current backflow is added to one of the current paths and a circuit means for shifting the voltage by capacitive coupling is provided at the output terminal. The voltage shift circuit means includes a capacitance element having one terminal connected to the output terminal and a logical gate connected to the other terminal of the capacitance element. The logic gate delays an input signal to the input terminal of the drive circuit for a predetermined time, and outputs an inverted signal as a voltage change.

This predetermined delay time is a precharge period in which the capacitance element is charged by the current from the current path. The logic gate outputs the voltage change at the same time as the end of the precharge period. The voltage change is transmitted to the output terminal via the capacitor.

By this voltage transmission, the voltage at the output terminal either exceeds the first power supply voltage or falls below the second power supply voltage, and becomes a control voltage having a signal level exceeding the full scale. The added semiconductor element prevents a current from flowing back to the pMOS transistor or the nMOS transistor by such a control voltage.

With the above-described analog switch driving method, a signal level exceeding the full scale can be secured, and a sufficient effective gate voltage for switching the analog switch can be obtained. Further, the above-described voltage shift circuit means by capacitive coupling and the semiconductor element for preventing current backflow can be formed by a miniaturized CMOS process, and can be easily incorporated into a MOS integrated circuit operating at a low power supply voltage. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram for explaining a first embodiment of a MOS integrated circuit according to the present invention, and FIG. 2 is an operation timing for explaining the first embodiment of the present invention. FIG. 3 is a cross-sectional view of the integrated circuit structure for explaining the first embodiment of the present invention, and FIG. 4 is a sectional view of the integrated circuit structure of the present invention.

FIG. 5 is a circuit diagram for explaining a second embodiment of the present invention, FIG. 5 is a cross-sectional view of an integrated circuit structure for explaining a second embodiment of the present invention, and FIG. FIG. 7 is a circuit diagram for explaining a third embodiment; FIG. 7 is a waveform diagram showing operation timing for explaining a third embodiment of the present invention;

FIG. 8 is a cross-sectional view of an integrated circuit structure for explaining a third embodiment of the present invention. FIG. 9 is a circuit diagram for explaining a fourth embodiment of the present invention. FIG. 10 is a circuit diagram for explaining a fifth embodiment of the present invention, and FIG. 11 is a circuit diagram for explaining a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram for explaining a seventh embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation timing for explaining the seventh embodiment of the present invention. FIG. 14 is an integrated circuit structure for explaining the seventh embodiment of the present invention. FIG. 15 is a circuit diagram for explaining an eighth embodiment of the present invention, and FIG. 16 is a circuit diagram for explaining a ninth embodiment of the present invention. FIG. 17 is a circuit diagram, and FIG. 17 is a circuit diagram for explaining a conventional MOS integrated circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a MOS integrated circuit according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. In FIGS. 1 to 17, those having the same functions are denoted by the same reference symbols, and their repeated description will be omitted. (Example 1)

In FIG. 1, 3 is a pn junction diode (hereinafter simply referred to as a “diode”) connected between the drain terminal of pMOS transistor 2 and output terminal 20, and 4 is the drain terminal and output terminal 2 of nMOS transistor 1. A diode connected between 0, 5 is a signal line connecting the output terminal 20 to the gate terminal of the analog switch SW, and C is a capacitive element having one terminal connected to the output terminal 20, that is, the signal line 5. Numeral 8 denotes an inverter connected to the other terminal of the capacitor C (hereinafter referred to as “capacitor C”). Inverter 7 is formed by transistors 1 and 2, diodes 3 and 4, and input / output terminals 5 and 20. The inverter 8 and the capacitor C to which the input signal 与え is applied form voltage shift circuit means by the above-described capacitive coupling, and the MOS drive for driving the analog switch SW by the circuit means and the inverter 7. A circuit is formed.

The capacitance C is driven by the inverter 8 and when the output signal of the inverter 8 changes according to the input signal Ψ, the level change is transmitted to the signal line 5 via the capacitor C. Thereby, the amplitude of the control voltage Vc is enlarged. On / off of the analog switch SW is controlled by the control voltage Vc, and when the analog switch SW is turned on, a voltage Vout having a value equal to the input voltage Vin is output to the other terminal of the switch SW. Either nMOS or pMOS transistors can be used for the switch SW.

A first current path is formed between the power supply of voltage Vdd (first power supply) and the output terminal 5 by the transistor 2, and a transistor is connected between the output terminal 5 and the ground of the voltage Vss (second power supply). 1 forms a second current path. Then, the stray capacitance (not shown) of the signal line 5 and the capacitance C are charged by the current of the first current path, and the stray capacitance of the signal line 5 and the capacitance to the capacitance C are charged by the current of the second current path. Discharge is performed to invert the input signal Φ Output signal is obtained.

The operation of such a MOS drive circuit will be described in more detail with reference to the timing waveform shown in FIG. When the input signal Φ goes low during the precharge period T1 for charging the capacitor C, the pMOS transistor 2 of the inverter turns on and the nMOS transistor 1 turns off. As a result, the charging current is supplied from the power supply Vdd to the signal line 5, and the control voltage Vc increases. Assuming that the forward voltage of diode 3 is Vf, the voltage Vc reaches Vc = Vdd-Vf. In the period T1, the input signal の of the inverter 8 is at a high level, and the output voltage Vb of the inverter 8 is at a low level Vss. Therefore, the charging voltage of the capacitor C is approximately Vc_Vss.

Subsequently, when the input signal Ψ is changed to a low level during the switching period T2 of the switch SW, that is, when the input signal になる becomes low after a delay of the period T1 from the input signal Φ, an inverting signal is generated. 8 is inverted and the output voltage Vb changes to the high level Vdd. This voltage change is almost equal to (Vdd-Vss) and is transmitted to the signal line 5 through the capacitor C. The voltage Vc shifts by (Vdd-Vss) to the high voltage level, and Vc = Vdd-Vf + (Vdd-Vss). Since (Vd-Vss) is generally larger than Vf, Vc> Vdd, and it can be seen that the high voltage level exceeds the power supply voltage. At this time, the signal line 5 is separated by the reverse bias of the diode 3 and the off operation of the nMOS transistor 1, so that the shifted high voltage level is maintained in the period T2.

Next, when the input signal Φ changes to a high level during the precharge period T3 for discharging the capacitor C, the pMOS transistor 2 of the inverter 7 turns off and the nMOS transistor 1 turns on. As a result, a discharge current flows from the signal line 5 to Vss, and the voltage Vc decreases. Assuming that the forward voltage of the diode 4 is Vf, the voltage Vc reaches Vc−Vss + Vf. In period T3, The input signal の at night 8 remains low, and the output voltage Vb at night 8 is high Vdd. Therefore, the charging voltage of the capacitor C is almost Vc-Vdd.

Next, when the input signal Ψ is set to the high level during the switching period T4 of the switch SW, that is, when the input signal になる is set to the high level with a delay of the period T3 from the input signal Φ, the inverter 8 is inverted. The output voltage Vb changes to the low level Vss. This voltage change (Vdd-Vss) shifts the voltage Vc of the signal line 5 through the capacitor C by (Vdd-Vss) to a low voltage level, and becomes Vc-2Vss + Vf- (Vdd-Vss) . Vf is the forward voltage of the diode 4, and since (Vdd-Vss) is generally larger than Vf, it can be seen that Vc is less than Vss, and the low voltage level is lower than the ground voltage Vss. At this time, the signal line 5 is separated by the reverse bias of the diode 4 and the off operation of the pMOS transistor 2, so that the shifted low voltage level is maintained in the period T4.

When the analog switch SW is an nMOS transistor, the high voltage level in period T2 turns on the switch SW sufficiently, and the low voltage level in period T4 turns off the switch SW sufficiently. . Specifically, Vdd = 2 V, Vss-2 V, Vth-0.6 V, and Vf = 0.7 V, which is general, is adopted.

In the ON operation,

Vgs— Vth = Vc— (Vin + Vth) = 1.7 V

In off operation,

Vgs-Vth = Vc-(Vin + Vth) = — 1.9 V

It can be seen that the switch SW is sufficiently turned on and off, which greatly exceeds the conventional values of 0.4 V and —0.6 V.

On the other hand, when the analog switch SW is a pMOS transistor, The switch SW is sufficiently turned on by the low voltage level in the period T4, and is sufficiently turned off by the high voltage level in the period Τ2.

The actual value of the capacitance C is lower than the above calculated value due to the charging / discharging time constant, and the actual value of the voltage Vc when the voltage Vb changes is that the signal line 5 has a stray capacitance. Is smaller than the above calculated value because Therefore, the charging / discharging time constant is set to be shorter than the period T1 and the period T3 so that the charging voltage of the capacitor C is close to the calculated value. Set by a time constant. Further, the capacitance value of the capacitor C is set to be larger than that of the stray capacitance of the signal line 5 so that the voltage Vc becomes a voltage close to the calculated value, and the lower limit thereof is set.

Here, the integrated circuit structure of the MOS drive circuit of the present embodiment will be described. Figure 3 shows the integrated circuit structure of the circuit 7 of the same circuit. In the cross-sectional structure of the CMOS IC shown in the figure, the nMOS transistor 1 forming the inverter 7 is formed on the p-type substrate 21, and the pMOS transistor 2 is formed on the n-type transistor region formed in the p-type substrate 21. 22 formed. The diode 3 is formed by a p-type diode 23 and an n-type diffusion layer in the n-type region 22, and the diode 4 is formed by an independent n-type diffusion layer 24 and a p-type diffusion layer in the same region. You. As described above, the member 7 of this embodiment can be easily realized by a CMOS-IC.

The capacitance C is realized by the MOS capacitance formed by the gate and source terminals of the MOS transistor. In addition, a MOS capacitor formed by a gate terminal and a drain terminal can be used as the capacitor C, and a capacitor using a normal metal wiring layer, a polysilicon wiring layer, a diffusion layer, or the like as an electrode is used. be able to. All of these can be realized with ordinary CMOS ICs. Needless to say, Inveru 8 is realized with a normal CMOS-IC. Although the substrate 21 is of the p-type, the MOS-IC of the present invention can be similarly realized on an n-type substrate. Furthermore, the MOS drive circuit of the present invention can be similarly configured in other integrated circuit processes, for example, SOI (Silicon On Insulator) and the like.

As described above, according to this embodiment, the output level of the logic gate (inverter 7) can be significantly increased beyond the full scale of the power supply voltage (Vdd-Vss), and a low-voltage power supply is used. In such a case, the analog switch SW can be sufficiently driven. This makes it possible to integrate analog switches into integrated circuits (on-chip) even in miniaturized CMOS, thereby improving the functions of integrated circuits and preventing the number of components from increasing. The circuit can be reduced in price.

(Example 2)

FIG. 4 shows an embodiment in which the diode for preventing current backflow in the first current path is arranged on the source side of the pMOS transistor. In the figure, 2a is a pMOS transistor of the first current path, 3a is a diode arranged on the source side of the pMOS transistor 2a, 7a is transistors 1, 2a, diodes 3a, 4 and This is an invar formed by the input / output terminals 5 and 20. Other structures are the same as those shown in FIG.

In this embodiment, as in the first embodiment, the level change of the output of the inverter 8 is transmitted to the signal line 5 via the capacitor C driven by the inverter 8, and the control voltage Vc having an increased amplitude is thereby transmitted. can get.

The operation of the MOS drive circuit according to the present embodiment is performed in the same manner as in the first embodiment. That is, a voltage shift (Vdd-Vss) is performed through the capacitor C during the periods T2 and T4. At this time, since the signal line 5 is separated by the reverse bias of the diode 3a and the diode 4, the high voltage level and the low The level is held in period T2 and period T4, respectively. The high voltage level in the period T2 and the low voltage level in the period T4 can sufficiently turn on and off the switch SW regardless of whether the analog switch SW is an nMOS transistor or a 'pMOS transistor.

Next, Fig. 5 shows the integrated circuit structure of Invar 7a. In the cross-sectional structure of the CMOS IC shown in FIG. 1, the nMOS transistor 1 is formed on the p-type substrate 21 and the pMOS transistor 2a is formed on the n-type well region 22 formed in the p-type substrate 21. You. The diode 3a is realized by a p-type diffusion layer in the same well as the independent n-type transistor 25. Further, the diode 4 is realized by an independent n-type well 24 and a p-type diffusion layer in the same well. As described above, the inverter 7a of this embodiment can be easily realized by a normal low-cost CMOS IC.

(Example 3)

FIG. 6 shows an embodiment in which the diode for preventing current backflow in the second current path of the first embodiment is omitted. In the figure, reference numeral 9 denotes an inverter in which the second current path is formed only by the nMOS transistor 1, SWn denotes an analog switch by the nMOS transistor, and Vcn denotes a gate of the switch SWn. This is the control voltage applied to the terminal. Other structures are the same as those shown in FIG.

In this embodiment, as in the first embodiment, the capacity driven by the inverter 8

The level change of the output of the inverter 8 is transmitted to the signal line 5 via C, but the low voltage level of the control voltage is suppressed to almost Vss as described later. FIG. 7 shows the operation timing of the MOS drive circuit of this embodiment. The operation in the period T1 to the period T3 is the same as that in the first embodiment, and the control voltage Vcn reaches a high voltage level Vcn = Vdd-Vf + (Vdd-Vss)> Vdd exceeding the power supply voltage. This control voltage Vcn is the reverse bias of diode 3 and nMOS. Separated by the off operation of the transistor 1 and held in the period T2. In the subsequent period T3, the voltage Vcn drops and reaches almost Vss.

The operation in the period T4 is different from that in the first embodiment. When the input signal Ψ is set to the high level during the period T4, the inverter 8 reverses, and the output voltage Vb changes to the low level. This voltage change (Vdd—Vss) acts to shift the voltage Vcn of the signal line 5 by (Vdd—Vss) through the capacitor C, but the signal line 5 is connected to Vss by the ON operation of the nMOS transistor 1. Therefore, the shifted low voltage level approaches Vss in the period T4.

The high voltage level of the control voltage Vcn in the period T2 can sufficiently turn on the switch SWn. On the other hand, the low voltage level in the period T4 is almost Vss, but under the same voltage condition as in the first embodiment, Vgs—Vth = —0.6 V, and the switch SWn is turned off. You.

Next, FIG. 8 shows the integrated circuit structure of Invar 9 of this embodiment. In the cross-sectional structure of the CMOS IC shown in the figure, the nMOS transistor 1 is formed on the p-type substrate 21 and the pMOS transistor 2 is formed on the n-type well region 22 in the p-type substrate 21. The diode 3 is realized by an independent n-type well 25 and a P-type diffusion layer in the same well. In this way, the inverter 9 of the present embodiment can be easily realized by a normal low-cost CMOS IC.

In the present embodiment, the second current path is formed only by the nMOS transistor 1. However, the present invention is not limited to this. It is possible to arrange a diode for preventing a current backflow between the nMOS transistor 1 and the ground. is there. The voltage level of the control signal Vc in the period T 4 can be equal to or lower than the ground voltage Vss as in the first embodiment.

(Example 4)

FIG. 9 shows an embodiment in which the diode of the fourth embodiment is replaced with an nMOS transistor. In the figure, 10 indicates a connection between the gate terminal and the drain terminal. An nMOS transistor 9 a having its connection point connected to the drain terminal of the pMOS transistor 2 and its source terminal connected to the signal line 5 is an inverter having such a transistor 10. Other structures are the same as those shown in FIG.

The nMOS transistor 10 that connects the gate terminal and the drain terminal behaves like a pn junction diode, flows current from the drain terminal to the source terminal, and transfers the charging current from the power supply voltage Vdd to the signal line 5. Form a current path. However, no current flows in the opposite direction.

The operation of the MOS drive circuit of this embodiment is performed in the same manner as the operation timing of the third embodiment shown in FIG. During the period T2, the signal line 5 is separated by the nMOS transistor 10, and the control voltage Vcn is maintained at the high voltage level during the same period. As a result, the analog switch SWn formed by the nMOS transistor can perform a sufficient ON operation. The low voltage level in the period T4 becomes almost Vss, and the switch SWn is turned off.

In the present embodiment, the second current path is formed only by the nMOS transistor 1.However, the present invention is not limited to this. The second current path can be formed by connecting the nMOS transistor 1 and a diode for preventing current backflow in series. is there. The voltage level of the control signal Vc in the period T4 can be equal to or lower than the ground voltage Vss, as in the first embodiment.

(Example 5)

FIG. 10 shows an embodiment in which the gate terminal of the diode operation nMOS transistor of the fourth embodiment is separated. In the figure, reference numeral 11 denotes an nMOS transistor in which a gate terminal is separated and an input signal X is applied to the terminal, and reference numeral 9b denotes an inverter having such a transistor 11. Other structures are the same as those shown in FIG. When the input signal X is at a high level, the channel of the nMOS transistor 11 is turned on, and X is at a low level. In the case of, the channel is turned off.

The operation of the MOS drive circuit of this embodiment is performed according to the operation timing of the third embodiment shown in FIG. However, the input signal X goes high during the period T1 and turns on the nMOS transistor 11. In a period T2 to a period T4, the input signal X is at a low level, and the nMOS transistor 11 is turned off.

When the input signal Φ goes low during the period T1, the pMOS transistor 2 turns on and the nMOS transistor 1 turns off. At this time, since the channel of the nMOS transistor 11 is on, a charging current flows from the power supply Vdd toward the signal line 5, and the voltage Vcn rises. In the period T1, the input signal の of the inverter 8 is at a high level, and the output voltage Vb is at a low level.

Next, when the input signal Ψ is changed to a low level in the period T2, the inverter 8 is inverted and the output voltage Vb is changed to a high level. This voltage change is transmitted to the signal line 5 through the capacitor C, and Vcn shifts to a high voltage level (Vcn> Vdd). At this time, the channel of the nMOS transistor 11 is turned off, and the signal line 5 is thereby separated, so that the shifted high voltage level is maintained in the period T2. Thus, the analog switch SWn by the nMOS transistor can perform a sufficient ON operation.

The operations in the period T3 and the period T4 are the same as those in the fourth embodiment. In the period T4, the control voltage Vcn asymptotic to Vss is obtained, and the OFF state of the switch SWn is ensured.

In the present embodiment, the second current path is formed only by the nMOS transistor 1.However, the present invention is not limited to this. The second current path can be formed by connecting the nMOS transistor 1 and a diode for preventing current backflow in series. is there. Period T The voltage level of the control signal Vc in (4) can be equal to or lower than the ground voltage Vss, as in the first embodiment.

(Example 6)

FIG. 11 shows an embodiment in which the pMOS transistor 2 of the embodiment 3 is replaced with a member. In the figure, reference numeral 13 denotes an inverter which receives an input signal Φ and the output side of which is connected to a diode 3, and numeral 12 denotes an inverter having such an inverter 13. Other structures are the same as those shown in FIG.

When the input signal Φ is low, the output of the inverter 13 goes to the power supply voltage Vdd, and the signal line 5 is charged to a high level. When the input signal Φ is at a high level, the output of the inverter 13 goes to the ground voltage Vss and the diode 3 turns off, and the signal line 5 goes to the low level Vss through the nMOS transistor 1 which turns on. Discharged.

The operation of the MOS drive circuit of this embodiment is performed in the same manner as the operation timing of the third embodiment shown in FIG. Since the signal line 5 is separated by the diode 3, the high voltage level Vcn is held during the period T2. This allows the nMOS analog switch SWn to perform a sufficient ON operation. The low voltage level in the period T4 becomes almost Vss, and the switch SWn is turned off.

(Example 7)

FIG. 12 shows an embodiment in which the diode for preventing current backflow in the first current path of the embodiment 1 is omitted. In the figure, reference numeral 14 denotes an inverter in which the first current path is formed only by the pMOS transistor 2, SWp denotes an analog switch formed by the pMOS transistor, and Vcp denotes a control applied to the gate terminal of the switch SWp. Voltage. The input signal 6 obtained by inverting the input signal Φ of the first embodiment is applied to the input terminal 6 of the inverter 14. In the evening 8, an input signal ¥ that is the inverse of the input signal of the first embodiment is applied. Other structures are the same as those shown in FIG.

The receiver outputs an inverted signal of the input signal ¥ to the signal line 5. The output signal of the inverter 8 that changes according to the input signal ¥ is transmitted to the signal line 5 via the capacitor C. The control signal Vcp of the signal line 5 is applied to the gate terminal of the analog switch SWp to control the on / off operation of the switch SWp.

FIG. 13 shows the operation timing of the MOS drive circuit of this embodiment. period

When the input signal Φ goes high at T1, the NMOS transistor 14 turns on the nMOS transistor 1 and turns off the pMOS transistor 2. As a result, a discharge current flows from the signal line 5 toward the ground voltage Vss, and the voltage Vcp decreases to reach Vcp = Vss + Vf. Vf is the forward voltage of diode 4. In the period T1, the input signal ¥ of the receiver 8 is at the low level, and the output voltage is at the high level Vdd.

Next, when the input signal ¥ is changed to the high level in the period T2, the inverter 8 is inverted, and the output voltage changes to the low level Vss. This voltage change (Vdd-Vss) is transmitted to the signal line 5 through the capacitor C, and Vcp is shifted by (Vdd-Vss) to reach a low voltage level of Vcp-Vss + Vf- (Vdd-Vss). Under the same voltage conditions as in the first embodiment, Vcp becomes Vss, and Vcp becomes a low voltage level equal to or lower than the ground voltage Vss. At this time, since the signal line 5 is separated by the reverse bias of the diode 4 and the off operation of the pMOS transistor 2, the low voltage level is maintained in the period T2.

When the input signal ¥ changes to low level during the period T3, the pMOS transistor 2 turns on and the nMOS transistor 1 turns off. As a result, a charging current flows from the power supply Vdd toward the signal line 5, and the voltage Vcp rises to almost Vdd. Next, when the input signal ¥ is changed to the low level in the period T4 and the inverter 8 is inverted, the output voltage ^ changes to the high level Vdd. This voltage change (Vdd-Vss) acts to shift the voltage Vcp of the signal line 5 through the capacitor C by (Vdd-Vss), but the signal line 5 is turned on by the pMOS transistor 2 turning on Vdd. , The shifted high voltage level asymptotically approaches Vdd in period T4.

The low voltage level of the control voltage Vcp in the period T2 can sufficiently turn on the switch SWp. Specifically, Vdd = 2 V, Vss = 0 V, Vth = -0.6 V, and a general = 0.7 V is adopted as Vf.

Vgs-Vth = Vc-(Vin + Vth) = — 1.7 V

Thus, the conventional value of 0.4 V can be greatly reduced.

On the other hand, the high voltage level in the period T4 is almost Vdd, but under the same voltage conditions as in the first embodiment, Vgs−Vth = 0.6 V, and the switch SWp is off.

Next, FIG. 14 shows an integrated circuit structure of Invar 14 of this embodiment. In the cross-sectional structure of the CMOS IC shown in FIG. 1, the nMOS transistor 1 is formed on the p-type substrate 21, and the pMOS transistor 2 is formed on the n-type well region 22 in the p-type substrate 21. The diode 4 is realized by an independent n-type well 24 and a p-type diffusion layer in the same well. As described above, the inverter 14 of this embodiment can be easily realized by a normal low-cost CMOS IC. In this embodiment, the diode 4 is used as an element for preventing a current backflow. However, the present invention is not limited to this, and it is possible to use a pMOS transistor in which the gate terminal is connected to the drain terminal. Alternatively, it can be a pMOS transistor that provides an input signal X to the gate terminal. Further, in any of these cases, it is possible to dispose a diode for preventing current backflow between the pMOS transistor 2 and the power supply. (Example 8)

An embodiment in which the analog switch is configured by connecting an nMOS transistor and a pMOS transistor in parallel, the nMOS transistor is driven by the MOS drive circuit of the third embodiment, and the pMOS transistor is driven by the MOS drive circuit of the second embodiment. See Figure 15. In the figure, reference numeral 15 denotes an analog switch in which a switch SWn formed by an nMOS transistor and a switch SWp formed by a pMOS transistor are connected in parallel. The MOS drive circuit for the switch SWn is the same as that shown in FIG. 6, and the MOS drive circuit for the switch SWp is the same as that shown in FIG.

The switch SWn is controlled by the control voltage Vcn of the signal line 5a, and the switch SWp is controlled by the control voltage Vcp of the signal line 5b. A high voltage level is obtained for the voltage Vcn by the capacitor 8 and the capacitor C and the capacitor 9 and a low voltage level Vcp is obtained by another capacitor 8 and the capacitor C and the capacitor 14. . Here, the input signal Φ and the input signal ¥ and the input signal ¥ are switched on in the period T2 according to the operation timings of FIGS. 7 and 13, respectively, to turn on the switch SWn and the switch SWp. At T4, switch SWn and switch SWp are turned off. The control voltage exceeding the full scale of the power supply voltage in the period T2, that is, the high voltage level of the voltage Vcn and the low voltage level of the voltage Vcp can sufficiently turn on the analog switch 15.

As described above, the inverters 8, 9, 14 and the capacitance C of this embodiment can be easily realized by a normal low-cost CMOS IC, and the present invention integrates an analog switch. A low power supply voltage operation MOS integrated circuit can be realized.

(Example 9)

FIG. 16 shows an embodiment in which the driving target is an output driver circuit. In the figure Here, 16 is an output driver circuit using an nMOS transistor, and L is an external load driven by the output driver circuit 16. The output driver circuit 16 is driven by the MOS drive circuit according to the third embodiment shown in FIG.

That is, the signal line 5 is connected to the gate terminal of the nMOS transistor constituting the output driver 16, and the on / off operation of the output driver 16 is controlled by the control voltage Vcn. As in the case of the third embodiment, a high voltage level (Vcn> Vdd) can be obtained for the voltage Vcn by the inverter 9, the inverter 8 and the capacitance C. Due to this high voltage level, the output dryno 16 performs a sufficient ON operation, and can supply a sufficient drive current to the external load L even in the presence of the parasitic impedance r.

As described above, according to the present invention, it is possible to realize a drive circuit that outputs a control voltage having a signal level exceeding the full scale of the power supply voltage, so that the analog switch and the like can be sufficiently turned on and off. It is possible to provide a MOS integrated circuit by a miniaturization process of a low-voltage power supply operation that can be performed. Analog circuits that are difficult to operate at low voltage, especially MOS analog switches, can be miniaturized. CMOS-ICs can be turned on, thereby improving the functions of integrated circuits and reducing the number of components. The increase can be prevented. As a result, various devices using integrated circuits can be reduced in price.

Industrial applicability

As described above, the present invention is useful for a MOS integrated circuit in which adoption of a low power supply voltage by a miniaturization process is inevitable, and is particularly suitable for application to a CMOS integrated circuit in which analog circuits are mixed.

Claims

The scope of the claims

1.The gate terminal of a p-channel MOS (Metal Oxide Semiconductor) transistor and the gate terminal of an n-channel MOS transistor are connected to each other as an input terminal, and the signal input to the input terminal is inverted. Output MOS integrated circuit,

At least one of the current path formed by the p-channel MOS transistor formed between the first power supply and the output terminal and the current path formed by the n-channel MOS transistor formed between the second power supply and the output terminal A semiconductor device for preventing current backflow is added to one of the current paths, and circuit means for shifting the voltage by capacitive coupling is provided at an output terminal.

MOS integrated circuit.

2. The voltage shift circuit means includes a capacitor having one terminal connected to the output terminal and a logic gate connected to the other terminal of the capacitor, and the logic gate is connected to the input terminal. 2. The MOS integrated circuit according to claim 1, wherein the MOS integrated circuit inverts the input signal and outputs a signal delayed by a predetermined time.

3. The capacitance value of the capacitance element is smaller than the capacitance value at which the time constant of the current path exhibits the predetermined delay time, and larger than the capacitance value of the stray capacitance added to the output terminal. 3. The MOS integrated circuit according to claim 2, wherein:

4.A pn junction diode is connected between the p-channel MOS transistor and the output terminal as a semiconductor element for preventing current backflow, and another pn junction diode is connected between the n-channel MOS transistor and the output terminal. 3. The MOS integrated circuit according to claim 2, wherein the MOS integrated circuit is connected as another semiconductor element for preventing current backflow.

5. The MOS integrated circuit according to claim 2, wherein a pn junction diode is connected between the p-channel MOS transistor and the output terminal as a semiconductor element for preventing current backflow.

6. The MOS integrated circuit according to claim 2, wherein a pn junction diode is connected between the n-channel MOS transistor and the output terminal as a semiconductor element for preventing current backflow.

7. Another n-channel MOS transistor having a gate terminal connected to the drain terminal between the p-channel MOS transistor and the output terminal is connected as a semiconductor element for preventing current reverse flow. 3. The MOS integrated circuit according to item 2.

8. Another p-channel MOS transistor having a gate terminal connected to the drain terminal between the n-channel MOS transistor and the output terminal is connected as a semiconductor element for preventing current reverse flow. 3. The MOS integrated circuit according to item 2.

9.Another n-channel MOS transistor is connected between the p-channel MOS transistor and the output terminal as a semiconductor element for preventing current backflow, and the gate terminal of the other n-channel MOS transistor is connected to another input. 3. The MOS integrated circuit according to claim 2, wherein the MOS integrated circuit is used as a terminal.

10 .Another p-channel MOS transistor is connected between the n-channel MOS transistor and the output terminal as a semiconductor element for preventing current backflow, and the gate terminal of the other p-channel MOS transistor is connected. 3. The MOS integrated circuit according to claim 2, wherein the MOS integrated circuit is used as another input terminal.

11.1 Another pn junction diode was connected between the n-channel MOS transistor and the second power supply as another semiconductor element for preventing current backflow. 6. The MOS integrated circuit according to claim 5, wherein:

8. The MOS integrated circuit according to claim 7, wherein a pn junction diode is connected as another semiconductor device for preventing current backflow between the 1 2n-channel MOS transistor and the second power supply. .

13. The MOS integrated circuit according to claim 9, wherein a pn junction diode is connected between the n-channel MOS transistor and the second power supply as another semiconductor element for preventing current backflow. .

14. The MOS according to claim 6, characterized in that another pn junction diode is connected between the p-channel MOS transistor and the first power supply as another semiconductor element for preventing current backflow. Integrated circuit.

15. The MOS integrated circuit according to claim 8, wherein a pn junction diode is connected between the p-channel type MOS transistor and the first power supply as another semiconductor element for preventing current backflow. .

16. The MOS integrated circuit according to claim 10, wherein a pn junction diode is connected between the p-channel type MOS transistor and the first power supply as another semiconductor element for preventing current backflow. circuit.