WO2000008759A1 - Circuit integre a mos - Google Patents

Circuit integre a mos Download PDF

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Publication number
WO2000008759A1
WO2000008759A1 PCT/JP1998/003440 JP9803440W WO0008759A1 WO 2000008759 A1 WO2000008759 A1 WO 2000008759A1 JP 9803440 W JP9803440 W JP 9803440W WO 0008759 A1 WO0008759 A1 WO 0008759A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
voltage
mos transistor
terminal
channel mos
Prior art date
Application number
PCT/JP1998/003440
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English (en)
Japanese (ja)
Inventor
Toshiro Tsukada
Keiko Fukuda
Masanori Otsuka
Akihiro Kitagawa
Shuzo Ichiki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/003440 priority Critical patent/WO2000008759A1/fr
Publication of WO2000008759A1 publication Critical patent/WO2000008759A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors

Definitions

  • the present invention relates to a MOS (Metal Oxide Semiconductor) integrated circuit, and more particularly to a MOS integrated circuit provided with a drive circuit for driving an analog circuit.
  • MOS Metal Oxide Semiconductor
  • CMOS' ICs Complementary MOS 'ICs
  • CMOS' ICs Complementary MOS 'ICs
  • their logic gates invar, NAND, NOR, etc.
  • the degree of integration of MOS and IC is increasing year by year, and accordingly, the dimensions of transistors are becoming finer, and the CMOS process is becoming finer. Since miniaturization of transistor dimensions inevitably causes a decrease in the withstand voltage of the transistor, the power supply voltage Vdd of the CMOS IC has been steadily decreasing, and it has been 5 V for a long time to 3 V. Recently it has become lower. Therefore, the output amplitude of the logic gate is also reduced.
  • a circuit for increasing the output amplitude of the logic gate As a circuit for increasing the output amplitude of the logic gate, a circuit for shifting the signal level (for example, refer to Japanese Patent Application Laid-Open No. Hei 7-'2162) or a voltage conversion is performed to increase the amplitude. There has been proposed a circuit (for example, see Japanese Patent Application Laid-Open No. 8-87008).
  • the former circuit uses a step-down circuit and a step-up circuit to expand the voltage range supplied to the MOS gate of the analog switch.
  • the step-down circuit and the step-up circuit are configured using switches that cannot be realized with ordinary CMOS ICs.
  • the latter circuit uses a voltage conversion circuit that uses a separate power supply, in addition to a circuit that combines bipolar and CMOS circuits.
  • the conventional drive circuit requires a separate circuit and a separate power supply, which further increases the cost, and is difficult to apply to recent miniaturized and low-cost CMOS ICs. . Disclosure of the invention
  • Fig. 17 shows a general example in which a CMOS circuit mounted on a CMOS IC is used as a drive circuit for driving a MOS analog switch.
  • the CMOS inverter includes an n-channel MOS transistor (hereinafter simply referred to as “nMOS transistor”) 1 and a p-channel MOS transistor (hereinafter simply referred to as “pMOS transistor”) 2.
  • nMOS transistor n-channel MOS transistor
  • pMOS transistor p-channel MOS transistor
  • the control signal Vc is output by inverting the input signal ⁇ at the input terminal 6.
  • the voltage Vc is supplied to the MOS gate terminal of the analog switch SW as a drive voltage, and controls on / off of the analog switch SW.
  • the switch SW When the analog switch SW is turned on, the switch SW A voltage Vout equal to the voltage Vin input to one terminal is output to the other terminal.
  • Vgs is Vc—Vin, so
  • Vgs-Vth Vc-Vin-Vth »0 (ON operation)
  • Vgs-Vth Vc-Vin-Vth «0 (OFF operation)
  • the analog switch SW requires that the control voltage Vc be sufficiently higher than Vin + Vth to be turned on, and that Vc be sufficiently lower than Vin + Vth to be turned off.
  • Vdd the power supply voltage
  • Vc the high level of the effective gate voltage (Vgs-Vth) of the analog switch SW decreases, and the ON operation becomes insufficient.
  • CMOS complementary metal-oxide-semiconductor
  • Vdd 2 V
  • Vss 0 V
  • Vth 0. 6 V
  • Vgs-Vth the high level of the effective gate voltage
  • Vgs-Vth the low level of the effective gate voltage
  • An object of the present invention is to solve the above-mentioned problems of the prior art, and to output a control signal having a high signal level exceeding a difference voltage (full scale) between a power supply voltage and a ground voltage, thereby achieving low power supply voltage.
  • An object of the present invention is to provide a MOS integrated circuit capable of driving an analog circuit such as an analog switch.
  • the object of the present invention is to reduce a current path formed by a pMOS transistor formed between a first power supply and an output terminal and a current path formed by an nMOS transistor formed between a second power supply (for example, ground) and an output terminal.
  • Both can be achieved by a drive circuit in which a semiconductor element for preventing current backflow is added to one of the current paths and a circuit means for shifting the voltage by capacitive coupling is provided at the output terminal.
  • the voltage shift circuit means includes a capacitance element having one terminal connected to the output terminal and a logical gate connected to the other terminal of the capacitance element. The logic gate delays an input signal to the input terminal of the drive circuit for a predetermined time, and outputs an inverted signal as a voltage change.
  • This predetermined delay time is a precharge period in which the capacitance element is charged by the current from the current path.
  • the logic gate outputs the voltage change at the same time as the end of the precharge period. The voltage change is transmitted to the output terminal via the capacitor.
  • the voltage at the output terminal either exceeds the first power supply voltage or falls below the second power supply voltage, and becomes a control voltage having a signal level exceeding the full scale.
  • the added semiconductor element prevents a current from flowing back to the pMOS transistor or the nMOS transistor by such a control voltage.
  • the above-described analog switch driving method a signal level exceeding the full scale can be secured, and a sufficient effective gate voltage for switching the analog switch can be obtained. Further, the above-described voltage shift circuit means by capacitive coupling and the semiconductor element for preventing current backflow can be formed by a miniaturized CMOS process, and can be easily incorporated into a MOS integrated circuit operating at a low power supply voltage.
  • FIG. 1 is a circuit diagram for explaining a first embodiment of a MOS integrated circuit according to the present invention
  • FIG. 2 is an operation timing for explaining the first embodiment of the present invention
  • FIG. 3 is a cross-sectional view of the integrated circuit structure for explaining the first embodiment of the present invention
  • FIG. 4 is a sectional view of the integrated circuit structure of the present invention.
  • FIG. 5 is a circuit diagram for explaining a second embodiment of the present invention
  • FIG. 5 is a cross-sectional view of an integrated circuit structure for explaining a second embodiment of the present invention
  • FIG. FIG. 7 is a circuit diagram for explaining a third embodiment
  • FIG. 7 is a waveform diagram showing operation timing for explaining a third embodiment of the present invention
  • FIG. 8 is a cross-sectional view of an integrated circuit structure for explaining a third embodiment of the present invention.
  • FIG. 9 is a circuit diagram for explaining a fourth embodiment of the present invention.
  • FIG. 10 is a circuit diagram for explaining a fifth embodiment of the present invention, and
  • FIG. 11 is a circuit diagram for explaining a sixth embodiment of the present invention.
  • FIG. 12 is a circuit diagram for explaining a seventh embodiment of the present invention.
  • FIG. 3 is a waveform diagram showing the operation timing for explaining the seventh embodiment of the present invention.
  • FIG. 14 is an integrated circuit structure for explaining the seventh embodiment of the present invention.
  • FIG. 15 is a circuit diagram for explaining an eighth embodiment of the present invention, and
  • FIG. 16 is a circuit diagram for explaining a ninth embodiment of the present invention.
  • FIG. 17 is a circuit diagram, and FIG. 17 is a circuit diagram for explaining a conventional MOS integrated circuit.
  • 3 is a pn junction diode (hereinafter simply referred to as a “diode”) connected between the drain terminal of pMOS transistor 2 and output terminal 20, and 4 is the drain terminal and output terminal 2 of nMOS transistor 1.
  • a diode connected between 0, 5 is a signal line connecting the output terminal 20 to the gate terminal of the analog switch SW
  • C is a capacitive element having one terminal connected to the output terminal 20, that is, the signal line 5.
  • Numeral 8 denotes an inverter connected to the other terminal of the capacitor C (hereinafter referred to as “capacitor C”).
  • Inverter 7 is formed by transistors 1 and 2, diodes 3 and 4, and input / output terminals 5 and 20.
  • the inverter 8 and the capacitor C to which the input signal ⁇ ⁇ is applied form voltage shift circuit means by the above-described capacitive coupling, and the MOS drive for driving the analog switch SW by the circuit means and the inverter 7.
  • a circuit is formed.
  • the capacitance C is driven by the inverter 8 and when the output signal of the inverter 8 changes according to the input signal ⁇ , the level change is transmitted to the signal line 5 via the capacitor C. Thereby, the amplitude of the control voltage Vc is enlarged.
  • On / off of the analog switch SW is controlled by the control voltage Vc, and when the analog switch SW is turned on, a voltage Vout having a value equal to the input voltage Vin is output to the other terminal of the switch SW.
  • Either nMOS or pMOS transistors can be used for the switch SW.
  • a first current path is formed between the power supply of voltage Vdd (first power supply) and the output terminal 5 by the transistor 2, and a transistor is connected between the output terminal 5 and the ground of the voltage Vss (second power supply). 1 forms a second current path. Then, the stray capacitance (not shown) of the signal line 5 and the capacitance C are charged by the current of the first current path, and the stray capacitance of the signal line 5 and the capacitance to the capacitance C are charged by the current of the second current path. Discharge is performed to invert the input signal ⁇ Output signal is obtained.
  • Vf is the forward voltage of the diode 4, and since (Vdd-Vss) is generally larger than Vf, it can be seen that Vc is less than Vss, and the low voltage level is lower than the ground voltage Vss.
  • the signal line 5 is separated by the reverse bias of the diode 4 and the off operation of the pMOS transistor 2, so that the shifted low voltage level is maintained in the period T4.
  • the analog switch SW is an nMOS transistor
  • the high voltage level in period T2 turns on the switch SW sufficiently
  • the low voltage level in period T4 turns off the switch SW sufficiently.
  • Vdd 2 V
  • Vss-2 V V
  • Vth-0.6 V V
  • Vf 0.7 V, which is general, is adopted.
  • the analog switch SW is a pMOS transistor
  • the switch SW is sufficiently turned on by the low voltage level in the period T4, and is sufficiently turned off by the high voltage level in the period ⁇ 2.
  • the actual value of the capacitance C is lower than the above calculated value due to the charging / discharging time constant, and the actual value of the voltage Vc when the voltage Vb changes is that the signal line 5 has a stray capacitance. Is smaller than the above calculated value because Therefore, the charging / discharging time constant is set to be shorter than the period T1 and the period T3 so that the charging voltage of the capacitor C is close to the calculated value. Set by a time constant. Further, the capacitance value of the capacitor C is set to be larger than that of the stray capacitance of the signal line 5 so that the voltage Vc becomes a voltage close to the calculated value, and the lower limit thereof is set.
  • Figure 3 shows the integrated circuit structure of the circuit 7 of the same circuit.
  • the nMOS transistor 1 forming the inverter 7 is formed on the p-type substrate 21, and the pMOS transistor 2 is formed on the n-type transistor region formed in the p-type substrate 21. 22 formed.
  • the diode 3 is formed by a p-type diode 23 and an n-type diffusion layer in the n-type region 22, and the diode 4 is formed by an independent n-type diffusion layer 24 and a p-type diffusion layer in the same region.
  • the member 7 of this embodiment can be easily realized by a CMOS-IC.
  • the capacitance C is realized by the MOS capacitance formed by the gate and source terminals of the MOS transistor.
  • a MOS capacitor formed by a gate terminal and a drain terminal can be used as the capacitor C, and a capacitor using a normal metal wiring layer, a polysilicon wiring layer, a diffusion layer, or the like as an electrode is used. be able to. All of these can be realized with ordinary CMOS ICs. Needless to say, Inveru 8 is realized with a normal CMOS-IC.
  • the substrate 21 is of the p-type
  • the MOS-IC of the present invention can be similarly realized on an n-type substrate.
  • the MOS drive circuit of the present invention can be similarly configured in other integrated circuit processes, for example, SOI (Silicon On Insulator) and the like.
  • the output level of the logic gate can be significantly increased beyond the full scale of the power supply voltage (Vdd-Vss), and a low-voltage power supply is used.
  • the analog switch SW can be sufficiently driven. This makes it possible to integrate analog switches into integrated circuits (on-chip) even in miniaturized CMOS, thereby improving the functions of integrated circuits and preventing the number of components from increasing. The circuit can be reduced in price.
  • FIG. 4 shows an embodiment in which the diode for preventing current backflow in the first current path is arranged on the source side of the pMOS transistor.
  • 2a is a pMOS transistor of the first current path
  • 3a is a diode arranged on the source side of the pMOS transistor 2a
  • 7a is transistors 1, 2a, diodes 3a, 4 and This is an invar formed by the input / output terminals 5 and 20.
  • Other structures are the same as those shown in FIG.
  • the level change of the output of the inverter 8 is transmitted to the signal line 5 via the capacitor C driven by the inverter 8, and the control voltage Vc having an increased amplitude is thereby transmitted. can get.
  • the operation of the MOS drive circuit according to the present embodiment is performed in the same manner as in the first embodiment. That is, a voltage shift (Vdd-Vss) is performed through the capacitor C during the periods T2 and T4. At this time, since the signal line 5 is separated by the reverse bias of the diode 3a and the diode 4, the high voltage level and the low The level is held in period T2 and period T4, respectively.
  • the high voltage level in the period T2 and the low voltage level in the period T4 can sufficiently turn on and off the switch SW regardless of whether the analog switch SW is an nMOS transistor or a 'pMOS transistor.
  • Fig. 5 shows the integrated circuit structure of Invar 7a.
  • the nMOS transistor 1 is formed on the p-type substrate 21 and the pMOS transistor 2a is formed on the n-type well region 22 formed in the p-type substrate 21.
  • the diode 3a is realized by a p-type diffusion layer in the same well as the independent n-type transistor 25.
  • the diode 4 is realized by an independent n-type well 24 and a p-type diffusion layer in the same well.
  • the inverter 7a of this embodiment can be easily realized by a normal low-cost CMOS IC.
  • FIG. 6 shows an embodiment in which the diode for preventing current backflow in the second current path of the first embodiment is omitted.
  • reference numeral 9 denotes an inverter in which the second current path is formed only by the nMOS transistor 1
  • SWn denotes an analog switch by the nMOS transistor
  • Vcn denotes a gate of the switch SWn. This is the control voltage applied to the terminal.
  • Other structures are the same as those shown in FIG.
  • FIG. 7 shows the operation timing of the MOS drive circuit of this embodiment.
  • This control voltage Vcn is the reverse bias of diode 3 and nMOS. Separated by the off operation of the transistor 1 and held in the period T2. In the subsequent period T3, the voltage Vcn drops and reaches almost Vss.
  • the operation in the period T4 is different from that in the first embodiment.
  • the inverter 8 reverses, and the output voltage Vb changes to the low level.
  • This voltage change (Vdd—Vss) acts to shift the voltage Vcn of the signal line 5 by (Vdd—Vss) through the capacitor C, but the signal line 5 is connected to Vss by the ON operation of the nMOS transistor 1. Therefore, the shifted low voltage level approaches Vss in the period T4.
  • the high voltage level of the control voltage Vcn in the period T2 can sufficiently turn on the switch SWn.
  • FIG. 8 shows the integrated circuit structure of Invar 9 of this embodiment.
  • the nMOS transistor 1 is formed on the p-type substrate 21 and the pMOS transistor 2 is formed on the n-type well region 22 in the p-type substrate 21.
  • the diode 3 is realized by an independent n-type well 25 and a P-type diffusion layer in the same well. In this way, the inverter 9 of the present embodiment can be easily realized by a normal low-cost CMOS IC.
  • the second current path is formed only by the nMOS transistor 1.
  • the present invention is not limited to this. It is possible to arrange a diode for preventing a current backflow between the nMOS transistor 1 and the ground. is there.
  • the voltage level of the control signal Vc in the period T 4 can be equal to or lower than the ground voltage Vss as in the first embodiment.
  • FIG. 9 shows an embodiment in which the diode of the fourth embodiment is replaced with an nMOS transistor.
  • 10 indicates a connection between the gate terminal and the drain terminal.
  • An nMOS transistor 9 a having its connection point connected to the drain terminal of the pMOS transistor 2 and its source terminal connected to the signal line 5 is an inverter having such a transistor 10.
  • Other structures are the same as those shown in FIG.
  • the nMOS transistor 10 that connects the gate terminal and the drain terminal behaves like a pn junction diode, flows current from the drain terminal to the source terminal, and transfers the charging current from the power supply voltage Vdd to the signal line 5. Form a current path. However, no current flows in the opposite direction.
  • the operation of the MOS drive circuit of this embodiment is performed in the same manner as the operation timing of the third embodiment shown in FIG.
  • the signal line 5 is separated by the nMOS transistor 10, and the control voltage Vcn is maintained at the high voltage level during the same period.
  • the analog switch SWn formed by the nMOS transistor can perform a sufficient ON operation.
  • the low voltage level in the period T4 becomes almost Vss, and the switch SWn is turned off.
  • the second current path is formed only by the nMOS transistor 1.However, the present invention is not limited to this.
  • the second current path can be formed by connecting the nMOS transistor 1 and a diode for preventing current backflow in series. is there.
  • the voltage level of the control signal Vc in the period T4 can be equal to or lower than the ground voltage Vss, as in the first embodiment.
  • FIG. 10 shows an embodiment in which the gate terminal of the diode operation nMOS transistor of the fourth embodiment is separated.
  • reference numeral 11 denotes an nMOS transistor in which a gate terminal is separated and an input signal X is applied to the terminal
  • reference numeral 9b denotes an inverter having such a transistor 11.
  • Other structures are the same as those shown in FIG.
  • the input signal X is at a high level
  • the channel of the nMOS transistor 11 is turned on, and X is at a low level. In the case of, the channel is turned off.
  • the operation of the MOS drive circuit of this embodiment is performed according to the operation timing of the third embodiment shown in FIG. However, the input signal X goes high during the period T1 and turns on the nMOS transistor 11. In a period T2 to a period T4, the input signal X is at a low level, and the nMOS transistor 11 is turned off.
  • the pMOS transistor 2 turns on and the nMOS transistor 1 turns off.
  • the channel of the nMOS transistor 11 is on, a charging current flows from the power supply Vdd toward the signal line 5, and the voltage Vcn rises.
  • the input signal ⁇ of the inverter 8 is at a high level, and the output voltage Vb is at a low level.
  • the inverter 8 is inverted and the output voltage Vb is changed to a high level.
  • This voltage change is transmitted to the signal line 5 through the capacitor C, and Vcn shifts to a high voltage level (Vcn> Vdd).
  • Vcn a high voltage level
  • the channel of the nMOS transistor 11 is turned off, and the signal line 5 is thereby separated, so that the shifted high voltage level is maintained in the period T2.
  • the analog switch SWn by the nMOS transistor can perform a sufficient ON operation.
  • the second current path is formed only by the nMOS transistor 1.However, the present invention is not limited to this.
  • the second current path can be formed by connecting the nMOS transistor 1 and a diode for preventing current backflow in series. is there.
  • Period T The voltage level of the control signal Vc in (4) can be equal to or lower than the ground voltage Vss, as in the first embodiment.
  • FIG. 11 shows an embodiment in which the pMOS transistor 2 of the embodiment 3 is replaced with a member.
  • reference numeral 13 denotes an inverter which receives an input signal ⁇ and the output side of which is connected to a diode 3
  • numeral 12 denotes an inverter having such an inverter 13.
  • Other structures are the same as those shown in FIG.
  • the operation of the MOS drive circuit of this embodiment is performed in the same manner as the operation timing of the third embodiment shown in FIG. Since the signal line 5 is separated by the diode 3, the high voltage level Vcn is held during the period T2. This allows the nMOS analog switch SWn to perform a sufficient ON operation. The low voltage level in the period T4 becomes almost Vss, and the switch SWn is turned off.
  • FIG. 12 shows an embodiment in which the diode for preventing current backflow in the first current path of the embodiment 1 is omitted.
  • reference numeral 14 denotes an inverter in which the first current path is formed only by the pMOS transistor 2
  • SWp denotes an analog switch formed by the pMOS transistor
  • Vcp denotes a control applied to the gate terminal of the switch SWp. Voltage.
  • the input signal 6 obtained by inverting the input signal ⁇ of the first embodiment is applied to the input terminal 6 of the inverter 14.
  • an input signal ⁇ that is the inverse of the input signal of the first embodiment is applied.
  • Other structures are the same as those shown in FIG.
  • the receiver outputs an inverted signal of the input signal ⁇ to the signal line 5.
  • the output signal of the inverter 8 that changes according to the input signal ⁇ is transmitted to the signal line 5 via the capacitor C.
  • the control signal Vcp of the signal line 5 is applied to the gate terminal of the analog switch SWp to control the on / off operation of the switch SWp.
  • FIG. 13 shows the operation timing of the MOS drive circuit of this embodiment. period
  • Vdd-Vss This voltage change (Vdd-Vss) is transmitted to the signal line 5 through the capacitor C, and Vcp is shifted by (Vdd-Vss) to reach a low voltage level of Vcp-Vss + Vf- (Vdd-Vss).
  • Vcp becomes Vss
  • Vcp becomes a low voltage level equal to or lower than the ground voltage Vss.
  • Vdd 2 V
  • Vss 0 V
  • Vth -0.6 V
  • FIG. 14 shows an integrated circuit structure of Invar 14 of this embodiment.
  • the nMOS transistor 1 is formed on the p-type substrate 21, and the pMOS transistor 2 is formed on the n-type well region 22 in the p-type substrate 21.
  • the diode 4 is realized by an independent n-type well 24 and a p-type diffusion layer in the same well.
  • the inverter 14 of this embodiment can be easily realized by a normal low-cost CMOS IC.
  • the diode 4 is used as an element for preventing a current backflow.
  • the present invention is not limited to this, and it is possible to use a pMOS transistor in which the gate terminal is connected to the drain terminal. Alternatively, it can be a pMOS transistor that provides an input signal X to the gate terminal. Further, in any of these cases, it is possible to dispose a diode for preventing current backflow between the pMOS transistor 2 and the power supply. (Example 8)
  • FIG. 15 An embodiment in which the analog switch is configured by connecting an nMOS transistor and a pMOS transistor in parallel, the nMOS transistor is driven by the MOS drive circuit of the third embodiment, and the pMOS transistor is driven by the MOS drive circuit of the second embodiment.
  • reference numeral 15 denotes an analog switch in which a switch SWn formed by an nMOS transistor and a switch SWp formed by a pMOS transistor are connected in parallel.
  • the MOS drive circuit for the switch SWn is the same as that shown in FIG. 6, and the MOS drive circuit for the switch SWp is the same as that shown in FIG.
  • the switch SWn is controlled by the control voltage Vcn of the signal line 5a
  • the switch SWp is controlled by the control voltage Vcp of the signal line 5b.
  • a high voltage level is obtained for the voltage Vcn by the capacitor 8 and the capacitor C and the capacitor 9
  • a low voltage level Vcp is obtained by another capacitor 8 and the capacitor C and the capacitor 14.
  • the input signal ⁇ and the input signal ⁇ and the input signal ⁇ are switched on in the period T2 according to the operation timings of FIGS. 7 and 13, respectively, to turn on the switch SWn and the switch SWp.
  • switch SWn and switch SWp are turned off.
  • the control voltage exceeding the full scale of the power supply voltage in the period T2 that is, the high voltage level of the voltage Vcn and the low voltage level of the voltage Vcp can sufficiently turn on the analog switch 15.
  • the inverters 8, 9, 14 and the capacitance C of this embodiment can be easily realized by a normal low-cost CMOS IC, and the present invention integrates an analog switch.
  • a low power supply voltage operation MOS integrated circuit can be realized.
  • FIG. 16 shows an embodiment in which the driving target is an output driver circuit.
  • 16 is an output driver circuit using an nMOS transistor, and L is an external load driven by the output driver circuit 16.
  • the output driver circuit 16 is driven by the MOS drive circuit according to the third embodiment shown in FIG.
  • the signal line 5 is connected to the gate terminal of the nMOS transistor constituting the output driver 16, and the on / off operation of the output driver 16 is controlled by the control voltage Vcn.
  • a high voltage level (Vcn> Vdd) can be obtained for the voltage Vcn by the inverter 9, the inverter 8 and the capacitance C. Due to this high voltage level, the output dryno 16 performs a sufficient ON operation, and can supply a sufficient drive current to the external load L even in the presence of the parasitic impedance r.
  • CMOS-ICs can be turned on, thereby improving the functions of integrated circuits and reducing the number of components. The increase can be prevented. As a result, various devices using integrated circuits can be reduced in price.
  • the present invention is useful for a MOS integrated circuit in which adoption of a low power supply voltage by a miniaturization process is inevitable, and is particularly suitable for application to a CMOS integrated circuit in which analog circuits are mixed.

Abstract

L'invention concerne un circuit intégré à MOS destiné à piloter un circuit analogique tel qu'un commutateur analogique avec une faible puissance d'alimentation en fournissant une tension de commande à niveau de signal élevé, qui dépasse la tension différentielle (en vraie grandeur) entre la tension d'alimentation et la tension de mise à la masse. Un élément semi-conducteur destiné à bloquer le flux de courant inverse est installé dans n'importe quelle voie de courant comprenant un transistor pMOS formé entre une première alimentation et la borne de sortie ou dans une voie de courant comprenant un transistor nMOS formé entre une deuxième alimentation et la borne de sortie. Un circuit destiné à décaler la tension par couplage capacitif est installé à la borne de sortie.
PCT/JP1998/003440 1998-08-03 1998-08-03 Circuit integre a mos WO2000008759A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015089100A (ja) * 2013-09-26 2015-05-07 株式会社デンソー 負荷駆動装置
CN104753511A (zh) * 2015-04-20 2015-07-01 中国电子科技集团公司第二十四研究所 一种低压低功耗线型模拟开关
WO2022202609A1 (fr) * 2021-03-25 2022-09-29 国立研究開発法人科学技術振興機構 Circuit de commutation et circuit d'alimentation électrique

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JPS63114316A (ja) * 1986-06-26 1988-05-19 Nec Corp ブ−トストラツプ回路
JPH0392832U (fr) * 1990-01-12 1991-09-20
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JPH04262615A (ja) * 1990-08-31 1992-09-18 Siemens Ag 容量性負荷の駆動回路および方法
JPH06204756A (ja) * 1992-12-28 1994-07-22 Sony Corp バツフア回路

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Publication number Priority date Publication date Assignee Title
JPS61255588A (ja) * 1985-05-07 1986-11-13 Seiko Epson Corp 半導体記憶装置
JPS62154663A (ja) * 1985-12-26 1987-07-09 Nec Corp 電圧発生回路
JPS63114316A (ja) * 1986-06-26 1988-05-19 Nec Corp ブ−トストラツプ回路
JPH0392832U (fr) * 1990-01-12 1991-09-20
JPH04108215A (ja) * 1990-08-28 1992-04-09 Nec Kansai Ltd 昇圧回路
JPH04262615A (ja) * 1990-08-31 1992-09-18 Siemens Ag 容量性負荷の駆動回路および方法
JPH06204756A (ja) * 1992-12-28 1994-07-22 Sony Corp バツフア回路

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Publication number Priority date Publication date Assignee Title
JP2015089100A (ja) * 2013-09-26 2015-05-07 株式会社デンソー 負荷駆動装置
CN104753511A (zh) * 2015-04-20 2015-07-01 中国电子科技集团公司第二十四研究所 一种低压低功耗线型模拟开关
CN104753511B (zh) * 2015-04-20 2017-11-07 中国电子科技集团公司第二十四研究所 一种低压低功耗线型模拟开关
WO2022202609A1 (fr) * 2021-03-25 2022-09-29 国立研究開発法人科学技術振興機構 Circuit de commutation et circuit d'alimentation électrique

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