JP3120303B2 - Power MOS control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS control circuit and, more particularly, to a technique effective for controlling switching characteristics of a power MOS transistor, and for driving an inductive load such as a motor. The present invention relates to a technology that is effective for use in a power circuit.

[0002]

2. Description of the Related Art In recent years, a power MOS transistor has been widely used as a power element for switchingly driving an inductive load such as a motor (for example, CQ Publishing Co., Ltd. Electronic Circuit Handbook 5 ”, pp. 234 to 236).

FIG. 8 shows an example of a power circuit using a power MOS transistor MA. The power circuit is composed of a power MOS transistor MA, a driving circuit 1 and a power MOS control 2.

The power MOS transistor MA has a power supply V
On / off control of energization to the load L is interposed in series between the DD and the load L.

The drive circuit 1 has a booster circuit (charge pump circuit) 11 and a logic circuit 12, etc., and the logic control signal Vin supplied from outside is set to high ("H") and low ("H").
L "), the power MOS transistor MA is turned on / off.

The power MOS control circuit 2 has the power M
A charge extraction MOS transistor M1 inserted in parallel with the gate of the OS transistor MA, the charge remaining in the gate of the power MOS transistor MA when the power MOS transistor MA is switched from on to off. Discharge the charge. Thereby, the gate control voltage V of the power MOS transistor MA is
By causing c to fall rapidly, the output current Iout to the load L can be quickly turned off (cut off).

[0007]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, in the above-described conventional power MOS control circuit, as shown in FIG. 9, the output current Iout is rapidly turned off (cut off) by the power MOS transistor.
(Electromagnetic interference) is likely to occur, and furthermore, if the load is inductive such as a motor, the circuit is likely to be broken by the kickback effect.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for preventing the occurrence of EMI due to a transient phenomenon and the destruction of a circuit due to kickback while properly controlling the power supply to a load by a power MOS transistor. .

The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a charge extracting MOS transistor is inserted in parallel with the gate of the power MOS transistor, and the power M is connected between the gate of the power MOS transistor and the charge extracting MOS transistor.
A discharge control MOS transistor whose conduction is automatically controlled by a voltage between the gate of the OS transistor and the output electrode is interposed in series.

[0013]

According to the above-described means, the gate residual charge after the power MOS transistor has been switched from on to off can be smoothly discharged under control such that the output current does not change abruptly.

This achieves the object of properly controlling the power supply to the load by the power MOS transistor and preventing the occurrence of EMI due to a transient phenomenon and the destruction of the circuit due to kickback.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a power M to which the technique of the present invention is applied.
1 shows an embodiment of an OS control circuit, in which MA is a power MOS transistor interposed between a power supply VDD and a load L to turn on / off the energization of the load L, and 1 is an externally applied logic control The power MOS transistor MA according to the high (“H”) and low (“L”) of the signal Vin.
Drive circuit for turning on / off the power MOS 2
This is a power MOS control circuit that controls switching characteristics when the transistor MA transitions from on to off.

The drive circuit 1 has a booster circuit (charge pump circuit) 11, a logic circuit 12, and the like, and drives the power MOS transistor MA on / off in accordance with the high and low levels of an externally applied logic control signal Vin. I do.

The power MOS control circuit 2 includes a power MOS control circuit.
A charge extraction MOS transistor M1 is inserted in parallel with the gate of the transistor MA, and the power MOS
The power MOS transistor M is provided between the gate of the transistor MA and the charge extraction MOS transistor M1.
A voltage Vgs between the gate and the source (output electrode) of A (=
(Vc−Vout), and a discharge control MOS transistor M2, whose conduction is automatically controlled by Vc−Vout), is arranged in series.

In this case, the power MOS transistor MA
An n-channel MOS transistor M1 is used for the charge extraction MOS transistor M1, and a p-channel MOS transistor M2 is used for the discharge control MOS transistor M2.

The conduction of the discharge control p-channel MOS transistor M2 is automatically controlled by the voltage Vgs between the gate and the source of the power MOS transistor MA.
Specifically, the gate of the power MOS transistor MA
Automatic control is performed so that the conduction amount is small while the source-to-source voltage Vgs is small, and the conduction amount is increased as the gate-source voltage Vgs increases.

Next, the operation will be described.

In FIG. 1, when the logic control signal Vin from the outside is high, the driving circuit 1
The gate voltage Vc of the OS transistor MA is driven to a high level, whereby the power MOS transistor MA is turned on and the output current Iout flows to the load L.

Next, when the external logic control signal Vin switches from high to low, the power M
The gate drive of the OS transistor MA is stopped, and the charge extraction MOS transistor M1 is turned on by the low level of the logic signal Vin, and the power M
The charge remaining in the gate of the OS transistor MA is extracted.

At this time, the gate charge is extracted by the charge extraction MOS transistor M1 by the discharge control MOS transistor M1.
Since the transistor M2 is interposed in series, the operation is performed as follows.

That is, an external logic control signal Vin
Immediately after switching from high to low, the power MOS
Since the source of the transistor MA is at substantially the same potential as the power supply VDD and the gate-source voltage Vgs is small, the conduction amount of the discharge control MOS transistor M2 is small. As a result, the charge extraction MOS transistor M1 has the power M
The gate charge of the OS transistor MA is relatively slowly extracted.

When the gate potential (Vc) of the power MOS transistor MA decreases due to the extraction of the gate charge by the charge extraction MOS transistor M1, the output current Iout flowing from the power MOS transistor MA to the load L is reduced, and the power MO
Source potential of S transistor MA, that is, output voltage Vo
ut decreases.

When the gate-source voltage Vgs increases due to the decrease in the output voltage Vout,
The amount of conduction of the discharge control MOS transistor M2 is increased, and the extraction of the gate charge of the power MOS transistor MA by the charge extraction MOS transistor M1 is accelerated.

If the gate potential Vc is excessively reduced by pulling out the gate electrode, the gate-source voltage Vgs is reduced, the amount of conduction is reduced, and at the same time, the output current Iout is reduced.
Also decreases. As a result, the output voltage Vout decreases,
The gate-source voltage Vgs increases again, the conduction amount increases, and the output current Iout also increases. As the amount of conduction increases, the gate potential Vc decreases again. This repetition can be performed, that is, the output voltage Vout can be reduced (turned off) while monitoring the output voltage Vout.

As described above, as shown in FIG. 2, the output current Iout when the power MOS transistor MA is switched from ON to OFF has a change trajectory that minimizes a transient phenomenon such as EMI and kickback. It is cut off while passing through. The change state of the output current Iout at this time can be arbitrarily set according to the gate width / channel length of the discharge control MOS transistor M2.

Thus, the power MOS transistor M
The generation of EMI due to a transient phenomenon and the destruction of the circuit due to kickback can be prevented while appropriately controlling the energization of the load L by the switching operation of A. Although the circuit of FIG. 1 is a so-called high-side driver, the same effect can be obtained by using a low-side driver in which the position of the load L is inserted between the power supply VDD and the power transistor MA as shown in FIG.

FIGS. 4, 5 and 6 each show a further preferred embodiment of the present invention.

In the embodiment shown in FIG.
S transistor M2 and charge extraction MOS transistor M
1, the upper limit of the gate charge discharge rate of the power MOS transistor MA is controlled by inserting a resistor R1 between the power MOS transistors MA.

In the embodiment shown in FIG. 5, a Zener diode Z1 is connected from the gate to the source of the power MOS transistor MA so as to clamp a certain voltage or more. In this case, when Vin is Low, that is, when M1 is ON, the gate potential Vc and the output voltage Vout settle down in a state where they are lowered to the ground potential. At this time, if the output voltage Vout temporarily becomes the forward voltage VF of the Zener diode, In this case, the current flows into the circuit from the output terminal through the zener diode Z1, and this current can be cut off by the discharge control MOS transistor M2. Note that the positive kickback voltage can be clamped to the power supply VDD by the diode D1 incorporated in the power MOS transistor MA.

In the embodiment shown in FIG. 6, a MOS transistor M3 is connected between the gate and the source of the power MOS transistor MA. Thus, even if there is a difference between the threshold voltage Vth of the power MOS transistor MA and the threshold voltage Vth of the MOS transistor M2, even if the MOS transistor M2 is cut off before the power MOS transistor MA, the power removal MOS transistor M3 completely removes the power MOS transistor M3. The gate charge of MA can be extracted. Therefore, the power MOS transistor M
A can be completely turned off.

FIG. 7 shows an example of a motor drive circuit to which the technique of the present invention is applied.

The drive circuit shown in FIG. 3 comprises four power MOS transistors MA, MB, M connected in a bridge.
By selectively turning on C and MD two by two symmetrically, the motor as the load L can be driven forward and reverse.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

In the above description, the case where the invention made by the present inventor is applied to a motor control circuit using a power MOS, which is the field of application as the background, has been described. However, the present invention is not limited to this. It can also be applied to circuits that require large current switching.

[0040]

The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.

That is, it is possible to prevent the generation of EMI due to a transient phenomenon and the destruction of the circuit due to kickback while properly controlling the power supply to the load by the power MOS transistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a power MOS control circuit (high-side driver) to which the technology of the present invention is applied;

FIG. 2 is an output current control waveform diagram of a power MOS transistor controlled by a power control circuit of the present invention.

FIG. 3 is a circuit diagram used as a low-side driver circuit.

FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing an outline of a conventional power MOS control circuit.

FIG. 8 is an output current control waveform diagram of a power MOS transistor controlled by a conventional power control circuit.

FIG. 9 is an output waveform diagram of a power MOS transistor controlled by a conventional power control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Drive circuit 2 Power MOS control circuit MA Power MOS transistor M1 Charge extraction MOS transistor M2 Discharge control MOS transistor R1 Resistance Z1 Zener diode VDD Power supply L Load M3 Charge extraction MOS transistor

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shuichi Horiuchi 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Inside Hitachi Eastern Semiconductor Co., Ltd. (56) References JP-A-4-35217 (JP, A) JP-A-3 JP-A-166816 (JP, A) JP-A-1-261919 (JP, A) JP-A-4-157813 (JP, A) JP-A-4-241511 (JP, A) (58) Fields investigated (Int. Cl) . ⁷ , DB name) H03K 17/00-17/70

Claims (3)

(57) [Claims] 1. A charge extraction MOS transistor is inserted in parallel with a gate of a power MOS transistor, and between the gate of the power MOS transistor and the charge extraction MOS transistor, the gate of the power MOS transistor and the output electrode are connected. A power MOS control circuit characterized in that a discharge control MOS transistor whose conduction is automatically controlled by a voltage between them is interposed in series. 2. A charge extracting MOS transistor connected in series between a gate of a power MOS transistor having a drain connected to a first power supply voltage terminal and a source connected to an output electrode, and a second power supply voltage terminal. And a discharge control MOS transistor, wherein the power MOS transistor is controlled by a voltage obtained by boosting a logic control signal, and the charge extraction MOS transistor operates complementarily with the power MOS transistor based on the logic control signal. And the discharge control MOS
A power MOS transistor, wherein a gate of the transistor is connected to a source of the power MOS transistor so that conduction is automatically controlled by a gate-source voltage of the power MOS transistor.
Control circuit. 3. A clamp diode is connected between the gate of the power MOS transistor and the output electrode so as to be in the opposite direction from the gate of the power MOS transistor toward the output electrode. The power MOS control circuit according to claim 2, wherein