CN102545560B - Power switch driver, IC chip, and DC-DC converter - Google Patents
Power switch driver, IC chip, and DC-DC converter Download PDFInfo
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- CN102545560B CN102545560B CN201110422515.7A CN201110422515A CN102545560B CN 102545560 B CN102545560 B CN 102545560B CN 201110422515 A CN201110422515 A CN 201110422515A CN 102545560 B CN102545560 B CN 102545560B
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Abstract
The invention discloses a power switch driver, an IC chip and a DC-DC converter, for lowering ground bounce of a switch power source and for lowering impedance from the gate of a power switch to the power source or the ground when the power switch is switched off while ensuring a low opening speed of the power switch so as to prevent instant-on of the power switch through coupling of a parasitic capacitor. The power switch driver provided by the invention comprises an N-channel metal oxide semiconductor field effect transistor NMOS for controlling a P-type power switch, and a P-channel metal oxide semiconductor field effect transistor PMOS for controlling an N-type power switch, and also includes a first resistor connected with source of the NMOS, and a second resistor connected with source of the PMOS.
Description
Technical field
The present invention relates to switch power technology field, relate in particular to a kind of power switch driver, IC chip and DC-to-DC converter.
Background technology
The demand of current portable equipment and mobile communication system increases day by day, and these systems all be unable to do without electric power system, and DC-to-DC converter (DC/DC Converter) is widely used with its high efficiency.Shown in Fig. 1, be exactly common synchronous buck type DC-to-DC converter (Buck, Step-Down DC/DC Converter) application circuit, comprise DC-to-DC converter integrated circuit (IC) chip, inductance L 0, output capacitance C0 and load RLoad.Wherein, IC chip comprises controller (CONTROLLER), power switch driver (DRIVER), power switch M1 and M2.
Controller adopts certain control mode (PWM or PFM) to produce the pulse control signal of certain duty ratio (duty cycle), by driver, remove driving power switch M1 and M2, making the common node SW generation peak value of M1 and M2 is the pulse signal that power supply arrives ground, through the filtering of inductance L 0 and capacitor C 0, at load RLoad, holds and produces stable output voltage.
But, have in actual applications some non-ideal factors to consider.For example, routing stray inductance and resistance after IC chip package, Rpara1 as shown in Figure 2 and Lpara1, Rpara2 and Lpara2.In general encapsulation, dead resistance is tens milliohm magnitudes, and stray inductance is a few nanohenry magnitudes.Due to power switch M1 and M2 alternation switch, in the stray inductance of routing, have mutation current and produce larger change in voltage, that is to say, the extraneous desirable earth potential of the earth potential of IC chip internal and chip has voltage difference, and the earth potential of chip when power switch turn-on and turn-off in high frequency " spring " state, Here it is, and ground plays phenomenon (ground bounce).When adopt thinner packaging and routing for cost consideration, or load is when heavier, and the amplitude that the earth potential of IC chip is beated will increase, and at this moment will affect the control circuit of IC chip, thereby affects the normal work of IC chip.
At present, as shown in Figure 3, in prior art, conventional method is to serial resistance (R1 and R2) between power switch M1 and the grid of M2 at driver, adopt larger R1 and R2 (the general several kilohms of orders of magnitude), by slow down the opening speed of power switch M1 and M2 reduce bullet, wherein, power switch M1 is P-channel metal-oxide-semiconductor field effect (MOS) transistor (P-channel Metal Oxide Semiconductor, PMOS); Power switch M2 is N NMOS N-channel MOS N field effect (MOS) transistor (N-channel Metal-Oxide-Semiconductor, NMOS).
But when the diameter of packaging and routing is less, the stray inductance of routing is larger, or load current is when larger, and the ground bullet of prior art is still very large.Reason is drawn high by controlling PMOS M11 and the resistance R 1 of this power switch M1 at the grid of power switch M1; But after M2 conducting, SW node is dragged down fast, because the resistance of R1 is larger, the grid that is M1 is larger to the impedance of power supply Vdd, parasitic capacitance Cgd by M1 is (because the area of power switch M1 is larger, equivalence Cgd also larger) coupling after, output (SW) also drags down the grid of M1, M1 is also at transient switching; M1 and M2 at the same time the moment of conducting will on packaging and routing inductance L para2, produce larger electric current, this large electric current can suddenly change and make GND end " spring " amplitude very high, it is many that the waveform GND amplitude of beating as shown in Figure 4 reaches 1V.
In sum, the ground bullet phenomenon of power switch of the prior art is comparatively serious.
Summary of the invention
The embodiment of the present invention provides a kind of power switch driver, IC chip and DC-to-DC converter, in order to the bullet that reduces Switching Power Supply, when keeping the slower opening speed of power switch, while reducing switch-off power switch, the grid of power switch is to the impedance on power supply or ground, makes to close the power switch of having no progeny and can not pass through the coupling of parasitic capacitance and transient switching.
A kind of power switch driver that the embodiment of the present invention provides, the n channel metal oxide semiconductor field effect transistor M12 that comprises co-controlling P type power switch together with P-channel metal-oxide-semiconductor field effect transistor M 11, the P-channel metal-oxide-semiconductor field effect transistor M 21 of co-controlling N-type power switch together with n channel metal oxide semiconductor field effect transistor M22, described P type power switch and described N-type power switch are for being connected in series in successively between power Vcc and ground to form the power switch of synchronous buck type DC-to-DC converter, wherein, the first source electrode of described P-channel metal-oxide-semiconductor field effect transistor M 11 connects the anodal Vdd of power switch driver, the first drain electrode of described P-channel metal-oxide-semiconductor field effect transistor M 11 connects the second drain electrode of described n channel metal oxide semiconductor field effect transistor M12, the first grid of described P-channel metal-oxide-semiconductor field effect transistor M 11 connects the second grid of described n channel metal oxide semiconductor field effect transistor M12, the 3rd drain electrode of described n channel metal oxide semiconductor field effect transistor M22 connects the 4th drain electrode of described P-channel metal-oxide-semiconductor field effect transistor M 21, the 3rd source electrode of described n channel metal oxide semiconductor field effect transistor M22 connects ground, the 3rd grid of described n channel metal oxide semiconductor field effect transistor M22 connects the 4th grid of described P-channel metal-oxide-semiconductor field effect transistor M 21, described the 4th grid of the described second grid of described n channel metal oxide semiconductor field effect transistor M12 and described P-channel metal-oxide-semiconductor field effect transistor M 21 is connected to the not overlapping clock of two-phase by inverter respectively, this power switch driver also comprises: the first resistance, be connected between the second source electrode and ground of described n channel metal oxide semiconductor field effect transistor M12, and the second resistance, is connected between the 4th source electrode and the described anodal Vdd of described power switch driver of described P-channel metal-oxide-semiconductor field effect transistor M 21, the 3rd resistance, is connected between described the second drain electrode and the grid of described P type power switch of described n channel metal oxide semiconductor field effect transistor M12, the 4th resistance, is connected between described the 4th drain electrode and the grid of described N-type power switch of described P-channel metal-oxide-semiconductor field effect transistor M 21.
A kind of integrated circuit (IC) chip that the embodiment of the present invention provides comprises described power switch driver.
A kind of DC-to-DC converter that the embodiment of the present invention provides comprises described power switch driver.The embodiment of the present invention is by described power switch driver, IC chip and DC-to-DC converter, can reduce Switching Power Supply ground bullet, when keeping the slower opening speed of power switch, while reducing switch-off power switch, the grid of power switch is to the impedance on power supply or ground, makes to close the power switch of having no progeny and can not pass through the coupling of parasitic capacitance and transient switching.
Accompanying drawing explanation
Fig. 1 is synchronous buck type DC-to-DC converter of the prior art (Buck, Step-Down DC/DC Converter) application circuit schematic diagram;
Fig. 2 is routing stray inductance after the IC chip package of DC-to-DC converter of the prior art and the schematic diagram of resistance;
Fig. 3 is that DC-to-DC converter of the prior art arrives the schematic diagram of serial resistance (R1 and R2) between power switch M1 and the grid of M2 at driver;
Fig. 4 is the ground bullet schematic diagram of the GND end of DC-to-DC converter shown in Fig. 3;
The electrical block diagram of the DC-to-DC converter that Fig. 5 provides for the embodiment of the present invention;
The ground bullet schematic diagram of the GND end of the DC-to-DC converter that Fig. 6 provides for the embodiment of the present invention.
Embodiment
The embodiment of the present invention provides a kind of power switch driver, IC chip and DC-to-DC converter, in order to the bullet (ground bounce) that reduces Switching Power Supply, when keeping the slower opening speed of power switch, while reducing switch-off power switch, the grid of power switch is to the impedance on power supply or ground, makes to close the power switch of having no progeny and can not pass through the coupling of parasitic capacitance and transient switching.
Referring to Fig. 5, a kind of power switch driver (DRIVER) that the embodiment of the present invention provides, comprise for controlling NMOS M12 and the PMOS M11 of P type power switch M1, and for controlling PMOS M21 and the NMOS M22 of N-type power switch M2, this power switch driver also comprises:
The first resistance R 12, is connected between the source electrode and ground (GND) of described NMOS M12; And,
The second resistance R 21, is connected between the source electrode of described PMOS M21 and the positive pole of described power switch driver (Vdd).
Preferably, this power switch driver also comprises: be connected in the 3rd resistance R 11 between the leakage level of described NMOS M12 and the grid of described P type power switch M1; And,
Be connected in the 4th resistance R 22 between the leakage level of described PMOS M21 and the grid of described N-type power switch M2.
Preferably,
The resistance of described the first resistance R 12, equates with the resistance of described the 3rd resistance R 11;
The resistance of described the second resistance R 21, equates with the resistance of described the 4th resistance R 22.
Preferably, the resistance span of described the first resistance is:
100 ohm～400 ohm.
Preferably, the resistance span of described the second resistance is:
100 ohm～400 ohm.
Preferably, the resistance span of described the 3rd resistance is:
100 ohm～400 ohm.
Preferably, the resistance span of described the 4th resistance is:
100 ohm～400 ohm.
As shown in Figure 5, the power switch driver that the embodiment of the present invention provides, also comprises the not overlapping clock of two-phase (BBM) and two inverters (INV).The not overlapping clock of two-phase receives the duty cycle signals of controller (CONTROLLER), produces respectively the driving signal of P type power switch M1 and N-type power switch M2.The not overlapping clock of two-phase guarantees not conducting simultaneously of P type power switch M1 and N-type power switch M2.Inverter receives the not driving signal of overlapping clock generating of two-phase, and it is anti-phase to reach P type power switch M1 and the required level of N-type power switch M2.
As shown in Figure 5, a kind of integrated circuit (IC) chip that the embodiment of the present invention provides, comprises controller (CONTROLLER), above-mentioned power switch driver (DRIVER), power switch M1 and M2.Controller (CONTROLLER) produces applicable duty cycle signals, and power switch driver (DRIVER) receives this duty cycle signals, finally produces the driving signal of power ratio control switch M1 and M2.
As shown in Figure 5, a kind of DC-to-DC converter that the embodiment of the present invention provides, comprise above-mentioned DC-to-DC converter integrated circuit (IC) chip (comprising above-mentioned power switch driver), routing stray inductance and resistance (being the Rpara1 shown in Fig. 5 and Lpara1, Rpara2 and Lpara2).Routing stray inductance Lpara1 and resistance R para1 represent that Vdd in chip is to the ghost effect of the VCC pin after having encapsulated.In like manner, routing stray inductance Lpara2 and resistance R para2 represent that GND in chip is to the ghost effect of 0 level pin after having encapsulated.
As shown in Figure 5, in the embodiment of the present invention, R1 of the prior art shown in Fig. 3 is divided into two resistance R 11 and R12, and preferably, R11=R12=0.5*R1, is also divided into two resistance R 21 and R22 by R2, and preferably, R21=R22=0.5*R2.Wherein R11 still remains on the position of original R1, and R22 remains on the position of original R2, R12 is placed between the source electrode and GND of prime driving tube M12 of power switch M2, R21 is placed between the source electrode and power supply Vdd of prime driving tube M21 of power switch M2.When power switch NMOS M2 opens, after M21 conducting still by R21 and R22 to the gate charges of M2, that is to say, the opening speed of power switch NMOS M2 is the same with prior art slower.But now M11 conducting, the grid of the power switch PMOS M1 turn-offing is reduced to R11 (R11=0.5*R1) to the impedance of power supply by prior art R1, thereby the grid of power switch PMOS M1 with regard to being not easy to be output the decline of end SW the step-down that is coupled, therefore power switch PMOS M1 can keep turn-offing when power switch NMOS M2 opens, on the inductance L para2 of packaging and routing, just do not have larger mutation current, the ground bullet of GND end also can obviously reduce, and during power switch PMOS M1 conducting, ground bullet improves effect and also can in like manner derive.
As shown in Figure 6, the simulation waveform schematic diagram that the power switch driver providing according to the embodiment of the present invention exactly obtains, as seen from the figure, and GND waveform, namely the ground bullet of the GND of IC chip end only has 500mV, compared with the 1V of prior art, has clear improvement more.
In sum, the embodiment of the present invention is by described power switch driver, IC chip and DC-to-DC converter, can reduce Switching Power Supply ground bullet, when keeping the slower opening speed of power switch, while reducing switch-off power switch, the grid of power switch is to the impedance on power supply or ground, makes to close the power switch of having no progeny and can not pass through the coupling of parasitic capacitance and transient switching.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (8)
1. a power switch driver, the n channel metal oxide semiconductor field effect transistor M12 that comprises co-controlling P type power switch together with P-channel metal-oxide-semiconductor field effect transistor M 11, the P-channel metal-oxide-semiconductor field effect transistor M 21 of co-controlling N-type power switch together with n channel metal oxide semiconductor field effect transistor M22, described P type power switch and described N-type power switch are for being connected in series in successively between power Vcc and ground to form the power switch of synchronous buck type DC-to-DC converter, wherein, the first source electrode of described P-channel metal-oxide-semiconductor field effect transistor M 11 connects the anodal Vdd of power switch driver, the first drain electrode of described P-channel metal-oxide-semiconductor field effect transistor M 11 connects the second drain electrode of described n channel metal oxide semiconductor field effect transistor M12, the first grid of described P-channel metal-oxide-semiconductor field effect transistor M 11 connects the second grid of described n channel metal oxide semiconductor field effect transistor M12, the 3rd drain electrode of described n channel metal oxide semiconductor field effect transistor M22 connects the 4th drain electrode of described P-channel metal-oxide-semiconductor field effect transistor M 21, the 3rd source electrode of described n channel metal oxide semiconductor field effect transistor M22 connects ground, the 3rd grid of described n channel metal oxide semiconductor field effect transistor M22 connects the 4th grid of described P-channel metal-oxide-semiconductor field effect transistor M 21, described the 4th grid of the described second grid of described n channel metal oxide semiconductor field effect transistor M12 and described P-channel metal-oxide-semiconductor field effect transistor M 21 is connected to the not overlapping clock of two-phase by inverter respectively, it is characterized in that, this power switch driver also comprises:
The first resistance, is connected between the second source electrode and ground of described n channel metal oxide semiconductor field effect transistor M12; And,
The second resistance, is connected between the 4th source electrode and the described anodal Vdd of described power switch driver of described P-channel metal-oxide-semiconductor field effect transistor M 21;
The 3rd resistance, is connected between described the second drain electrode and the grid of described P type power switch of described n channel metal oxide semiconductor field effect transistor M12;
The 4th resistance, is connected between described the 4th drain electrode and the grid of described N-type power switch of described P-channel metal-oxide-semiconductor field effect transistor M 21.
2. power switch driver according to claim 1, is characterized in that,
The resistance of described the first resistance, equates with the resistance of described the 3rd resistance;
The resistance of described the second resistance, equates with the resistance of described the 4th resistance.
3. power switch driver according to claim 1, is characterized in that, the resistance span of described the first resistance is:
100 ohm～400 ohm.
4. power switch driver according to claim 1, is characterized in that, the resistance span of described the second resistance is:
100 ohm～400 ohm.
5. power switch driver according to claim 1, is characterized in that, the resistance span of described the 3rd resistance is 100 ohm～400 ohm.
6. power switch driver according to claim 1, is characterized in that, the resistance span of described the 4th resistance is:
100 ohm～400 ohm.
7. an integrated circuit (IC) chip, is characterized in that, this integrated circuit (IC) chip comprises the power switch driver described in the arbitrary claim of claim 1-6.
8. a DC-to-DC converter, is characterized in that, this transducer comprises the power switch driver described in the arbitrary claim of claim 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201110422515.7A CN102545560B (en) | 2011-12-15 | 2011-12-15 | Power switch driver, IC chip, and DC-DC converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110422515.7A CN102545560B (en) | 2011-12-15 | 2011-12-15 | Power switch driver, IC chip, and DC-DC converter |
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| CN102545560A CN102545560A (en) | 2012-07-04 |
| CN102545560B true CN102545560B (en) | 2014-09-03 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018021510A1 (en) * | 2016-07-29 | 2018-02-01 | パナソニックＩｐマネジメント株式会社 | Switching circuit device and electric power converter |
| CN106100297B (en) * | 2016-08-02 | 2018-08-31 | 北京交通大学 | Driving circuit based on silicon carbide MOSFET |
| JP6549200B2 (en) * | 2017-10-03 | 2019-07-24 | 三菱電機株式会社 | Power conversion circuit |
| CN107888152B (en) * | 2017-11-16 | 2022-04-22 | 海信视像科技股份有限公司 | Power amplifier applied to radio frequency transceiver, radio frequency transceiver and remote controller |
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| CN1961481A (en) * | 2004-06-02 | 2007-05-09 | 罗姆股份有限公司 | Coil load drive output circuit |
| CN101234561A (en) * | 2007-01-31 | 2008-08-06 | 三美电机株式会社 | Thermal head driving circuit |
| CN101677210A (en) * | 2008-06-18 | 2010-03-24 | 技领半导体(上海)有限公司 | Switch driver with low impedance initial drive and higher impedance final drive |
| CN202424492U (en) * | 2011-12-15 | 2012-09-05 | 无锡中星微电子有限公司 | Power switch driver, IC (integrated circuit) chip and DC-DC converter |
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2011
- 2011-12-15 CN CN201110422515.7A patent/CN102545560B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1961481A (en) * | 2004-06-02 | 2007-05-09 | 罗姆股份有限公司 | Coil load drive output circuit |
| CN101234561A (en) * | 2007-01-31 | 2008-08-06 | 三美电机株式会社 | Thermal head driving circuit |
| CN101677210A (en) * | 2008-06-18 | 2010-03-24 | 技领半导体(上海)有限公司 | Switch driver with low impedance initial drive and higher impedance final drive |
| CN202424492U (en) * | 2011-12-15 | 2012-09-05 | 无锡中星微电子有限公司 | Power switch driver, IC (integrated circuit) chip and DC-DC converter |
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Address after: 214028 Jiangsu New District of Wuxi, Taihu international science and Technology Park Jia Qing 530 building 10 layer Patentee after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: 214028 Jiangsu New District of Wuxi, Taihu international science and Technology Park Jia Qing 530 building 10 layer Patentee before: Wuxi Vimicro Co., Ltd. |