CN114552976A - full-GaN gate drive circuit with high conversion rate - Google Patents
full-GaN gate drive circuit with high conversion rate Download PDFInfo
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- CN114552976A CN114552976A CN202210203639.4A CN202210203639A CN114552976A CN 114552976 A CN114552976 A CN 114552976A CN 202210203639 A CN202210203639 A CN 202210203639A CN 114552976 A CN114552976 A CN 114552976A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention belongs to the technical field of power management, relates to the integrated circuit design technology, and particularly relates to a full GaN gate drive circuit with high conversion rate. The full-GaN gate drive circuit provided by the invention is added with a cross-coupled charge pump in the traditional full-GaN bootstrap inverter, realizes the rail-to-rail charging voltage of a bootstrap capacitor, and realizes higher matching between the output rising speed and the output falling speed while improving the output rising speed of the bootstrap inverter. A power supply lifting module is added in a traditional two-stage structure bootstrap phase inverter for driving a GaN power tube to lift the output voltage of a bias stage to be triple power supply voltage, the grid electrode rising speed of the GaN power tube is improved, the mismatching of the grid electrode rising slope and the grid electrode falling slope is reduced, and high-speed high-conversion-rate driving is realized. And the good matching between the opening delay and the closing delay of the GaN power tube is realized by adopting a four-stage bootstrap reverser cascade mode.
Description
Technical Field
The invention belongs to the technical field of power management, and particularly relates to a full GaN gate drive circuit with high conversion rate.
Background
GaN power devices have smaller on-resistance and parasitic capacitance than Si MOSFET power devices. Compared with a Si MOSFET power device, the GaN power device applied to the power conversion system can realize higher working frequency, higher power density and higher efficiency. Therefore, GaN power devices are considered to be an ideal choice for improving the performance of power conversion systems. When the enhancement mode GaN device is applied to a system, compared with a depletion mode GaN device, the enhancement mode GaN device is simpler in driving mode, extra negative voltage does not need to be generated, and less power consumption can be achieved while the driving complexity is reduced. Therefore, enhanced GaN devices are generally preferred in power conversion system applications.
At present, a GaN power device and a driving circuit thereof mostly adopt a discrete structure or an SIP structure, that is, a GaN gate driving circuit adopts Si-based integration, and is connected with the GaN power device on a PCB board or integrally packaged after being connected through gold wires. Parasitic inductance on PCB wiring or gold wires exists in the gate driving loop, and when the GaN device is rapidly switched on and off, the larger source parasitic series inductance in the gate driving loop can attenuate the switching speed of the GaN power device, so that the maximum working frequency of gate driving is limited; the grid electrode parasitic series inductance easily causes grid electrode overshoot of the GaN power device in the process of opening the GaN power device, causes grid electrode overvoltage of the device, and easily causes mistaken opening of the device after the GaN power device is turned off. Grid series resistance or programmable driving current is generally adopted in a grid driving circuit of a traditional discrete structure or a SIP structure to inhibit grid overshoot, but the grid overshoot is caused to increase the switching loss of a GaN power device and limit the maximum working frequency of grid driving. Therefore, the large parasitic inductance in the driving loop of the GaN gate driving circuit of the discrete structure or the SIP structure may limit the operating frequency of the driving circuit and cause a reliability problem of the GaN power device.
By adopting a silicon-based GaN process to integrate a GaN power device and a GaN gate driving single chip, parasitic inductance in a gate driving loop can be reduced to be close to zero, the compromise problem of the switching speed and the reliability of a grid electrode of a GaN power tube can be perfectly solved, and the switching operation with high frequency and high reliability is realized. At present, because the mobility of a p-type GaN transistor is far smaller than that of an n-type GaN transistor, an active device in a silicon-based GaN integrated circuit still only adopts the n-type GaN transistor. Fig. 1 shows a conventional two-stage bootstrap inverter in a full GaN gate driver ic, in which transistors are all n-type enhancement GaN transistors. The output rising rate is improved by cascading the bias stage and the driving stage. The static power consumption of the bias stage during output pull-down is reduced by the resistor R. However, the bootstrap capacitor CT0And CT1The voltage at both ends cannot be charged to the supply voltage VCC, there is a loss of threshold voltage, attenuating ET2And ET6The pull-up capability of. CT1By ET9To ET6When the gate-source capacitor is charged, ET9Working in the saturation region, the on-resistance is larger when ET6When the width and length of the input signal is large, the output rising rate is reduced, and the output rising rate and the output falling rate are seriously mismatched.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the problems in the traditional full GaN gate drive, a full GaN gate drive circuit with high conversion rate is designed, and the high-frequency characteristic of a GaN power tube can be fully exerted. The circuit structure comprises a four-stage bootstrap reverser, a cross coupling charge pump, a power supply lifting circuit, a bias stage and a driving stage.
The technical scheme of the invention is as follows: fig. 2 is a system configuration diagram of the all-GaN gate driving of the present invention. Four-stage bootstrap phase inverters are cascaded on the driving chain to realize the high-matching on-off delay. Between the first stage and the second stage bootstrap phase inverter, and between the third stage and the fourth stage bootstrap phase inverter, a cross-coupled charge pump is adopted to realize the rail-to-rail charging voltage of the bootstrap capacitor in the bootstrap phase inverter, thereby improving the output rising rate of the bootstrap phase inverter. The third stage bootstrap inverter adopts a mode of cascading an offset stage and a driving stage, wherein the offset stage provides an offset voltage which is twice of the power supply voltage for the driving stage, and the output rising rate of the bootstrap inverter is improved. On the basis of cascade connection of the bias stage and the driving stage in the fourth stage bootstrap inverter, the power supply boosting circuit is adopted to boost the power supply voltage of the bias stage to be twice of the gate driving power supply voltage, so that the bias voltage of triple power supply voltage is provided for the driving stage, and the output rising rate of the fourth stage bootstrap inverter is increased
Specifically, the first-stage bootstrap phase inverter comprises a first GaN tube, a second GaN tube, a third GaN tube, a fourth GaN tube, a fifth GaN tube, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor, and the second-stage bootstrap phase inverter comprises a sixth GaN tube, a seventh GaN tube, an eighth GaN tube, a ninth GaN tube, a tenth GaN tube, a fourth resistor and a second capacitor; the grid electrodes of the first GaN tube and the second GaN tube are connected with a PWM signal, the drain electrode of the first GaN tube is connected with the source electrode of the fourth GaN tube after passing through the first resistor, the source electrode of the first GaN tube is grounded, the drain electrode of the second GaN tube is connected with the source electrode of the third GaN tube, and the source electrode of the second GaN tube is grounded; the drain electrode of the third GaN tube is connected with a power supply, and the grid electrode of the third GaN tube is connected with the source electrode of the fourth GaN tube after passing through the first resistor; the drain electrode of the fourth GaN tube is connected with the power supply, and the grid electrode of the fourth GaN tube is connected with the source electrode of the ninth GaN tube; the source electrode of the fourth GaN tube is connected with one end of a first capacitor, the other end of the first capacitor is connected with the source electrode of the third GaN tube and one end of a second resistor, and the other end of the second resistor is connected with a power supply; the drain electrode of the fifth GaN tube is connected with the PWM signal through a third resistor, the grid electrode of the fifth GaN tube is connected with one end of the second resistor, and the source electrode of the fifth GaN tube is grounded; the drain electrode of the sixth GaN tube is connected with the source electrode of the tenth GaN tube through a fourth resistor, the grid electrode of the sixth GaN tube is connected with one end of the second resistor, and the source electrode of the sixth GaN tube is grounded; the drain electrode of the seventh GaN tube is connected with the source electrode of the eighth GaN tube, the grid electrode of the seventh GaN tube is connected with one end of the second resistor, and the source electrode of the seventh GaN tube is grounded; the drain electrode of the eighth GaN tube is connected with the power supply, and the grid electrode of the eighth GaN tube is connected with the source electrode of the tenth GaN tube after passing through the fourth resistor; the drain electrode of the ninth GaN tube is connected with a power supply, the grid electrode of the ninth GaN tube is connected with the source electrode of the fourth GaN tube, the source electrode of the ninth GaN tube is connected with the source electrode of the tenth GaN tube and one end of a second capacitor, and the other end of the second capacitor is connected with the source electrode of the eighth GaN tube; the drain electrode of the tenth GaN tube is connected with the power supply, and the grid electrode of the tenth GaN tube is interconnected with the drain electrode; the source electrode of the eighth GaN tube is the output end of the second-stage bootstrap phase inverter; the fourth GaN tube, the eighth GaN tube, the first capacitor and the second capacitor form a cross-coupled charge pump between the first-stage bootstrap inverter and the second-stage bootstrap inverter;
the third-stage bootstrap phase inverter comprises an eleventh GaN tube, a twelfth GaN tube, a thirteenth GaN tube, a fourteenth GaN tube, a fifteenth GaN tube, a sixteenth GaN tube, a seventeenth GaN tube, an eighteenth GaN tube, a nineteenth GaN tube, a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor and a fourth capacitor, wherein the eleventh GaN tube, the twelfth GaN tube, the thirteenth GaN tube, the fourteenth GaN tube, the third capacitor and the fifth resistor form a bias stage, and the fifteenth GaN tube, the sixteenth GaN tube, the seventeenth GaN tube, the eighteenth GaN tube, the nineteenth GaN tube, the sixth resistor, the seventh resistor and the fourth capacitor form a driving stage; the fourth-stage bootstrap phase inverter comprises a twentieth GaN tube, a twenty-first GaN tube, a twenty-twelfth GaN tube, a twenty-thirteenth GaN tube, a twenty-fourteenth GaN tube, a twenty-fifth GaN tube, a twenty-sixth GaN tube, a twenty-seventh GaN tube, a twenty-eighteenth GaN tube, a twenty-ninth GaN tube, a thirty-eighth GaN tube, a thirty-eleventh GaN tube, a thirty-twelfth GaN tube, a thirty-thirteenth GaN tube, a thirty-fourteenth GaN tube, a thirty-fifteenth GaN tube, a thirty-sixth GaN tube, a seventeenth GaN tube, a thirty-eighth GaN tube, a thirty-nineteenth GaN tube, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor, a twentieth GaN tube, a twenty-first GaN tube, a twenty-twelfth GaN tube, a twenty-thirteenth GaN tube, a twenty-fourteenth GaN tube, a twenty-fifth GaN tube, a twenty-sixth GaN tube, a twenty-seventh tube, a twenty-eighteenth GaN tube, a twenty-ninth tube, a twenty-eighth tube, a twenty-ninth GaN tube, a twenty-eighth tube, a fourth tube, a sixth tube, a fourth tube, a sixth tube, A fifth capacitor, a sixth capacitor and an eighth resistor form power supply promotion, a thirty-fifth GaN tube, a thirty-first GaN tube, a thirty-second GaN tube, a thirty-third GaN tube, a thirty-fourth GaN tube, a ninth resistor and a seventh capacitor form a bias stage, and a thirty-fifth GaN tube, a thirty-sixth GaN tube, a thirty-seventeenth GaN tube, a thirty-eighth GaN tube, a thirty-ninth GaN tube, an eighth capacitor and an eleventh resistor form a driving stage; wherein the content of the first and second substances,
the drain electrode of the eleventh GaN tube is connected with the source electrode of the fourteenth GaN tube through a fifth resistor, the grid electrode of the eleventh GaN tube is connected with the source electrode of the eighth GaN tube, and the source electrode of the eleventh GaN tube is grounded; the drain electrode of the twelfth GaN tube is connected with the source electrode of the thirteenth GaN tube, the grid electrode of the twelfth GaN tube is connected with the source electrode of the eighth GaN tube, and the source electrode of the twelfth GaN tube is grounded; the drain electrode of the thirteenth GaN tube is connected with the power supply, and the grid electrode of the thirteenth GaN tube is connected with the source electrode of the fourteenth GaN tube after passing through the fifth resistor; the drain electrode of the fourteenth GaN tube is connected with the power supply, the connecting point of the source electrode of the fourteenth GaN tube and the fifth resistor is connected with one end of the third capacitor, and the other end of the third capacitor is connected with the source electrode of the thirteenth GaN tube; the drain electrode of the fifteenth GaN tube is connected with the source electrode of the nineteenth GaN tube, the grid electrode of the fifteenth GaN tube is connected with the source electrode of the thirteenth GaN tube, and the source electrode of the fifteenth GaN tube is grounded; the drain electrode of the sixteenth GaN tube is connected with the source electrode of the seventeenth GaN tube, the grid electrode of the sixteenth GaN tube is connected with the source electrode of the thirteenth GaN tube, and the source electrode of the sixteenth GaN tube is grounded; the drain electrode of the seventeenth GaN tube is connected with a power supply, and the grid electrode of the seventeenth GaN tube is connected with the source electrode of the nineteenth GaN tube; the drain electrode of the eighteenth GaN tube is connected with a power supply, the grid electrode of the eighteenth GaN tube is connected with the source electrode of the twenty-third GaN tube, the source electrode of the eighteenth GaN tube is connected with the drain electrode of the nineteenth GaN tube and one end of a fourth capacitor, and the other end of the fourth capacitor is connected with the source electrode of the seventeenth GaN tube; a sixth resistor is connected between the drain electrode and the source electrode of the nineteenth GaN tube; the source electrode of the seventeenth GaN tube is connected with one end of a seventh resistor, and the other end of the seventh resistor is connected with a power supply;
the drain electrode of the twentieth GaN tube is connected with the source electrode of the twenty-fourth GaN tube through the eighth resistor, the grid electrode of the twentieth GaN tube is connected with one end of the seventh resistor, and the source electrode of the twentieth GaN tube is grounded; the drain electrode of the twenty-first GaN tube is connected with the source electrode of the twenty-second GaN tube, the grid electrode of the twenty-first GaN tube is connected with one end of the seventh resistor, and the source electrode of the twenty-first GaN tube is grounded; the drain electrode of the twenty-second GaN tube is connected with the power supply, and the grid electrode of the twenty-second GaN tube is connected with the source electrode of the twenty-fourth GaN tube through an eighth resistor; the drain electrode of the twenty-third GaN tube is connected with a power supply, the grid electrode of the twenty-third GaN tube is connected with the source electrode of the eighteenth GaN tube, the source electrode of the twenty-third GaN tube is connected with the source electrode of the twenty-fourth GaN tube and one end of a fifth capacitor, and the other end of the fifth capacitor is connected with the source electrode of the twenty-second GaN tube; the drain electrode of the twenty-fourth GaN tube is connected with the power supply, and the grid electrode and the drain electrode of the twenty-fourth GaN tube are interconnected; the drain electrode, the grid electrode and the source electrode of the twenty-fifth GaN tube are all connected with a power supply; the drain electrode and the source electrode of the twenty-sixth GaN tube are connected with a power supply, and the grid electrode of the twenty-sixth GaN tube is connected with the source electrode of the eighteenth GaN tube; the grid electrode and the source electrode of the twenty-seventh GaN tube are connected with a power supply, and the drain electrode of the twenty-seventh GaN tube is connected with the drain electrode of the twenty-eighth GaN tube; the source electrode of the twenty-eighth GaN tube is connected with the power supply, and the grid electrode of the twenty-eighth GaN tube is connected with the source electrode of the eighteenth GaN tube; one end of the sixth capacitor is connected with the power supply, and the other end of the sixth capacitor is connected with the source electrode of the twenty-second GaN tube; the drain electrode of the twenty-ninth GaN tube is connected with the drain electrode of the twenty-eighth GaN tube, one end of the seventh capacitor, the grid electrode of the thirty-second GaN tube and the grid electrode of the thirty-third GaN tube through a ninth resistor, the grid electrode of the twenty-ninth GaN tube is connected with one end of the seventh resistor, and the source electrode of the twenty-ninth GaN tube is grounded; the drain electrode of the thirty-third GaN tube is connected with the source electrode of the thirty-third GaN tube, the grid electrode of the thirty-third GaN tube is connected with one end of the seventh resistor, and the source electrode of the thirty-third GaN tube is grounded; the drain electrode of the thirty-first GaN tube is connected with the source electrode of the thirty-second GaN tube, the grid electrode of the thirty-first GaN tube is connected with one end of the seventh resistor, and the source electrode of the thirty-first GaN tube is grounded; the drain electrode of the thirty-second GaN tube is connected with the power supply, and a tenth resistor is arranged between the drain electrode and the source electrode; the other end of the seventh capacitor is connected with a source electrode of the thirty-third GaN tube, and a drain electrode of the thirty-third GaN tube is connected with the power supply; the drain electrode of the thirty-fourth GaN tube is connected with the source electrode of the thirty-ninth GaN tube, the grid electrode of the thirty-fourth GaN tube is connected with one end of the seventh resistor, and the source electrode of the thirty-fourth GaN tube is grounded; the drain electrode of the thirty-fifth GaN tube is connected with the source electrode of the thirty-sixth GaN tube, the grid electrode of the thirty-fifth GaN tube is connected with one end of the seventh resistor after passing through the eleventh resistor, and the source electrode of the thirty-fifth GaN tube is grounded; the drain electrode of the thirty-sixth GaN tube is connected with the power supply, and the grid electrode of the thirty-ninth GaN tube is connected with the source electrode of the thirty-ninth GaN tube; the drain electrode of the thirty-seventh GaN tube is connected with the power supply, the grid electrode of the thirty-seventh GaN tube is connected with the source electrode of the eighteenth GaN tube, and the drain electrode of the thirty-seventeenth GaN tube is connected with the source electrode of the thirty-eighth GaN tube and one end of the eighth capacitor; the other end of the eighth capacitor is connected with a source electrode of the thirty-sixth GaN tube; the drain electrode of the thirty-eighth GaN tube is connected with the power supply, and the grid electrode and the drain electrode of the thirty-eighth GaN tube are interconnected; the drain electrode of the thirty-ninth GaN tube is connected with the source electrode of the thirty-eighth GaN tube, and the grid electrode of the thirty-ninth GaN tube is connected with the source electrode of the thirty-second GaN tube; and the drain electrode of the thirty-sixth GaN tube is an output end and is connected with the grid electrode of the GaN power tube.
The invention has the beneficial effects that: the cross-coupled charge pump is adopted to realize the rail-to-rail charging voltage of the bootstrap capacitor in the traditional bootstrap reverser, and the output rising speed of the bootstrap reverser is improved while the higher matching between the output rising speed and the output falling speed is realized. The power supply lifting module is added into the traditional two-stage structure bootstrap phase inverter for driving the GaN power tube to lift the output voltage of the bias stage to triple power supply voltage, so that the rising speed of the output voltage of the driving stage is improved, the mismatching of the rising slope and the falling slope of the grid electrode of the GaN power tube is reduced, the time delay of a driving chain is reduced, and the shorter conduction time of the GaN power tube is favorably realized. Four stages of bootstrap inverters are cascaded, so that the matching between the opening delay and the closing delay of the GaN power tube is improved.
Drawings
Fig. 1 is a schematic diagram of a conventional two-stage bootstrap inverter in an all-GaN gate-driven integrated circuit.
Fig. 2 is a block diagram of a high slew rate full GaN gate driving system according to the present invention.
Fig. 3 is a structural diagram of a high-slew-rate all-GaN gate driving circuit according to the present invention.
FIG. 4 is a schematic diagram of the operation of the GaN power transistor with high conversion rate and full GaN gate drive
Fig. 5 is a schematic diagram of the operation of the high slew rate all-GaN gate-driven off GaN power transistor according to the present invention.
Fig. 6 is a simulation diagram of a high-conversion-rate full GaN gate-driven switching GaN power transistor according to the present invention, wherein (a) is a simulation diagram of transmission delay, and (b) is a simulation diagram of gate-source voltage of the GaN power transistor.
Detailed Description
The operation of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 3 shows a circuit structure diagram of a high-conversion-rate all-GaN gate driving circuit provided by the invention, transistors in the circuit all adopt enhancement-type GaN transistors, wherein a GaN power tube is a high-voltage tube, and the rest GaN tubes are low-voltage tubes.
In the first and second stage bootstrap inverters, GaN tube E4、E9And a capacitor C1、C2Forming a cross-coupled charge pump between the first and second stage bootstrapped inverters. The first stage bootstrap phase inverter is composed of a GaN tube E1、E2、E3、E4、E5Resistance R1、 R2、R3And a capacitor C2Forming; e2For the output pull-down tube of the bootstrap inverter, E3For the output pull-up tube of the bootstrap inverter, E1For turning off E3Static power consumption is reduced; r1Determination of C1The charging voltage across and determines the static power consumption; r2、R3And E5Providing an initialization state for the primary input and the secondary input, when the PWM signal is high, E5And the power is turned off, and extra static power consumption is not consumed. The second stage bootstrap phase inverter is composed of a GaN tube E6、E7、E8、E9、E10Resistance R4And a capacitor C2Forming; e7For the output pull-down tube of the bootstrap inverter, E8For the output pull-up tube of the bootstrap inverter, E6For turning off E8Static power consumption is reduced; r4Determination of C2The charging voltage across and determines the static power consumption; e10Is C2Providing an initialization state of C2The initial voltage at the two ends is higher than the threshold voltage of the low-voltage GaN tube.
In the third and fourth stage bootstrap inverters, GaN tube E14、E18、E23、E26、E27、E37And a capacitor C3、C4、C5、 C6、C7、C8Forming a cross-coupled charge pump between the third and fourth stage bootstrapped inverters. In the third stage of bootstrap inverter, the bias stage is composed of GaN tube E20、E21、E22、E23Resistance R5And a capacitor C4The driving stage is composed of GaN tube E24、E25、 E26、E27、E28Resistance R6And a capacitor C5Forming; wherein E21、E25Output pull-down tubes for the bootstrap inverters in the bias and driver stages, E22And E26Output pull-up tubes for the bootstrap inverters in the bias and driver stages, E20And E24For turning off E22、 E26And E28Static power consumption is reduced; resistance R5And R6Determination of C4And C5The charging voltage across and determining the static power consumption, the resistance R7To initialize the resistor; e19For accelerating C4To E17The output rising speed of the third stage bootstrap inverter is improved by the charging speed of the grid source capacitor. In the fourth stage bootstrap phase inverter, the power supply lifting module is composed of a GaN tube E20、E21、E22、E23、E24、E25、E26、E27、E28Resistance R8And a capacitor C5、C6Forming; wherein E21And E22Respectively an output pull-down tube and an output pull-up tube of a bootstrap phase inverter in the power supply boost module, E20For turning off E22Static power consumption is reduced; resistance R8Determination of C5The charging voltage across and determines the static power consumption; e24，E25，E28Are respectively C5、C6、C7Providing an initialization state of C5、 C6And C7The voltage at two ends is higher than the threshold voltage of the low-voltage GaN tube; bias stage composed of GaN tube E29、E30、E31、E32、E33Resistance R9、R10And a capacitor C7Composition of, wherein E30Output pull-down tube for bias stage bootstrap inverter, E31For the output pull-up tube of the bias stage bootstrap inverter, E29For turning off E31And E33，E32For switching off the secondary charging tube E39Static power consumption is reduced; resistance R9、R10Determination of C7The charging voltage across and determines the static power consumption; the driving stage is composed of GaN tube E34、E35、E36、E37、 E38、E39Resistance R11And a capacitor C8Composition is carried out; wherein E35Output pull-down tube for driving stage bootstrap phase inverter, E36Output pull-up tube for driving stage bootstrap phase inverter, E34For turning off E36The zero static power consumption of the driving stage is realized; using GaN tubes E operating in the linear region39The output rising rate of the driving stage is improved instead of the resistance; e38Is C8Providing an initialization state of C8The voltage at two ends is higher than the threshold voltage of the low-voltage GaN tube; r11At turn-on and turn-off E35And E36Generating dead time therebetween, avoiding E35And E36And is simultaneously turned on.
The specific working principle of the circuit is shown in fig. 4 and 5.
Fig. 4 is a working schematic diagram of the high-conversion-rate full GaN gate driving GaN power transistor according to the present invention. At a bootstrap capacitor C1N、C3NAnd C4NUnder the condition of not being charged, when the PWM signal is logic low, the GaN tube E with short-circuited grid and drain is connected with the grid10N、E24N、E28NAnd E38NSeparately bootstrap capacitors C2N、C5N、C6NAnd C8NCharging the voltage at both ends to VCC-VTHGrid source short-connected GaN tube E25NC is to be7NCharging the voltage at both ends to VCC-VTH(VTHThreshold voltage of low-voltage GaN tube), implement C2N、C5N、C6N、C7NAnd C8NInitialization of the voltage across the terminals. When the PWM is inverted from logic low to logic high, the first stage bootstrap inverter outputs VO1NQuilt E2NRapidly pulling down to GND; in the second stage bootstrap inverter, because of bootstrap capacitor C2NHas an initialization voltage VCC-VTHOutput VO2NQuilt E8NPulling up to VCC. By cross-coupling charge pumps between first and second stage bootstrap inverters, E4NIs raised to 2VCC-VTH，E4NOperating in a deep linear region when R1NFar greater than E4NAt on-resistance of (C)1NBoth ends voltage is E4NCharging to VCC. Third stage bootstrapped inverter output VO3NQuilt E16NPulling down quickly to GND. In the fourth stage bootstrap inverter, C5N、C6N、C7NAnd C8NHas an initialization voltage VCC-VTHOutput V of bootstrap inverter in power boost moduleO41NQuilt E22NPull up to VCC. By cross-coupling charge pumps between third and fourth stage bootstrap inverters, E14NAnd E18NIs raised to 2VCC-VTH，E14NAnd E18NOperating in a deep linear region when R5NAnd R6NFar greater than E14NAnd E18NAt on-resistance of (C)3NAnd C4NBoth end voltages are respectively controlled by E14NAnd E18NCharging to VCC. By bootstrapping the capacitor C6NThe power supply rail of the bias stage of the fourth stage bootstrap inverter is raised to 2VCC-VTH. Bootstrap inverter output V in the biasing stageO42NQuilt E31NPull up to 2VCC-VTH，C7NThe potential of the upper polar plate is 3VCC-2VTH. By R9NDrive E33N，E33NAnd R10NParallel drive E39N，E39NThe gate voltage of the transistor finally rises to 3VCC-2VTH。E39NWorking in linear region after starting, low on-resistance, C8NBy working in the linear region E39NDrive E36NCan be quickly turned on36NIncreasing the grid end V of the GaN power tubeGNThe rising speed of (2).
At a bootstrap capacitor C1N、C3NAnd C4NWhen the PWM signal is logic low, with the voltage across the two terminals already charged to VCC, through the cross-coupled charge pumps between the first and second stage bootstrap inverters and the third and fourth stage bootstrap inverters, C2N、C5N、C6N、C7NAnd C8NE with voltages at both ends respectively operated in linear region9N、E23N、E27N、E26NAnd E37NAnd when the voltage is charged to VCC, the voltages at two ends of all bootstrap capacitors in the gate drive are VCC, and no loss of threshold voltage exists. When PWM is inverted from logic low to logic high, VO1NCan be E2NPull down to GND, V quicklyO2NCan be E8NQuickly pulled up to VDD, VO3NCan be E16NPulling down quickly to GND. In the fourth stage bootstrap phase inverter, the power supply lifting module lifts the power supply rail of the bias stage to 2VCC, and the bias stage lifts E39NEventually rising to 3 VCC. By reaction from R9NWarp E33NTo E39NManner of stepwise driving and39Nthe increase of the grid potential greatly increases E39NTo E36NHas reduced drive capability from VO3NDown to VGNA delay in the rise. At E36NIs much higher than E17NIn the case of (2), V can be ensuredGNAnd VO3NThe rising speed of the gate is close to the rising speed of the gate, and the matching between the transmission delay of the rising edge and the transmission delay of the falling edge of the gate drive is improved.
Fig. 5 is a working schematic diagram of a high-conversion-rate full GaN gate driving turn-off GaN power transistor according to the present invention. When the PWM signal is logic high, through cross-coupling charge pump, C1F、C3FAnd C4FIs charged to VCC. When PWM is inverted from logic high to logic low, VO1FQuilt E3FQuickly pulled up to VDD, VO2FQuilt E7FE, rapidly pulled down to GND and working in deep linear region9FC is to be2FThe voltage across the terminals is charged to VCC, E10FAnd (6) turning off. Bias stage pass drive E for a third stage bootstrap inverter19FCan be quickly turned on17FIncrease VO3FRising speed of (V)O3FFinally by E17FPull up to VCC. In the fourth stage bootstrap inverter, E23F、E26F、E27FAnd E37FWorking in deep linear zones, E24F、E25F、E28FAnd E38FOff, C5F、 C6F、C7FAnd C8FThe voltage across is charged to VCC and the bias stage supply voltage is VCC. E35FThe GaN power tube can be turned off quickly. E25FAnd E26FBy using a leaky port pair C7FCharging, avoiding C7FAnd the risk of gate oxide breakdown of the low-voltage GaN device when the upper plate potential is bootstrapped to 3 VCC.
FIG. 6(a) is a simulation of transmission delay of the full GaN gate driving circuit proposed by the present inventionAnd (5) a result chart. From PWM input to GaN power tube grid end (V)GS) The delay from 50% rise is 12.9ns, and the delay from 50% drop of PWM input to 50% drop of GaN power tube gate terminal is 14.1 ns. The delay difference of the grid end of the GaN power tube is 1.2ns when the grid end of the GaN power tube is turned on and turned off. From PWM input rising by 50% to GaN power tube drain voltage (V)DS) The turn-on delay from the PWM input reduction of 50% to the GaN power tube drain voltage increase of 10% is 13.8ns, and the turn-off delay from the PWM input reduction of 50% to the GaN power tube drain voltage increase of 10% is 13.6 ns. The delay difference of the GaN power tube drain terminal is 0.2 ns. The all-GaN-gate drive circuit provided by the invention has low drive delay and good delay matching.
Fig. 6(b) is a simulation result diagram of the gate-source voltage of the GaN power transistor in the all-GaN gate driving circuit according to the present invention. The time for the GaN power tube to rise from 10% to 90% is 2.2ns, and the time for the GaN power tube to fall from 90% to 10% is 2.3 ns. The GaN power tube gate end has high turn-on and turn-off speed, and the rising slope and the falling slope of the gate end have good matching.
In summary, the all-GaN gate driving circuit provided by the present invention adds a cross-coupled charge pump to the conventional all-GaN bootstrap inverter, so as to realize the rail-to-rail charging voltage of the bootstrap capacitor, improve the output rising speed of the bootstrap inverter, and improve the matching between the output rising slope and the output falling slope of the bootstrap inverter. A power supply lifting module is added into a traditional two-stage structure bootstrap phase inverter for driving a grid end of a GaN power tube to lift the output voltage of a bias stage to be triple power supply voltage, so that the grid lifting speed of the GaN power tube is increased, the mismatching of the grid lifting slope and the grid descending slope is reduced, and high-speed high-conversion-rate driving is realized. And good matching between the opening delay and the closing delay of the GaN power tube is realized by adopting a cascade mode of an even-level (four-level) bootstrap reverser.
Claims (2)
1. A full GaN gate drive circuit with high slew rate is characterized by comprising a first stage bootstrap inverter, a second stage bootstrap inverter, a third stage bootstrap inverter and a fourth stage bootstrap inverter which are sequentially cascaded, wherein cross-coupled charge pumps are arranged between the first stage bootstrap inverter and the second stage bootstrap inverter and between the third stage bootstrap inverter and the fourth stage bootstrap inverter; the third-stage bootstrap inverter adopts a mode of cascading an offset stage and a driving stage, wherein the offset stage provides an offset voltage which is twice of the power supply voltage for the driving stage, and the output rising rate of the bootstrap inverter is improved; on the basis of cascade connection of a bias stage and a driving stage in the fourth stage bootstrap inverter, a power supply boosting circuit is adopted to boost the power supply voltage of the bias stage to be twice of the gate driving power supply voltage, so that a bias voltage which is three times of the power supply voltage is provided for the driving stage, and the output rising rate of the fourth stage bootstrap inverter is increased; the input of the first stage bootstrap phase inverter is a PWM signal, and the output of the fourth stage bootstrap phase inverter is connected with the grid electrode of the GaN power tube; all transistors in the circuit are enhancement mode GaN transistors.
2. The all-GaN gate driving circuit with high slew rate of claim 1, wherein the first-stage bootstrapped inverter comprises a first GaN tube, a second GaN tube, a third GaN tube, a fourth GaN tube, a fifth GaN tube, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor, and the second-stage bootstrapped inverter comprises a sixth GaN tube, a seventh GaN tube, an eighth GaN tube, a ninth GaN tube, a tenth GaN tube, a fourth resistor and a second capacitor; the grid electrodes of the first GaN tube and the second GaN tube are connected with a PWM signal, the drain electrode of the first GaN tube is connected with the source electrode of the fourth GaN tube after passing through the first resistor, the source electrode of the first GaN tube is grounded, the drain electrode of the second GaN tube is connected with the source electrode of the third GaN tube, and the source electrode of the second GaN tube is grounded; the drain electrode of the third GaN tube is connected with a power supply, and the grid electrode of the third GaN tube is connected with the source electrode of the fourth GaN tube after passing through the first resistor; the drain electrode of the fourth GaN tube is connected with the power supply, and the grid electrode of the fourth GaN tube is connected with the source electrode of the ninth GaN tube; the source electrode of the fourth GaN tube is connected with one end of a first capacitor, the other end of the first capacitor is connected with the source electrode of the third GaN tube and one end of a second resistor, and the other end of the second resistor is connected with a power supply; the drain electrode of the fifth GaN tube is connected with the PWM signal through a third resistor, the grid electrode of the fifth GaN tube is connected with one end of the second resistor, and the source electrode of the fifth GaN tube is grounded; the drain electrode of the sixth GaN tube is connected with the source electrode of the tenth GaN tube through a fourth resistor, the grid electrode of the sixth GaN tube is connected with one end of the second resistor, and the source electrode of the sixth GaN tube is grounded; the drain electrode of the seventh GaN tube is connected with the source electrode of the eighth GaN tube, the grid electrode of the seventh GaN tube is connected with one end of the second resistor, and the source electrode of the seventh GaN tube is grounded; the drain electrode of the eighth GaN tube is connected with the power supply, and the grid electrode of the eighth GaN tube is connected with the source electrode of the tenth GaN tube after passing through the fourth resistor; the drain electrode of the ninth GaN tube is connected with a power supply, the grid electrode of the ninth GaN tube is connected with the source electrode of the fourth GaN tube, the source electrode of the ninth GaN tube is connected with the source electrode of the tenth GaN tube and one end of a second capacitor, and the other end of the second capacitor is connected with the source electrode of the eighth GaN tube; the drain electrode of the tenth GaN tube is connected with the power supply, and the grid electrode of the tenth GaN tube is interconnected with the drain electrode; the source electrode of the eighth GaN tube is the output end of the second-stage bootstrap phase inverter; the fourth GaN tube, the eighth GaN tube, the first capacitor and the second capacitor form a cross-coupled charge pump between the first-stage bootstrap inverter and the second-stage bootstrap inverter;
the third-stage bootstrap phase inverter comprises an eleventh GaN tube, a twelfth GaN tube, a thirteenth GaN tube, a fourteenth GaN tube, a fifteenth GaN tube, a sixteenth GaN tube, a seventeenth GaN tube, an eighteenth GaN tube, a nineteenth GaN tube, a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor and a fourth capacitor, wherein the eleventh GaN tube, the twelfth GaN tube, the thirteenth GaN tube, the fourteenth GaN tube, the third capacitor and the fifth resistor form a bias stage, and the fifteenth GaN tube, the sixteenth GaN tube, the seventeenth GaN tube, the eighteenth GaN tube, the nineteenth GaN tube, the sixth resistor, the seventh resistor and the fourth capacitor form a driving stage; the fourth-stage bootstrap phase inverter comprises a twentieth GaN tube, a twenty-first GaN tube, a twenty-twelfth GaN tube, a twenty-thirteenth GaN tube, a twenty-fourteenth GaN tube, a twenty-fifth GaN tube, a twenty-sixth GaN tube, a twenty-seventh GaN tube, a twenty-eighteenth GaN tube, a twenty-ninth GaN tube, a thirty-eighth GaN tube, a thirty-eleventh GaN tube, a thirty-twelfth GaN tube, a thirty-thirteenth GaN tube, a thirty-fourteenth GaN tube, a thirty-fifteenth GaN tube, a thirty-sixth GaN tube, a seventeenth GaN tube, a thirty-eighth GaN tube, a thirty-nineteenth GaN tube, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor, a twentieth GaN tube, a twenty-first GaN tube, a twenty-twelfth GaN tube, a twenty-thirteenth GaN tube, a twenty-fourteenth GaN tube, a twenty-fifth GaN tube, a twenty-sixth GaN tube, a twenty-seventh tube, a twenty-eighteenth GaN tube, a twenty-ninth tube, a twenty-eighth tube, a twenty-ninth GaN tube, a twenty-eighth tube, a fourth tube, a sixth tube, a fourth tube, a sixth tube, A fifth capacitor, a sixth capacitor and an eighth resistor form power supply promotion, a thirty-fifth GaN tube, a thirty-first GaN tube, a thirty-second GaN tube, a thirty-third GaN tube, a thirty-fourth GaN tube, a ninth resistor and a seventh capacitor form a bias stage, and a thirty-fifth GaN tube, a thirty-sixth GaN tube, a thirty-seventeenth GaN tube, a thirty-eighth GaN tube, a thirty-ninth GaN tube, an eighth capacitor and an eleventh resistor form a driving stage; wherein the content of the first and second substances,
the drain electrode of the eleventh GaN tube is connected with the source electrode of the fourteenth GaN tube through a fifth resistor, the grid electrode of the eleventh GaN tube is connected with the source electrode of the eighth GaN tube, and the source electrode of the eleventh GaN tube is grounded; the drain electrode of the twelfth GaN tube is connected with the source electrode of the thirteenth GaN tube, the grid electrode of the twelfth GaN tube is connected with the source electrode of the eighth GaN tube, and the source electrode of the twelfth GaN tube is grounded; the drain electrode of the thirteenth GaN tube is connected with the power supply, and the grid electrode of the thirteenth GaN tube is connected with the source electrode of the fourteenth GaN tube after passing through the fifth resistor; the drain electrode of the fourteenth GaN tube is connected with the power supply, the connecting point of the source electrode of the fourteenth GaN tube and the fifth resistor is connected with one end of the third capacitor, and the other end of the third capacitor is connected with the source electrode of the thirteenth GaN tube; the drain electrode of the fifteenth GaN tube is connected with the source electrode of the nineteenth GaN tube, the grid electrode of the fifteenth GaN tube is connected with the source electrode of the thirteenth GaN tube, and the source electrode of the fifteenth GaN tube is grounded; the drain electrode of the sixteenth GaN tube is connected with the source electrode of the seventeenth GaN tube, the grid electrode of the sixteenth GaN tube is connected with the source electrode of the thirteenth GaN tube, and the source electrode of the sixteenth GaN tube is grounded; the drain electrode of the seventeenth GaN tube is connected with a power supply, and the grid electrode of the seventeenth GaN tube is connected with the source electrode of the nineteenth GaN tube; the drain electrode of the eighteenth GaN tube is connected with a power supply, the grid electrode of the eighteenth GaN tube is connected with the source electrode of the twenty-third GaN tube, the source electrode of the eighteenth GaN tube is connected with the drain electrode of the nineteenth GaN tube and one end of a fourth capacitor, and the other end of the fourth capacitor is connected with the source electrode of the seventeenth GaN tube; a sixth resistor is connected between the drain electrode and the source electrode of the nineteenth GaN tube; the source electrode of the seventeenth GaN tube is connected with one end of a seventh resistor, and the other end of the seventh resistor is connected with a power supply;
the drain electrode of the twentieth GaN tube is connected with the source electrode of the twenty-fourth GaN tube through the eighth resistor, the grid electrode of the twentieth GaN tube is connected with one end of the seventh resistor, and the source electrode of the twentieth GaN tube is grounded; the drain electrode of the twenty-first GaN tube is connected with the source electrode of the twenty-second GaN tube, the grid electrode of the twenty-first GaN tube is connected with one end of the seventh resistor, and the source electrode of the twenty-first GaN tube is grounded; the drain electrode of the twenty-second GaN tube is connected with a power supply, and the grid electrode of the twenty-second GaN tube is connected with the source electrode of the twenty-fourth GaN tube through an eighth resistor; the drain electrode of the twenty-third GaN tube is connected with a power supply, the grid electrode of the twenty-third GaN tube is connected with the source electrode of the eighteenth GaN tube, the source electrode of the twenty-third GaN tube is connected with the source electrode of the twenty-fourth GaN tube and one end of a fifth capacitor, and the other end of the fifth capacitor is connected with the source electrode of the twenty-second GaN tube; the drain electrode of the twenty-fourth GaN tube is connected with the power supply, and the grid electrode and the drain electrode of the twenty-fourth GaN tube are interconnected; the drain electrode, the grid electrode and the source electrode of the twenty-fifth GaN tube are all connected with a power supply; the drain electrode and the source electrode of the twenty-sixth GaN tube are connected with a power supply, and the grid electrode of the twenty-sixth GaN tube is connected with the source electrode of the eighteenth GaN tube; the grid electrode and the source electrode of the twenty-seventh GaN tube are connected with a power supply, and the drain electrode of the twenty-seventh GaN tube is connected with the drain electrode of the twenty-eighth GaN tube; the source electrode of the twenty-eighth GaN tube is connected with the power supply, and the grid electrode of the twenty-eighth GaN tube is connected with the source electrode of the eighteenth GaN tube; one end of the sixth capacitor is connected with the power supply, and the other end of the sixth capacitor is connected with the source electrode of the twenty-second GaN tube; the drain electrode of the twenty-ninth GaN tube is connected with the drain electrode of the twenty-eighth GaN tube, one end of the seventh capacitor, the grid electrode of the thirty-second GaN tube and the grid electrode of the thirty-third GaN tube through a ninth resistor, the grid electrode of the twenty-ninth GaN tube is connected with one end of the seventh resistor, and the source electrode of the twenty-ninth GaN tube is grounded; the drain electrode of the thirty-third GaN tube is connected with the source electrode of the thirty-third GaN tube, the grid electrode of the thirty-third GaN tube is connected with one end of the seventh resistor, and the source electrode of the thirty-third GaN tube is grounded; the drain electrode of the thirty-first GaN tube is connected with the source electrode of the thirty-second GaN tube, the grid electrode of the thirty-first GaN tube is connected with one end of the seventh resistor, and the source electrode of the thirty-first GaN tube is grounded; the drain electrode of the thirty-second GaN tube is connected with the power supply, and a tenth resistor is arranged between the drain electrode and the source electrode; the other end of the seventh capacitor is connected with a source electrode of the thirty-third GaN tube, and a drain electrode of the thirty-third GaN tube is connected with the power supply; the drain electrode of the thirty-fourth GaN tube is connected with the source electrode of the thirty-ninth GaN tube, the grid electrode of the thirty-fourth GaN tube is connected with one end of the seventh resistor, and the source electrode of the thirty-fourth GaN tube is grounded; the drain electrode of the thirty-fifth GaN tube is connected with the source electrode of the thirty-sixth GaN tube, the grid electrode of the thirty-fifth GaN tube is connected with one end of the seventh resistor after passing through the eleventh resistor, and the source electrode of the thirty-fifth GaN tube is grounded; the drain electrode of the thirty-sixth GaN tube is connected with the power supply, and the grid electrode of the thirty-ninth GaN tube is connected with the source electrode of the thirty-ninth GaN tube; the drain electrode of the thirty-seventh GaN tube is connected with the power supply, the grid electrode of the thirty-seventh GaN tube is connected with the source electrode of the eighteenth GaN tube, and the drain electrode of the thirty-seventeenth GaN tube is connected with the source electrode of the thirty-eighth GaN tube and one end of the eighth capacitor; the other end of the eighth capacitor is connected with a source electrode of the thirty-sixth GaN tube; the drain electrode of the thirty-eighth GaN tube is connected with the power supply, and the grid electrode and the drain electrode of the thirty-eighth GaN tube are interconnected; the drain electrode of the thirty-ninth GaN tube is connected with the source electrode of the thirty-eighth GaN tube, and the grid electrode of the thirty-ninth GaN tube is connected with the source electrode of the thirty-second GaN tube; and the drain electrode of the thirty-sixth GaN tube is an output end and is connected with the grid electrode of the GaN power tube.
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