CN105634461A - Level shift circuit - Google Patents
Level shift circuit Download PDFInfo
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- CN105634461A CN105634461A CN201511005198.3A CN201511005198A CN105634461A CN 105634461 A CN105634461 A CN 105634461A CN 201511005198 A CN201511005198 A CN 201511005198A CN 105634461 A CN105634461 A CN 105634461A
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- 238000007667 floating Methods 0.000 claims abstract description 58
- 230000005669 field effect Effects 0.000 claims description 105
- 238000001914 filtration Methods 0.000 claims description 21
- 230000001737 promoting effect Effects 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 abstract 1
- 238000012913 prioritisation Methods 0.000 description 9
- 238000012423 maintenance Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
Abstract
The invention provides a level shift circuit for controlling on-off of a power tube. The level shift circuit comprises a narrow pulse generator which outputs a first narrow pulse signals according to a rising edge of low-pressure duty ratio signals and outputting second narrow pulse signals according to a falling edge of the input low-pressure duty ratio signals; a level shift module which reverses the first narrow pulse signals and lifts level to somewhere between the positive electrode of a floating power supply and the ground to obtain first high-level reverse signals and reverses the second narrow pulse signals and lifts level to somewhere between the positive electrode of the floating power supply and the ground to obtain second high-level reverse signals; a signal latch register which outputs high-pressure duty ratio signals according to the first high-level reverse signals and the second high-level reverse signals; and a driving-grade circuit which controls the opening and closing of the power tube according to the high-pressure duty ratio signals and has an input end accessed to the high-level duty ratio signals and an output end connected with the grid of the power tube. According to the invention, the short-pulse driving capability is large, level shift is rapidly realized, the level shift time is shortened, and power consumption is reduced.
Description
Technical field
The present invention relates to the control techniques field of high tension apparatus, specifically, it relates to a kind of level shift circuit being applicable in floating power supply rail.
Background technology
Low-voltage control signal is converted to high voltage control signal by level shift circuit, realize low voltage logic to the control of high-voltage power output stage, the control techniques field being applied to high tension apparatus, is widely applied in motor driving, plasma display (PDP), organic light-emitting diode display (OLED) and FLASH memory circuit etc. In the control techniques field of high tension apparatus, pilot circuit and high-voltage output drive circuit can be integrated, it is achieved high withstand voltage, big current, high precision.
Low-voltage control signal is converted under high voltage control signal is used for driving high pressure output stage NMOS (should the be NMOS) pipe worked by conventional level shift circuit. Level shift circuit is as connection control circuit and exports the Key Circuit driving level, had both needed responding ability fast, and had needed again lower quiescent current, and also had needed to ensure higher stability and reliability simultaneously. Prior art usually adopt voltage stabilizing tube as the clamper components and parts in level shift circuit, the problem that this kind of structure has cost height, processing requirement is high.
Summary of the invention
For defect of the prior art, it is an object of the invention to provide a kind of level shift circuit.
According to a kind of level shift circuit provided by the invention, for controlling the break-make of power tube, comprising: spike pulse producer, level shift module, signal latch, driving level circuit;
Described spike pulse producer is used for the positive rise according to low pressure duty cycle signals and exports the first narrow pulse signal, the 2nd narrow pulse signal is exported with the negative edge of the described low pressure duty cycle signals according to input, the reversal rate of described first narrow pulse signal and the 2nd narrow pulse signal is all greater than described low pressure duty cycle signals, the power supply end of described spike pulse producer is connected to low-voltage power supply, and the input terminus of described spike pulse producer accesses described low pressure duty cycle signals;
Described level shift module is for oppositely by described first narrow pulse signal and promoting and obtain the first reverse signal of high level between current potential to the n-ground of floating power supply, and described 2nd narrow pulse signal oppositely and is promoted and obtains the 2nd reverse signal of high level between current potential to the n-ground of described floating power supply, first input terminus described first narrow pulse signal of access of described level shift module, the 2nd input terminus described 2nd narrow pulse signal of access of described level shift module;
Described signal latch is used for exporting high pressure duty cycle signals according to the reverse signal of the described first reverse signal of high level and the 2nd high level, the set input described first reverse signal of high level of access of described signal latch, the zero setting input terminus described 2nd reverse signal of high level of access;
Described driving level circuit is used for controlling opening and turning off of power tube according to described high pressure duty cycle signals, and the input terminus of described driving level circuit accesses described high pressure duty cycle signals, and output terminal connects the grid of described power tube.
As a kind of prioritization scheme, described level shift module comprises the first high-pressure MOS field effect transistor, the 2nd high-pressure MOS field effect transistor, the first clamper MOS field effect transistor, the 2nd clamper MOS field effect transistor, the first resistance, the 2nd resistance;
The grid of described first high-pressure MOS field effect transistor is described first input terminus, accesses described first narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the source electrode of described first clamper MOS field effect transistor,
The grid of described first clamper MOS field effect transistor connects the ground of described floating power supply, drain electrode connects the positive pole of described floating power supply, described first resistance is accessed, between the drain electrode of the set input described first high-pressure MOS field effect transistor of access of described signal latch and the source electrode of described first clamper MOS field effect transistor between drain electrode and source electrode;
The grid of described 2nd high-pressure MOS field effect transistor is described 2nd input terminus, accesses described 2nd narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the source electrode of described 2nd clamper MOS field effect transistor,
The grid of described 2nd clamper MOS field effect transistor connects the ground of described floating power supply, drain electrode connects the positive pole of described floating power supply, described 2nd resistance is accessed, between the drain electrode of the zero setting input terminus described 2nd high-pressure MOS field effect transistor of access of described signal latch and the source electrode of described 2nd clamper MOS field effect transistor between drain electrode and source electrode.
As a kind of prioritization scheme, the resistance of described first resistance and the 2nd resistance is all within the scope of 1k ����10k ��.
As a kind of prioritization scheme, the threshold voltage of described first high-pressure MOS field effect transistor and the 2nd high-pressure MOS field effect transistor is all greater than the threshold voltage of described first clamper MOS field effect transistor and the 2nd clamper MOS field effect transistor.
As a kind of prioritization scheme, described level shift module comprises the first high-pressure MOS field effect transistor, the 2nd high-pressure MOS field effect transistor, the first clamper triode, the 2nd clamper triode, the first diode, the 2nd diode;
The grid of described first high-pressure MOS field effect transistor is described first input terminus, accesses described first narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the emtting electrode of described first clamper triode,
The base stage of described first clamper triode connects the ground of described floating power supply, collector electrode connects the positive pole of described floating power supply, between the drain electrode of the set input described first high-pressure MOS field effect transistor of access of described signal latch and the emtting electrode of described first clamper triode
The negative pole of described first diode connects the collector electrode of described first clamper triode, and positive pole connects the emtting electrode of described first clamper triode;
The grid of described 2nd high-pressure MOS field effect transistor is described 2nd input terminus, accesses described 2nd narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the emtting electrode of described 2nd clamper triode,
The base stage of described 2nd clamper triode connects the ground of described floating power supply, collector electrode connects the positive pole of described floating power supply, between the drain electrode of the zero setting input terminus described 2nd high-pressure MOS field effect transistor of access of described signal latch and the emtting electrode of described 2nd clamper triode
The negative pole of described 2nd diode connects the collector electrode of described 2nd clamper triode, and positive pole connects the emtting electrode of described 2nd clamper triode.
As a kind of prioritization scheme, the resistance of described first diode and the 2nd diode is all within the scope of 1k ����10k ��.
As a kind of prioritization scheme, the threshold voltage of described first high-pressure MOS field effect transistor and the 2nd high-pressure MOS field effect transistor is all greater than the threshold voltage of described first clamper triode and the 2nd clamper triode.
As a kind of prioritization scheme, the potential difference between described floating power supply normal incidence is 10��20V.
As a kind of prioritization scheme, also comprise noise filtering circuit;
The described first reverse signal of high level that described level shift module exports accesses the set input of described signal latch by described noise filtering circuit,
The described 2nd reverse signal of high level that described level shift module exports accesses the zero setting input terminus of described signal latch by described noise filtering circuit.
As a kind of prioritization scheme, described noise filtering circuit is made up of two groups of RC wave filters; The set input of RC wave filter described in a group for exporting described signal latch after the reverse signal filtering of described first high level to, another organizes described RC wave filter for the zero setting input terminus by exporting described signal latch after the reverse signal filtering of described 2nd high level to.
Compared with prior art, the present invention has following useful effect:
Present configuration is simple, and the narrow pulse signal that spike pulse producer obtains is carried out level shift by level shift module, and this kind of short pulse mode is because driving force is big, it is possible to realize level shift fast, such that it is able to improve operating frequency. In addition, spike pulse mode makes the level shift circuit short period of time work, and has saved power consumption. The structure that level shift module is consisted of the first diode d1, the 2nd diode d2, the first clamper triode Q1, the 2nd clamper triode Q2, or the first clamper effect of clamper MOS field effect transistor NM3 and the 2nd clamper MOS field effect transistor NM4, prevent the too low signal latch caused of current potential from damaging problem. Relative to scheme of the prior art, the present invention reduces the requirement becoming production art, also reduces manufacturing cost, it is to increase the stability of circuit and reliability, be conducive to applying.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in embodiment being described is briefly described, obviously, accompanying drawing in the following describes is only some embodiments of the present invention, for those skilled in the art, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings. In accompanying drawing:
Fig. 1 is a kind of level shift circuit structure block diagram in optional embodiment;
Fig. 2 is a kind of level shift circuit structure in optional embodiment;
Fig. 3 is another kind of level shift circuit structure in optional embodiment;
Fig. 4 is each stage waveform comparison schematic diagram in circuit.
Embodiment
Hereafter in the way of specific embodiment, the present invention is described in detail by reference to the accompanying drawings. The technician contributing to this area is understood the present invention by following examples further, but does not limit the present invention in any form. It should be appreciated that other embodiment can also be used, or the embodiment enumerated is carried out the amendment on structure and function herein, and can not depart from the scope and spirit of the present invention.
At a kind of level shift circuit provided by the invention, for controlling the break-make of power tube, as shown in the structure block diagram of Fig. 1, comprising: spike pulse producer, level shift module, signal latch, driving level circuit;
Described spike pulse producer is used for the positive rise according to low pressure duty cycle signals and exports the first narrow pulse signal, the 2nd narrow pulse signal is exported with the negative edge of the described low pressure duty cycle signals according to input, the reversal rate of described first narrow pulse signal and the 2nd narrow pulse signal is all greater than described low pressure duty cycle signals, the power supply end of described spike pulse producer is connected to low-voltage power supply, and the input terminus of described spike pulse producer accesses described low pressure duty cycle signals;
Described level shift module is for oppositely by described first narrow pulse signal and promoting and obtain the first reverse signal of high level between current potential to the n-ground of floating power supply, and described 2nd narrow pulse signal oppositely and is promoted and obtains the 2nd reverse signal of high level between current potential to the n-ground of described floating power supply, first input terminus described first narrow pulse signal of access of described level shift module, the 2nd input terminus described 2nd narrow pulse signal of access of described level shift module;
Described signal latch is used for exporting high pressure duty cycle signals according to the reverse signal of the described first reverse signal of high level and the 2nd high level, the set input described first reverse signal of high level of access of described signal latch, the zero setting input terminus described 2nd reverse signal of high level of access;
Described driving level circuit is used for controlling opening and turning off of power tube according to described high pressure duty cycle signals, and the input terminus of described driving level circuit accesses described high pressure duty cycle signals, and output terminal connects the grid of described power tube.
The power supply end of described level shift module, signal latch, driving level circuit is all connected to floating power supply.
In embodiment shown in Fig. 1, input low pressure duty cycle signals is pwm signal, VDD and GND is the VDD-to-VSS of low-voltage power supply part. BST and SW is the VDD-to-VSS of high pressure floating power supply rail part. PVIN is the service voltage of controlled power tube. Low-voltage power supply part only spike pulse and circuit part before thereof in figure, level shift module and latter linked noise filtering circuit, signal latch, driving level be all belong to high pressure floating power supply rail part. The floating power supply rail of high pressure described in this patent refers to bootstrap circuit, also claims boost-up circuit, and between BST-SW, relative pressure is constant, but current potential can raise, as floated to 220V-200V from the 20V-0V of SW ground connection state. VDD-GND is then low-voltage power supply, and is solid ground power supply, such as the 20V-0V got in 15V-0V or the present embodiment. Floating power supply is common circuit in prior art, not its structure of detail in the present invention.
In Fig. 1, when inputting pwm signal, spike pulse producer respectively produces a narrow pulse signal i.e. the first narrow pulse signal PWM_R and the 2nd narrow pulse signal PWM_F according to the positive rise of pwm signal and negative edge, as shown in Figure 4.
Wherein narrow pulse signal rises to 220V-200V corresponding to BST-SW the amplitude of input signal from the 20V-0V that VDD-GND is corresponding through level shift circuit. This kind of short pulse mode is because driving force is big, it is possible to realize level shift fast, such that it is able to improve operating frequency. In addition, spike pulse mode makes the level shift circuit short period of time work, and has saved power consumption.
As a kind of embodiment, level shift circuit also comprises noise filtering circuit;
The described first reverse signal of high level that described level shift module exports accesses the set input of described signal latch by described noise filtering circuit,
The described 2nd reverse signal of high level that described level shift module exports accesses the zero setting input terminus of described signal latch by described noise filtering circuit.
The first reverse signal of high level, the 2nd reverse signal of high level that signal exports from level shift module are still narrow pulse signals, but signal level has been converted into 220V-200V corresponding to BST-SW. In order to prevent the noise jamming in circuit, after followed again one-level noise filtering circuit, be conducive to preventing the signal latch false triggering of follow-up connection, thus cause power tube mishandle. Signal latch has the characteristic of pulse signals sensitivity, if therefore there is noise jamming, follow-up output will be produced bigger impact. Noise filters the zero setting input terminus R in output signal and Fig. 4 and set input S. After noise filtering circuit and R-S signal latch, signal becomes again duty cycle signals (high pressure duty cycle signals) from narrow pulse signal, but high pressure duty signal level has been promoted to 220V-200V corresponding to BST-SW, finally achieving from low pressure duty cycle signals to the level shift of high pressure duty cycle signals, high pressure duty cycle signals is shown in the Q signal in Fig. 4. The high pressure duty cycle signals Q that signal latch exports controls opening and turning off of power tube PM1 after level of overdriving, and thus achieves PWM low-voltage signal to the control of high drive level and power tube.
Described noise filtering circuit is made up of two groups of RC wave filters; The set input S of RC wave filter described in a group for exporting described signal latch after the reverse signal filtering of described first high level to, another organizes described RC wave filter for the zero setting input terminus R by exporting described signal latch after the reverse signal filtering of described 2nd high level to. RC wave filter is filter circuit construction conventional in this area. The RC filter construction adopted in the present invention is see Fig. 2, Fig. 3: be made up of a resistance and an electric capacity, the output terminal of resistance one end level shift module, the input terminus of another termination signal latch; Electric capacity one end is accessed between described resistance and signal latch, the ground (i.e. SW pole) of another termination floating power supply.
A kind of embodiment being illustrated in figure 2 in Fig. 1 level shift module, described level shift module comprises the first high-pressure MOS field effect transistor NM1, the 2nd high-pressure MOS field effect transistor NM2, the first clamper MOS field effect transistor NM3, the 2nd clamper MOS field effect transistor NM4, the first resistance R1, the 2nd resistance R2;
The grid of described first high-pressure MOS field effect transistor NM1 is described first input terminus, access described first narrow pulse signal, source electrode connects the ground (low pressure GND) of described low-voltage power supply, and drain electrode connects the source electrode of described first clamper MOS field effect transistor NM3
The grid of described first clamper MOS field effect transistor NM3 connects the ground of described floating power supply, drain electrode connects the positive pole of described floating power supply, described first resistance R1 is accessed, between the drain electrode of the set input described first high-pressure MOS field effect transistor NM1 of access of described signal latch and the source electrode of described first clamper MOS field effect transistor NM3 between drain electrode and source electrode;
The grid of described 2nd high-pressure MOS field effect transistor NM2 is described 2nd input terminus, access described 2nd narrow pulse signal, source electrode connects the ground (low pressure GND) of described low-voltage power supply, and drain electrode connects the source electrode of described 2nd clamper MOS field effect transistor NM4
The grid of described 2nd clamper MOS field effect transistor NM4 connects the ground of described floating power supply, drain electrode connects the positive pole of described floating power supply, described 2nd resistance R2 is accessed, between the drain electrode of the zero setting input terminus described 2nd high-pressure MOS field effect transistor NM2 of access of described signal latch and the source electrode of described 2nd clamper MOS field effect transistor NM4 between drain electrode and source electrode.
The resistance of described first resistance R1 and the 2nd resistance R2 is all within the scope of 1k ����10k ��, and described first resistance R1 is identical with the resistance of the 2nd resistance R2, it is possible to be 1k ��, or 5k ��, or 10k ��.
The threshold voltage of described first high-pressure MOS field effect transistor NM1 and the 2nd high-pressure MOS field effect transistor NM2 is all greater than the threshold voltage of described first clamper MOS field effect transistor NM3 and the 2nd clamper MOS field effect transistor NM4. In the present embodiment, floating power supply can boost to 220V-200V from 20V-0V, described first high-pressure MOS field effect transistor NM1 and the 2nd high-pressure MOS field effect transistor NM2 need to bear floating power supply and boost to, from 20V-0V, the high voltage differential that 220V-200V causes, therefore it is required that have the performance that can bear high pressure. And the first clamper MOS field effect transistor NM3 and the 2nd clamper MOS field effect transistor NM4 only needs to bear the voltage difference of floating power supply positive pole relative to floating ground, therefore only need to bear 20V voltage, it is not necessary to high pressure requirement. The present embodiment requires to select different devices according to different performance, it is achieved best cost performance.
When PWM becomes high, the first narrow pulse signal PWM_R becomes high, and the first high-pressure MOS field effect transistor NM1 conducting, the n1 point voltage that level shift module is connected with described signal latch set input S is drawn low, and electric current is through the first resistance R1. When the SW of the voltage ratio floating power supply of n1 point is low, and voltage difference is when being greater than the threshold voltage of the first clamper MOS field effect transistor NM3, first clamper MOS field effect transistor NM3 conducting, now part electric current is through the first clamper MOS field effect transistor NM3, the voltage of n1 point can not reduce again, but by the first clamper MOS field effect transistor NM3 clamper. The pressure reduction that positive pole BST to the n1 of such floating power supply puts would not be excessive, and the signal being input to signal latch set input S also will make signal latch be damaged because of too low. Arriving the set input S of signal latch after the change of n1 point voltage is low through RC wave filter, signal latch set input S Low level effective, signal latch is set, and it is high for exporting high pressure duty cycle signals Q. When the first narrow pulse signal PWM_R spike pulse disappear again become low after, the first high-pressure MOS field effect transistor NM1 turns off. N1 point is charged by the first resistance R1, and last voltage equals BST voltage. The voltage that RC wave filter exports signal latch set input S to also becomes BST voltage, but the output of signal latch maintenance high level is constant, sees signal Q in Fig. 4.
When PWM becomes low, the 2nd narrow pulse signal PWM_F becomes high, and the 2nd high-pressure MOS field effect transistor NM2 conducting, the n2 point voltage that level shift module is connected with described signal latch zero setting input terminus R is drawn low, and electric current is through the 2nd resistance R2. When the SW of the voltage ratio floating power supply of n2 point is low, and when voltage difference is greater than the threshold voltage of the 2nd clamper MOS field effect transistor NM4, the 2nd clamper MOS field effect transistor NM4 conducting. Now part electric current is through the 2nd clamper MOS field effect transistor NM4, and the voltage of n2 point can not reduce again, by the 2nd clamper MOS field effect transistor NM4 clamper. The pressure reduction that positive pole BST to the n2 of such floating power supply puts would not be excessive, and the signal being input to signal latch zero setting input terminus R also will make signal latch be damaged because of too low. Arriving signal latch zero setting input terminus R through RC wave filter after the change of n2 point voltage is low, signal latch zero setting input terminus R Low level effective, signal latch is reset, and the described high pressure duty cycle signals Q of output becomes low, see signal Q in Fig. 4. When the 2nd narrow pulse signal PWM_F spike pulse disappear again become low after, 2nd high-pressure MOS field effect transistor NM2 turns off, n2 point voltage is charged by resistance R2, last voltage equals BST voltage, the voltage that RC wave filter exports signal latch zero setting input terminus R to also becomes BST voltage, but the output of signal latch maintenance lower level is constant.
When BST and the SW voltage of floating power supply becomes low simultaneously, n1 and n2 point voltage can be discharged by n1 and n2 by the parasitic diode of the first clamper MOS field effect transistor NM3 and the 2nd clamper MOS field effect transistor NM4 so that the voltage of n1 and n2 too much can not damage late-class circuit higher than the positive pole BST of floating power supply and ground SW. MOS field effect transistor produces described parasitic diode due to its manufacturing process, it is not necessary to additionally increase setting.
On circuit realiration, above-mentioned parasitic diode can also with the diode in place of non-parasitism. In figure, the clamper function of NM3 and NM4 can also be replaced by NPN triode. Wherein the collector electrode of triode meets BST, and base stage meets SW, launches level and meets n1 and n2. In addition, the function of NM3 and NM4 directly can also carry out clamper with zener pipe, and the P level of zener pipe meets n1 and n2, and N level meets BST.
Thus can design the embodiment of another kind of level shift module, in embodiment as shown in Figure 3, described level shift module comprises the first high-pressure MOS field effect transistor NM1, the 2nd high-pressure MOS field effect transistor NM2, the first clamper triode Q1, the 2nd clamper triode Q2, the first diode d1, the 2nd diode d2;
The grid of described first high-pressure MOS field effect transistor NM1 is described first input terminus, accesses described first narrow pulse signal, and source electrode connects the ground (low pressure GND) of described low-voltage power supply, and drain electrode connects the emtting electrode of described first clamper triode Q1,
The base stage of described first clamper triode Q1 connects the ground of described floating power supply, collector electrode connects the positive pole of described floating power supply, between the drain electrode of the set input described first high-pressure MOS field effect transistor NM1 of access of described signal latch and the emtting electrode of described first clamper triode Q1
The negative pole of described first diode d1 connects the collector electrode of described first clamper triode Q1, and positive pole connects the emtting electrode of described first clamper triode Q1;
The grid of described 2nd high-pressure MOS field effect transistor NM2 is described 2nd input terminus, accesses described 2nd narrow pulse signal, and source electrode connects the ground (low pressure GND) of described low-voltage power supply, and drain electrode connects the emtting electrode of described 2nd clamper triode Q2,
The base stage of described 2nd clamper triode Q2 connects the ground of described floating power supply, collector electrode connects the positive pole of described floating power supply, between the drain electrode of the zero setting input terminus described 2nd high-pressure MOS field effect transistor NM2 of access of described signal latch and the emtting electrode of described 2nd clamper triode Q2
The negative pole of described 2nd diode d2 connects the collector electrode of described 2nd clamper triode Q2, and positive pole connects the emtting electrode of described 2nd clamper triode Q2.
As a kind of embodiment, the resistance of described first diode d1 and the 2nd diode d2 is all within the scope of 1k ����10k ��, and described first diode d1 is identical with the resistance of the 2nd diode d2, it is possible to be 1k ��, or 5k ��, or 10k ��. The threshold voltage of described first high-pressure MOS field effect transistor NM1 and the 2nd high-pressure MOS field effect transistor NM2 is all greater than the threshold voltage of described first clamper triode Q1 and the 2nd clamper triode Q2. Described floating power supply positive pole relatively between potential difference be 10��20V.
In embodiment as shown in Figure 3, when PWM becomes high, the first narrow pulse signal PWM_R becomes high, the first high-pressure MOS field effect transistor NM1 conducting, the n1 point voltage that level shift module is connected with described signal latch set input S is drawn low, and electric current is through the first diode d1. When the SW of the voltage ratio floating power supply of n1 point is low, and voltage difference is when being greater than the threshold voltage of the first clamper triode Q1, the first clamper triode Q1 conducting, now part electric current is through the first clamper triode Q1, the voltage of n1 point can not reduce again, but by the first clamper triode Q1 clamper. The pressure reduction that positive pole BST to the n1 of such floating power supply puts would not be excessive, and the signal being input to signal latch set input S also will make signal latch be damaged because of too low. Arriving the set input S of signal latch after the change of n1 point voltage is low through RC wave filter, signal latch set input S Low level effective, signal latch is set, and it is high for exporting high pressure duty cycle signals Q. When the first narrow pulse signal PWM_R spike pulse disappear again become low after, the first high-pressure MOS field effect transistor NM1 turns off. N1 point is charged by the first diode d1, and last voltage equals BST voltage. The voltage that RC wave filter exports signal latch set input S to also becomes BST voltage, but the output of signal latch maintenance high level is constant, sees signal Q in Fig. 4.
When PWM becomes low, the 2nd narrow pulse signal PWM_F becomes high, and the 2nd high-pressure MOS field effect transistor NM2 conducting, the n2 point voltage that level shift module is connected with described signal latch zero setting input terminus R is drawn low, and electric current is through the 2nd diode d2. When the SW of the voltage ratio floating power supply of n2 point is low, and when voltage difference is greater than the threshold voltage of the 2nd clamper triode Q2, the 2nd clamper triode Q2 conducting. Now part electric current is through the 2nd clamper triode Q2, and the voltage of n2 point can not reduce again, by the 2nd clamper triode Q2 clamper. The pressure reduction that positive pole BST to the n2 of such floating power supply puts would not be excessive, and the signal being input to signal latch zero setting input terminus R also will make signal latch be damaged because of too low. Arriving signal latch zero setting input terminus R through RC wave filter after the change of n2 point voltage is low, signal latch zero setting input terminus R Low level effective, signal latch is reset, and the described high pressure duty cycle signals Q of output becomes low, see signal Q in Fig. 4. When the 2nd narrow pulse signal PWM_F spike pulse disappear again become low after, 2nd high-pressure MOS field effect transistor NM2 turns off, n2 point voltage is charged by resistance R2, last voltage equals BST voltage, the voltage that RC wave filter exports signal latch zero setting input terminus R to also becomes BST voltage, but the output of signal latch maintenance lower level is constant.
When BST and the SW voltage of floating power supply becomes low simultaneously, n1 and n2 point voltage can be discharged by n1 and n2 by the first diode d1 and the 2nd diode d2 so that the voltage of n1 and n2 too much can not damage late-class circuit higher than the positive pole BST of floating power supply and ground SW.
Present configuration is simple, by the first diode d1 and the 2nd diode d2, or the clamper effect of the first clamper MOS field effect transistor NM3 and the 2nd clamper MOS field effect transistor NM4, it is possible to ensure the stability of whole level shift circuit, it is to increase the reliability of circuit. Relative to scheme of the prior art, present invention reduces manufacturing cost, be conducive to applying.
The foregoing is only the better embodiment of the present invention, it will be understood by those skilled in the art that without departing from the spirit and scope of the present invention, it is possible to these characteristic sum embodiments are carried out various change or equivalent replacement. In addition, under the teachings of the present invention, it is possible to these characteristic sum embodiments modify to adapt to concrete situation and material and the spirit and scope of the present invention can not be departed from. Therefore, the present invention is not by the restriction of specific embodiment disclosed herein, and the embodiment in the right of all the application of falling into all belongs to protection scope of the present invention.
Claims (10)
1. a level shift circuit, for controlling the break-make of power tube, it is characterised in that, comprising: spike pulse producer, level shift module, signal latch, driving level circuit;
Described spike pulse producer is used for the positive rise according to low pressure duty cycle signals and exports the first narrow pulse signal, the 2nd narrow pulse signal is exported with the negative edge of the described low pressure duty cycle signals according to input, the reversal rate of described first narrow pulse signal and the 2nd narrow pulse signal is all greater than described low pressure duty cycle signals, the power supply end of described spike pulse producer is connected to low-voltage power supply, and the input terminus of described spike pulse producer accesses described low pressure duty cycle signals;
Described level shift module is for oppositely by described first narrow pulse signal and promoting and obtain the first reverse signal of high level between current potential to the n-ground of floating power supply, and described 2nd narrow pulse signal oppositely and is promoted and obtains the 2nd reverse signal of high level between current potential to the n-ground of described floating power supply, first input terminus described first narrow pulse signal of access of described level shift module, the 2nd input terminus described 2nd narrow pulse signal of access of described level shift module;
Described signal latch is used for exporting high pressure duty cycle signals according to the reverse signal of the described first reverse signal of high level and the 2nd high level, the set input described first reverse signal of high level of access of described signal latch, the zero setting input terminus described 2nd reverse signal of high level of access;
Described driving level circuit is used for controlling opening and turning off of power tube according to described high pressure duty cycle signals, and the input terminus of described driving level circuit accesses described high pressure duty cycle signals, and output terminal connects the grid of described power tube.
2. a kind of level shift circuit according to claim 1, it is characterized in that, described level shift module comprises the first high-pressure MOS field effect transistor, the 2nd high-pressure MOS field effect transistor, the first clamper MOS field effect transistor, the 2nd clamper MOS field effect transistor, the first resistance, the 2nd resistance;
The grid of described first high-pressure MOS field effect transistor is described first input terminus, accesses described first narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the source electrode of described first clamper MOS field effect transistor,
The grid of described first clamper MOS field effect transistor connects the ground of described floating power supply, drain electrode connects the positive pole of described floating power supply, described first resistance is accessed, between the drain electrode of the set input described first high-pressure MOS field effect transistor of access of described signal latch and the source electrode of described first clamper MOS field effect transistor between drain electrode and source electrode;
The grid of described 2nd high-pressure MOS field effect transistor is described 2nd input terminus, accesses described 2nd narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the source electrode of described 2nd clamper MOS field effect transistor,
The grid of described 2nd clamper MOS field effect transistor connects the ground of described floating power supply, drain electrode connects the positive pole of described floating power supply, described 2nd resistance is accessed, between the drain electrode of the zero setting input terminus described 2nd high-pressure MOS field effect transistor of access of described signal latch and the source electrode of described 2nd clamper MOS field effect transistor between drain electrode and source electrode.
3. a kind of level shift circuit according to claim 2, it is characterised in that, the resistance of described first resistance and the 2nd resistance is all within the scope of 1k ����10k ��.
4. a kind of level shift circuit according to claim 2, it is characterized in that, the threshold voltage of described first high-pressure MOS field effect transistor and the 2nd high-pressure MOS field effect transistor is all greater than the threshold voltage of described first clamper MOS field effect transistor and the 2nd clamper MOS field effect transistor.
5. a kind of level shift circuit according to claim 1, it is characterized in that, described level shift module comprises the first high-pressure MOS field effect transistor, the 2nd high-pressure MOS field effect transistor, the first clamper triode, the 2nd clamper triode, the first diode, the 2nd diode;
The grid of described first high-pressure MOS field effect transistor is described first input terminus, accesses described first narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the emtting electrode of described first clamper triode,
The base stage of described first clamper triode connects the ground of described floating power supply, collector electrode connects the positive pole of described floating power supply, between the drain electrode of the set input described first high-pressure MOS field effect transistor of access of described signal latch and the emtting electrode of described first clamper triode
The negative pole of described first diode connects the collector electrode of described first clamper triode, and positive pole connects the emtting electrode of described first clamper triode;
The grid of described 2nd high-pressure MOS field effect transistor is described 2nd input terminus, accesses described 2nd narrow pulse signal, and source electrode connects the ground of described low-voltage power supply, and drain electrode connects the emtting electrode of described 2nd clamper triode,
The base stage of described 2nd clamper triode connects the ground of described floating power supply, collector electrode connects the positive pole of described floating power supply, between the drain electrode of the zero setting input terminus described 2nd high-pressure MOS field effect transistor of access of described signal latch and the emtting electrode of described 2nd clamper triode
The negative pole of described 2nd diode connects the collector electrode of described 2nd clamper triode, and positive pole connects the emtting electrode of described 2nd clamper triode.
6. a kind of level shift circuit according to claim 5, it is characterised in that, the resistance of described first diode and the 2nd diode is all within the scope of 1k ����10k ��.
7. a kind of level shift circuit according to claim 5, it is characterised in that, the threshold voltage of described first high-pressure MOS field effect transistor and the 2nd high-pressure MOS field effect transistor is all greater than the threshold voltage of described first clamper triode and the 2nd clamper triode.
8. a kind of level shift circuit according to claim 1, it is characterised in that, the potential difference between described floating power supply normal incidence is 10��20V.
9. a kind of level shift circuit according to claim 1, it is characterised in that, also comprise noise filtering circuit;
The described first reverse signal of high level that described level shift module exports accesses the set input of described signal latch by described noise filtering circuit,
The described 2nd reverse signal of high level that described level shift module exports accesses the zero setting input terminus of described signal latch by described noise filtering circuit.
10. a kind of level shift circuit according to claim 9, it is characterised in that, described noise filtering circuit is made up of two groups of RC wave filters; The set input of RC wave filter described in a group for exporting described signal latch after the reverse signal filtering of described first high level to, another organizes described RC wave filter for the zero setting input terminus by exporting described signal latch after the reverse signal filtering of described 2nd high level to.
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| CN111917408A (en) * | 2020-08-13 | 2020-11-10 | 聚辰半导体股份有限公司 | High-voltage level conversion circuit and high-voltage level conversion system |
| CN113079331A (en) * | 2021-03-31 | 2021-07-06 | 中国科学院长春光学精密机械与物理研究所 | TDICCD reset driving circuit of space camera |
| CN115085707A (en) * | 2022-06-23 | 2022-09-20 | 四川锶未铼科技有限公司 | Silicon carbide MOSFET grid driving circuit and method |
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