WO2013011289A2

WO2013011289A2 - Switching circuits

Info

Publication number: WO2013011289A2
Application number: PCT/GB2012/051673
Authority: WO
Inventors: Richard Anthony Mcmahon; Florent GUEDON; Santosh Kumar Singh; Philip John GARSED
Original assignee: Cambridge Enterprise Limited
Priority date: 2011-07-15
Filing date: 2012-07-13
Publication date: 2013-01-24
Also published as: WO2013011289A3; GB201112144D0

Abstract

We describe a protection circuit for a normally-on silicon carbide JFET, comprising a first power switching connection coupled to the JFET drain; a gate driver circuit; and a normally-off MOSFET in series between the JFET source and a second power switching connection. The circuit includes a diode having an anode coupled to JFET gate and a cathode coupled between a second power switching connection and a source/drain connection of the MOSFET. A control circuit is coupled to the gate of the MOSFET to sense a failure of a power supply to the gate driver circuit and to switch off the MOSFET in response, for example using a bias circuit powered from this power supply. When the MOSFET is off the external power maintains the gate of the JFET negative with respect to the source, via a circuit including the internal capacitance of the off MOSFET and the diode.

Description

Switching Circuits

FIELD OF THE INVENTION This invention relates to switching circuits and, more particularly to protection circuits for normally-on transistors, especially silicon carbide (SiC) junction field effect transistors (JFETs).

BACKGROUND TO THE INVENTION

With the increasing demand for power converters, especially with high power densities, and Silicon (Si) devices reaching their theoretical limits, Silicon Carbide (SiC) is the object of growing interest. As a semiconductor, it possesses several advantages over Si, leading to the fabrication of devices with lower specific on-resistance, a higher breakdown voltage, or a combination of these. It is also capable of operation at higher temperatures (it is still semiconducting at 700°C). Therefore, devices made in SiC can handle a high power density. Unipolar SiC tansistors can in addition work at high switching frequencies. This makes of SiC transistors, and more generally power converters using them, ideal candidates for use in hybrid and electric cars.

Thus important commercial applications for SiC devices include hybrid and electric cars, where the high power density in a high temperature ambient is a significant advantage, and harsh environments such as aerospace, where SiC is more reliable than Si. As the price of SiC devices is likely to come down in the future, SiC power converters could replace conventional Si power converters in a wide range of applications, with lower losses.

A SiC power transistor which can retain all the advantages of SiC is the JFET. However, it is a normally-on device, i.e. it needs a negative voltage to be turned off, and it is on in the absence of a gate bias voltage. Therefore it needs protection when used in a circuit as a fault in the gate drive power supply could leave the JFET permanently on. If a JFET is permanently on, depending on circuit configuration, there is a high chance of a short-circuit. Background prior art can be found in US2008/0174184. Normally-off JFETs have been made but they are not an ideal solution since the gate driver must provide a sizable gate current to keep the JFET on. Also the performance of a silicon carbide JFET is, in effect, degraded to convert the JFET to normally-off operation.

We will give techniques for use in SiC circuits to enhance user safety and to reduce the risk of destroying a device in the case of a fault in the driver power supply.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is therefore provided a silicon carbide power semiconductor switching circuit, the circuit comprising: first and second power switching connections; a silicon carbide (SiC) junction field effect transistor (JFET) comprising a drain, a source and a gate terminal, wherein said first power switching connection is coupled to said drain connection of said SiC JFET; a gate driver circuit having a control input to control switching of said SiC JFET and a gate drive output connected to said gate terminal of said SiC JFET; a series-protection semiconductor switching device having first and second switched connections and a control connection to control switching of said semiconductor switching device, wherein said semiconductor switching device is connected in series between said source terminal of said SiC JFET and said second power switching connection via said switched connections of said semiconductor switching device; a diode having an anode coupled to said gate terminal of said SiC JFET and a cathode coupled to a junction between said second power switching connection and a said switched connection of said semiconductor switching device; and a control circuit coupled to said control connection of said semiconductor switching device to sense a fault condition and to control said semiconductor switching device to switch off responsive to said sensed fault condition.

Broadly speaking by connecting a diode between the gate of the JFET and the drain of the MOSFET, the series coupled arrangement can be driven by a gate driver circuit but "fails safe". Furthermore, embodiments of this circuit are suitable for high junction temperature operation of the SiC device, for example >150°C, 175°C or 200°C, in part because the JFET and the MOSFET can be implemented in different packages. This also allows the JFET to switch quickly without being slowed down by the MOSFET.

The semiconductor switching device need not be a high-voltage MOSFET. It can advantageously be a low-voltage (<50 volts) MOSFET. Indeed, low-voltage MOSFETs may have a relatively low on resistance, in embodiments <1 00ΓΠΩ, for example - ^"Ι ΟΓΠΩ, and because absent a fault condition the MOSFET is not switching there are no switching losses. Nonetheless in principle other semiconductor switching devices may be employed, for example an IGBT (although the on-state characteristics are less desirable so the losses are greater).

In embodiments the MOSFET is a normally-off silicon or other semiconductor device (i.e. the device is off in the absence of a gate bias voltage), and the control circuit includes a bias circuit dedicated to the MOSFET to bias the MOSFET on. Conveniently the MOSFET is a PMOS MOSFET and the source of the MOSFET is connected to the source of the SiC JFET; this facilitates control of the MOSFET gate voltage with respect to the source voltage to turn the MOSFET off when a fault condition is detected. In preferred embodiments the control circuit is configured to sense a voltage on a power supply rail providing power to the gate driver circuit, and to turn the semiconductor switching device (MOSFET) off when this sensed voltage falls below a threshold level, in embodiments by removing the gate bias on a normally-off silicon MOSFET. Thus the control circuit may comprise a resistor in series with a Zener diode, with one end of the resistor connected to the positive supply rail and the anode of the Zener diode connected to the other supply rail. The voltage across the resistor can provide a turn-off signal for the MOSFET. In some preferred implementations the circuit also includes a (relatively large) pull-down resistor across the power supply to the gate driver circuit so that the MOSFET is switched off rapidly (otherwise a control signal derived from a power supply rail in this manner may be left floating and take a relatively long time to change, for example of order 1 00ms).

In embodiments, when the semiconductor switching device (MOSFET) is off the drain- source capacitance across this device is charged such that the potential on the source terminal of the JFET rises and its gate potential becomes negative with respect to the source, shutting the JFET off when the gate source voltage of the JFET reaches the pinch-off voltage. Once the JFET is off, it blocks the remaining voltage of the power circuit. Therefore, the switching device (MOSFET) only blocks a voltage of order the modulus of the pinch-off voltage of the JFET, generally not more than 30 volts. Thus a low voltage MOSFET device may be employed. In effect the voltage to make the gate terminal of the JFET negative with respect to the source is derived from the power circuit that the JFET is connected to, via the charging of the drain-source capacitance of the MOSFET. In principle a current path between the source terminal of the JFET, via the internal capacitance of the MOSFET to the gate terminal could be provided by a wire, but this would inhibit normal operation as it would make the gate-source voltage of the JFET null when the MOSFET is in the on state (i.e. when no fault is detected). Thus, connecting this wire would force the JFET in the on state all the time, as long as no fault is detected by the protection circuit. Instead, therefore, a diode is connected between the far side of the semiconductor switching device (ie the switched connection not connected to the JFET) and the gate of the JFET, to block a reverse voltage (ie with the anode of the diode connected towards the gate of the JFET). The skilled person will appreciate that the diode could be, for example, the built-in diode of a MOSFET (although in practice this may not have desirable characteristics). Alternatively the diode could potentially be replaced by another switching device such as a MOSFET, controlled to provide an equivalent effect to that of the unidirectional current flow through a diode, more particularly to disconnect the gate terminal of the JFET from its source terminal during normal use, that is when the series-protection semiconductor switching device is on. Thus when the semiconductor switching device is off, an internal capacitance, or a combination of external and internal capacitances, between the switched connections of the semiconductor switching device charges, via current from the source terminal of the JFET, such that a voltage on the source terminal becomes greater than a voltage on the gate terminal of said JFET, to turn the JFET off via the diode (or other switching device).

In some preferred embodiments the gate driver circuit for the JFET comprises a constant current source (here the term "source" includes a current sink) to maintain a gate potential of the JFET at substantially a point of avalanche breakdown of a gate- source junction of the JFET when the JFET is to be off. The current drawn by the current source should be made small in order not to risk damaging on the gate-source junction of the JFET, and also not to waste power. Use of a constant current source in this way effectively forces the JFET to an operating point where it is switched off and gives the best noise margin possible (i.e. the margin between the avalanche breakdown voltage and the pinch-off voltage). It also caters for the possible variation in avalanche and pinch-off voltages between different JFETs. Historically this variation was considerable, but it has improved significantly with advances in fabrication technologies. In some preferred embodiments the gate driver circuit also includes a speed-up gate capacitor coupled between the gate terminal of the JFET and a power supply rail via a secondary controllable switch or MOSFET, a main switch or MOSFET controlling the turn-on of the JFET. When the JFET is to be turned on the primary switch makes a direct connection between the gate and source of the JFET and thus the switching is fast, but when the JFET is turned off the increase of the gate-source potential of the JFET (as it becomes more negative) is relatively slow since the current drawn by the current source is small (therefore the charging of the gate-source capacitance of the JFET is relatively slow). This is addressed by switching in an additional capacitor at the point of turn-off to, in effect, dump charge from this additional capacitor into the gate-source capacitance of the JFET. This additional capacitor is charged during the period when the JFET is off and this charge is dumped into the gate terminal when the JFET is next turned off, thus increasing the turn-off switching speed. With such an arrangement it is preferable to switch this additional capacitor in for only a relatively short time, to save power, noting that in any case this period must end before the main MOSFET switch is turned on to avoid shorting out this additional capacitance. Thus in embodiments the switching series with this additional speed-up capacitance may be pulsed on, for example by controlling the secondary switch using a pulse generator circuit triggered by a control signal switching the JFET off, for example an edge of a gate drive signal for the JFET.

In a related aspect the invention provides a method of protecting a silicon carbide (SiC) junction field effect transistor (JFET), the method comprising: connecting a normally-off semiconductor switch in series with said JFET such that a switched connection of said semiconductor switch is connected to a source terminal of said JFET; providing power to a drain terminal of said JFET; driving a gate terminal of said JFET to control a flow of said power from said drain terminal through said series-connected JFET and semiconductor switch; biasing said semiconductor switch on to provide a current path from said source terminal of said JFET; and arranging for said biasing to be removed on detection of a fault, such that on removal of said biasing said semiconductor switch reverts to a normally-off state and a voltage on said source terminal of said JFET rises to reverse bias a gate-source junction of said JFET to drive said JFET off.

The invention further provides a circuit protecting a silicon carbide (SiC) junction field effect transistor (JFET), the circuit comprising: a normally-off semiconductor switch connected in series with said JFET such that a switched connection of said semiconductor switch is connected to a source terminal of said JFET; a connection to a drain terminal of said JFET to receive power for switching; a gate driver for driving a gate terminal of said JFET to control a flow of said power from said drain terminal through said JFET and said semiconductor switch; a bias circuit to bias said semiconductor switch on to provide a current path to said source connection, wherein said bias circuit is configured to remove said bias on detection of a fault such that on removal of said biasing said semiconductor switch reverts to a normally-off state and a voltage on said source terminal rises to reverse bias a gate-source junction of said JFET to drive said JFET off.

The invention still further provides a method of protecting a silicon carbide JFET, the method comprising: connecting a normally-off silicon MOSFET in series with said silicon carbide JFET such that a source terminal of said JFET is connected to a source/drain terminal of said MOSFET; biasing said MOSFET on; and switching said MOSFET off by removing said biasing, on detection of a fault.

The above described circuits and methods are particularly useful when employed with a normally-on silicon carbide JFET but may also be advantageously employed with quasi normally-off transistors (which block only a fraction of their rated voltage when there is no bias on their gate-source junction).

Further, although preferred embodiments of the above described techniques are applied to a silicon carbide, normally-on JFET in principle the techniques may be applied to protect other power semiconductor switching devices, for example a MOSFET or an IGBT (insulated gate bipolar transistor). Similarly, the techniques may be applied to p-channel JFET devices as well as to n-channel devices.

The voltage across the semiconductor switching device (MOSFET) may be measured to detect a fault. Optionally the voltage across this device/MOSFET may be used to sense a current flowing through the power semiconductor switching device. Conveniently the sensed voltage may be referenced to a power rail of a driver circuit for the power semiconductor switching device. In a related aspect, therefore, the invention provides a method of protecting a power semiconductor switching device, the method comprising: connecting a normally-off MOSFET in series with said power semiconductor switching device; biasing said MOSFET on; sensing a voltage across said MOSFET; and removing said biasing on said MOSFET to allow said MOSFET to switch off on detection that said voltage across said MOSFET is greater than a threshold value.

Additionally or alternatively, if only an overcurrent is detected, but the power supply of the gate driver is still working, the protection circuit does not have to be triggered. Instead the JFET may just be turned off in the normal way, that is using a gate driver circuit.

The invention also provides a circuit for protecting a power semiconductor switching device, the circuit comprising: a normally-off MOSFET connected in series with said power semiconductor switching device; a bias circuit for biasing said MOSFET on; a circuit for sensing a voltage across said MOSFET; and a system for removing said biasing on said MOSFET, to allow said MOSFET to switch off, on detection that said voltage across said MOSFET is greater than a threshold value.

In the above described method and circuit aspects of the invention which sense a voltage across the MOSFET, additionally or alternatively, if only an overcurrent is detected, but the power supply of the gate driver is still working, the protection circuit does not have to be triggered. Instead the JFET may just be turned off in the normal way, that is using a gate driver circuit. In principle the control techniques for the speed-up capacitor may be employed independently of the protection circuit.

Thus in a further aspect the invention provides a gate driver for a silicon carbide junction field effect transistor (JFET) comprising: a gate drive output for driving a gate terminal of said silicon carbide JFET; a constant current source to maintain a gate potential of said JFET at substantially a point of avalanche breakdown of a gate source junction of said JFET when said JFET is off; a speed-up capacitor connected in series with a first controllable switch, wherein said speed-up capacitor is coupled between said gate terminal of said JFET and a power rail via said first controllable switch; and a second controllable switch coupled across said gate and source terminals of said JFET; wherein said first and second controllable switches are controlled such that each one is on when the other is off, to charge said speed-up capacitor with a turn-off voltage for applying to said gate terminal of said JFET when said JFET is turned off; and wherein said first and second controllable switches are controlled said that said first controllable switch is pulsed on for a period then off when said second controllable switch is turned off.

Typically high voltage or power semiconductor devices (and circuits) such as the above described JFET are operable with a voltage in the range 20V to 1 .2 kV and typically higher than 30V, or 50V. Current capability of such a device may be in the range 10mA to 50A and is typically higher than 0.1 A and smaller than 20A. Such devices are typically capable of delivering up to >1W, >10W, >100W or >1000W, for example up to a few kilowatts of power.

In embodiments of the above described aspects of the invention the functions of the gate driver may be provided on a PCB (Printed Circuit Board) or integrated into a single Integrated Circuit (IC) such as an ASIC (Application Specific IC), or into a hybrid circuit, for example a hybrid circuit constructed on a high-temperature ceramic substrate. Alternatively some combination of these technologies may be employed.

In embodiments, particularly where a ceramic hybrid circuit is employed, the silicon carbide semiconductor die may be directly bonded to the substrate. Such a SiC die is preferably located adjacent to the gate driver electronics and connected to the gate driver circuit through (very) short bond wires. This reduces parasitic effects and leads to faster, more efficient switching.

In some preferred embodiments the gate driver is controllable through a simple logic- level interface. For example, the input to the gate driver may be a logic level signal or an input to an optoisolator. The gate driver may include isolation and/or signal conditioning circuitry to implement this functionality.

In embodiments an isolated, on-board power supply is provided for the gate driver IC. The integrated/hybrid circuit becomes a more attractive 'drop in' option if providing power is easy for the user. By adding a small switching (and/or linear) isolated power supply on board the (isolated) power requirements of the gate driver can be supplied from a single power input provided by the user. In embodiments of the above described aspects of the invention the gate driver circuit is configured to apply a (small) positive gate voltage to the gate of the SiC JFET gate, to reduce the on-state resistance for improved efficiency. In embodiments this is achieved by providing a power supply for the gate which is able to provide both a positive voltage below the turn-on threshold of the SiC JFET, and a negative voltage sufficient to turn off the SiC JFET, where "positive" and "negative" are referenced to the voltage at the source of the JFET (W). This may comprise a controllable floating, isolated power supply for the gate. The positive voltage below the turn-on threshold of the SiC JFET may, for example, be a voltage of less than 3V, 2.5V, 2V, 1 .5V, 1 V or 0.5V.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying figures in which:

Figures 1 a to 1 c show, respectively, typical operating characteristics of a normally-on silicon carbide JFET inset with an outline of a driver circuit, and first and second example silicon carbide JFET gate driver circuits; Figures 2a and 2b show an outline circuit diagram of an embodiment of a silicon carbide JFET protection circuit according to an embodiment of the invention, and a simple equivalent circuit illustrating the effect of the circuit of Figure 2a when protection is triggered and there is no diode;

Figure 3 shows an outline circuit diagram of a silicon carbide JFET gate driver circuit incorporating a protection circuit according to an embodiment of the invention; and

Figure 4 shows the silicon carbide JFET gate driver circuit of Figure 1 b incorporating the silicon carbide JFET protection circuit of Figure 2.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Broadly speaking we will describe techniques to address the problems outline in the Introduction while retaining the advantages of using a SiC transistor, in particular by putting a small Si MOSFET in series with the SiC JFET, and arranging for the Si MOSFET to be always on unless a fault is detected. Therefore this does not add switching losses; in embodiments it does not impede the high temperature operation as the MOSFET can be in a different package to the JFET.

Referring to Figure 1 a, this shows curves of current against gate-source voltage for a normally-on silicon carbide JFET. As can be seen the drain current l_D begins to increase as V_GS increases above a pinch-off voltage V_po, typically of order -10 to -20 volts. Below this voltage the transistor is off. As V_GS increases above zero volts the gate current l_G increases; the gate current also increases as V_GS increases (becomes more negative) above an avalanche breakdown voltage V_x, which may be of order -20 to -40 volts. The gate-source junction of the JFET can be considered as equivalent to a zener diode and thus the current increases when V_GS becomes too negative.

The values of V_po and V_x can vary from one device to another and it can be the case that V_x of one device is less negative than V_po of another. It can therefore be advantageous to employ a controlled current drive rather than a controlled voltage drive to turn the JFET on and off, illustrated schematically by the inset circuit diagram (in which the fictional zener diode is shown dotted). Indeed, putting the JFET in a soft avalanche breakdown state to turn it off gives the best noise margin possible during the off state. Not shown in this circuit are the internal gate-source capacitance and the internal gate-drain (Miller) capacitance. When switch S is off the constant current I forces V_GS to substantially V_x so that the JFET is on the point of avalanche breakdown (I is typically small, for example of order 10 to 100 μΑ, to keep the gate-source junction safe and reduce power losses). When switch S is closed V_GS goes to zero and the JFET is turned on (a quick process). However when switch S is turned off the rise of V_GS is relatively slow because of slow charging of the gate-source capacitance of the JFET by the current source, and it is therefore advantageous to add a capacitor C_speed in series with a switch S_speed arranged so that S_speed is on when S is off, and vice versa. In this way when the JFET is off C_speed is charged to substantially V_B - V_x (current source I, typically a current mirror, maintains this voltage); this voltage is maintained when Sspeed is opened, and when the JFET is turned off by opening S and closing Sspeed, Cspeed charges the gate-source capacitance of the JFET via the power supply V_B and other decoupling capacitors potentially placed in the circuit, resulting in fast turn- off. (Provided C_speed is much larger than the Miller capacitance of the JFET, this also helps to reduce the effect of the Miller capacitance which would otherwise tend to cause a current surge in the gate driver when the potential of the drain of the JFET changes suddenly, potentially creating a jump in the gate-source voltage of the JFET. Cspeed helps to absorb the current spike from the Miller capacitance without any significant rise in the gate-source voltage.

The outline schematic diagram also shows a voltage source B: absent this voltage source the current source I would have to provide power to the rest of the circuit.. Thus conveniently the circuit includes a power supply to provide a voltage V_B which is sufficiently high so as to always be above the modulus value of V_x, that is (V_B - |V_X|) is always positive. Thus, for example, V_B may be approximately 39 volts (typical values for V_x and V_po are minus 25 volts and minus 20 volts respectively). V_B may be much smaller if the absolute value of the gate-source avalanche breakdown voltage of the SiC JFETs is lower. For example, if |V_X| < 22V, V_B could be 24V; if |V_X| < 13V, V_B could be 15V. In practice V_B may be provided from a DC/DC converter. The use of the voltage source with V_B - V_x always positive enables the use of a simple current mirror as current sink. The current sink does not provide any power to the circuit. All the power is provided by the power supply V_B. Referring now to Figure 1 b, this shows an example embodiment of a normally-on silicon carbide JFET gate driver circuit 100, embodying the above principles. Thus the circuit comprises a silicon carbide JFET 102, with a source coupled to a VCC line 104 at, in this example, 15 volts above the potential of a ground line 106. The input current to a Wilson current mirror 108 is set by the value of a resistor R, 1 10, approximately as (39V - 0.7V - 0.7V)/R. This in turn sets the current on an output 1 12 of the current mirror 108 which is applied, via a diode 1 14, to a gate connection 1 16 of JFET 102. The current sink is a Wilson current mirror for a good stability but other configurations for a current sink will also work. The Bipolar Junction Transistors (BJTs) in this current mirror are preferably as similar as possible; the optional emitter resistors assist stability.

The driver circuit is responsive to a logical output signal on line 1 18 from a MOSFET driver circuit 120 which, in turn, received JFET switching control data. The signal on line 1 18 controls a main switch S, MOSFET 122, which can either short the gate and source of JFET 102 (via a resistor) or allow the current mirror 108 to control a current to drive the gate voltage to the avalanche breakdown voltage of JFET 102. The "battery" (voltage source) is conveniently split into first and second batteries 124, 126 of, respectively, 15 volts and 24 volts (although in practice these may be implemented by DC/DC converters). A MOSFET 128 functions as switch S_speed to connect capacitor 130 to the gate of JFET 102 via a diode 132. Thus capacitor 130 acts as the speed-up capacitor.

When the output 1 18 of driver 120 (driving JFET 102) changes from on to off capacitor 135 charges and the charging current is sensed by resistor 134. The voltage across this resistor first peaks and then decays and this controls a PMOS MOSFET 136 with gate and source connections to, respectively, either side of resistor 134. Thus MOSFET 136 pulses on and this pulse is applied, via a level shift circuit comprising a zener diode 138a and resistor 138b, to pulse MOSFET switch 128 on for a brief interval to apply the speed up capacitor to the gate of JFET 102.

Continuing to refer to Figure 1 b, when a transistor is used in a bridge, because the transistor cannot be turned off instantaneously there is a deadtime before each rising edge in the control signals. Therefore, when a transistor is turned off, the complementary transistor remains off for the deadtime. Just after the deadtime, this complementary transistor turns on and the potential of the middle point in the bridge jumps. This jump in potential induces a jump in the voltage across the Miller capacitance of the transistor which is off. A sudden change in voltage across a capacitor translates into a surge in the current drawn by this capacitor, and this current surge is fed back into the gate driver. As the surge can be large, it can induce a spike in the gate-source voltage and therefore turn the transistor back on and lead to short- circuits. Consequently, the gate driver should preferably be able to absorb the sizeable Miller capacitance current without turning the transistor back on. In the gate driver of Figure 1 b, the speed-up capacitor can play this role if its value is large compared to the Miller capacitance ( C_GD ). Diode 132 should also be a fast diode so it can let the Miller capacitance current surge flow through. However, this absorbed current increases the voltage across the speed-up capacitor. The increase is small over one cycle, but it would reach high values after a few cycles if there was no discharge path for this extra energy. Resistor 131 is employed to provide such a discharge path. Its value should be chosen so that it can discharge any extra energy due to the Miller capacitance current.

Transistor 122 is switch S in Figure 1 a. When this transistor is on, it puts 0 V across the gate-souce junction of the JFET by discharging rapidly the gate-source capacitance C_GS . Here the transistor shown is a p-channel MOSFET because it is convenient to control in this particular circuit. However it may in principle be any switch (including for example a n-channel MOSFET). Resistor 123 is a turn-on gate resistor; its value should be small for fast turn-on.

In Figure 1 b the power supply V_power is 39 V and is split into 15 V + 24 V . This was convenient for the JFETs employed in a constructed embodiment since their pinch-off voltage varied between -15 and -19 V and V_x ( V_{GS br} ) is always 3 to 4 V below V_Po .

However other JFETs have pinch-off voltages much smaller in absolute value and thus a smaller value for V_power could be employed. The same gate driver would work with a

V of 24 or 15 V . In the latter case, diode 138a may be unnecessary. The circuit of Figure 1 b works well as long as the transistor is switched every cycle, but if for a cycle the transistor is not switched (because, for example, the voltage pulse is too small or the modulation index of the driving scheme removes some pulses), then the speed-up capacitor is not switched in either and it does absorb the Miller capacitance current.

Figure 1 c shows a variant of the circuit of Figure 1 b in which the speed-up capacitor is switched in for the whole time the JFET is off. In Figure 1 c the gate driver uses a MOSFET driver which has an inverting and a non-inverting output. When the input to the MOSFET driver is low, the output of the inverting pin is high. It charges CI and therefore turns Ml on. Ml remains on for the whole time the input to the MOSFET driver is low. When the input to the MOSFET driver goes to high, a current flows through Rl for a short time, turning Ml on for this short time. Ml discharges CI and therefore turns Ml off. This way of turning off Ml is fast, which is desirable because if M₂ is still on, even for a short time, when M3 is switched on, the speed-up capacitor will charge to a different voltage than that desired. Once again, in this example, V_power is composed of 15 V + 24 V but there could be only the 15 V voltage source if, say, V_GS of the JFET is not too negative. Protection

Referring again to Figure 1 b, it can be seen that if both of batteries 124, 126 fail the gate-source voltage on JFET 102 will eventually go to zero and the JFET becomes permanently on. Figure 2a shows an outline circuit diagram of an embodiment of a silicon carbide JFET protection circuit 200 according to the invention, which addresses this problem. Thus the circuit comprises a normally-off MOSFET 202 coupled to a biasing circuit 204. The biasing circuit comprises, in essence, a zener diode 206 connected across batteries 124, 126 to provide a gate voltage on line 208 to MOSFET 202. Thus a turn-off signal for MOSFET 202 on line 208 is derived from a power supply for the JFET gate driver circuit (this is not essential but for good fail-safe protection it is helpful if the turn-off circuit for MOSFET 202 is derived "locally"). The gate of MOSFET 202 could be connected directly to the negative terminal of the batteries (via a resistor) but the arrangement illustrated is preferred as it protects where there is a "brown out" of the gate driver power supply. Thus if, say, the threshold voltage of MOSFET 202 is around 3 volts then if, say, the battery voltage falls from 39 volts to 33 volts the gate-source voltage of MOSFET 202 falls to approximately 3 volts, turning the MOSFET off. In embodiments a (large) pull-down resistor 210 is connected across the DC power sources(s), to provide a more rapid response to failure of the power supply. As illustrated, conveniently MOSFET 202 is a PMOS device as this facilitates referencing the gate-source voltage of this device to the V_cc line, reducing the voltage across resistor 212 to reduce the gate-source voltage of MOSFET 202 towards zero when the power supply fails.

If only one of the two voltage sources fails, the remaining V_power (V_B) will not be high enough to turn the JFET off. Therefore, the protection should be triggered even when only one voltage source fails. This can be done by choosing a Zener voltage higher than any of the two voltage sources. Note that the triggering signal (the potential on the cathode of the Zener diode 206) should be used to disable the gate driver when a fault in the power supply is detected. Indeed, it is important that the gate driver of the JFET does not force 0 V on the gate-source junction of the JFET at any point when the protection is triggered. This would be the case if the power supply breaks down completely, but it may not be the case if the voltage from the power supply only drops by a few volts. Therefore, the fault detection circuit should preferably also be used to disable the gate driver of the JFET, for example by pulling low an enable signal on the MOSFET driver.

In normal operation MOSFET 202 is always on, and because this is a low voltage device it may have a low on resistance, for example of order 10mQ, and because this MOSFET does not switch in normal operation there are no switching losses. Consider now a fault condition in which MOSFET 202 is turned off. MOSFET 202 has an internal drain-source capacitance and when the switch is off this charges (approximately linearly) towards the pinch-off voltage of JFET 102. The gate-source capacitance of JFET 102 also charges in this way (the source of JFET 102 is connected to the V_Cc line). More particularly, current flows through JFET 102 from the switched power source to which it is connected, for example a DC bus, charging the MOSFET capacitance (and the gate source capacitance) so that the source voltage of JFET 102 rises. Diode D1 214 provides a "return" current path to the gate of JFET 102. Gradually, as the source voltage of JFET 102 rises the gate becomes more and more negative with respect to the source, until JFET 102 is turned off. The process is, effectively, self-limiting in that the gate-source voltage of JFET 102 will continue to increase (the gate voltage becoming more negative) driven by current flowing through JFET 102 from the externally switched power source, until JFET 102 turns itself off. Thus in the event of the failure of batteries/power source 124, 126 the JFET 102 is effectively self-biased off by a combination of the MOSFET capacitance (and internal date-source capacitance) and diode 214, powered by the external power source (if this latter also dies there is no need to turn of JFET 102).

The diode 214 clamps the gate of JFET 102 at the drain voltage of the MOSFET plus the forward drop of the diode. Without the diode, in embodiments the gate of JFET 102 could not be pulled negative under normal operating conditions, and thus the presence of diode 214 enables normal control of JFET 102 absent failure of batteries 124, 126, but provides a current path for self-biasing JFET 102 off in the event of a gate drive power failure. Figure 3 illustrates, schematically, a silicon carbide JFET gate driver circuit 300 incorporating a protection circuit 200 as described with reference to figure 2. Like elements to those previously described are indicated by like reference numerals. The circuit has input/output power switching connections 302a, b, and a gate driver circuit 304, for example as described with reference to figure 1 .

Continuing to refer to Figures 2a and 3 in more detail, when transistor 202 ( Ml ) is off, a voltage V_DSM0SFET starts building up between its drain and source due to the charging of the drain-source capacitance of the MOSFET. This voltage V_DSM0SFET in turn charges the gate-source capacitance of the JFET 102 via the diode 214 ( Dl ). Calling the voltage drop across the diode V_D1 , we have the following relationship:

V * DS, MOSFET + ^τv ' GSJFET = v * Dl

Therefore:

V ^v GS , JFET = V Dl -V ^v DS OSFET

Since V_DSM0SFET increases, there is a point at which V_{DS M0SFET} =

\ +V_Dl . At this moment, we have:

^GS JFET ~ ^ Dl ^_ (I^ Po I ~*~ ^Dl ] Therefore, the JFET turns off. From this moment on, the JFET alone blocks the remaining voltage of the power circuit. Thus, the MOSFET can be a low voltage

MOSFET. It should be able to withstand |V_Po | with a safety margin, so typically, a 50 or 60 V Si MOSFET can be used.

To summarize, when the protection is triggered, the MOSFET turns off and a voltage starts rising across its drain-source junction. When this voltage reaches a certain value, the JFET turns off and blocks the remaining voltage of the power circuit. Since the MOSFET Ml is constantly on (unless there is a problem with the power supply of the gate driver), absent diode 214 ( Dl ), or a similar component the gate of the JFET would be connected to its source (and the JFET could not be turned off). A diode is a cheap and convenient way of addressing this problem but other solutions, for example a transistor, could be used.

Resistor 210 is a pull-down resistor with a large value, to pull down the voltage of the power supply if there is a problem and the output is left floating. In embodiments the triggering signal for the protection is the voltage between the drain and source of the MOSFET 202 ( Ml ). When there is no problem, this voltage is higher than the threshold voltage of the MOSFET but when there is a problem, this voltage falls below the threshold voltage of the MOSFET and it triggers the protection. The potential of the cathode of the Zener diode is therefore the potential for the trigger of the protection. This is preferably also used to trigger an "disable" function of the gate driver, for example to pull down the enable pin of the MOSFET driver. This is desirable because if for any reason the gate driver switches the JFET on while the protection is triggered, the p-MOSFET 122 ( M3 ) in Figures 1 b and 1 c will bypass the MOSFET of the protection circuit and conduct a potentially significant current (via diode 214, Dl ) which could lead to the destruction of these devices. The voltage of the Zener diode may be adapted to the voltage of the power supply.

Referring back to Figures 1 b and 1 c, diodes 132 and 1 14 in Figure 1 b and diodes D3 and D5 in Figure 1 c, are (preferably) included in these circuits because they are to be used with the above-described protection circuit. If no protection circuit was used, i.e. if only the gate driver was used, then these diodes may be omitted. Diode 132 in Figure 1 b (diode D3 in Figure 1 c), is used to stop the speed-up capacitor from slowing down the protection circuit when it is triggered. The skilled person will appreciate, however, that it is not essential for either of these diodes to be included in a gate driver circuit with protection circuit as described, merely desirable. Figure 2b shows what would happen if there were no diode and the protection was triggered. The voltage on the gate-source junction of the JFET increases (in absolute value) because a voltage builds up across the MOSFET in the protection circuit. The power supply is faulty and has been replaced on the schematic by a wire. As the gate- source voltage V_GS becomes more negative, the speed-up capacitor is charged via the body diode of the MOSFET (or even via the channel of the MOSFET if the MOSFET is on). Neglecting the voltage drop across the diode (or the channel), we have: V_speed = VQS, giving the appearance that the gate-source capacitance of the JFET had been increased substantially by putting the speed-up capacitor in parallel. Therefore, the turn-off of the JFET is slower. Putting a diode in series with the speed-up capacitor, with the anode of the diode connected to the gate of the JFET, inhibits V_speed from being negative, i.e. it inhibits the speed-up capacitor from slowing down the protection. The role of the diode 1 14 in Figure 1 b (D5 in Figure 1 c) is different - it only helps lower the reverse voltage the Wilson current mirror would have to block if the diode was not there. Indeed, if there is a fault in the power supply, it can be assumed that the bottom of the Wilson current mirror is connected to the source of the JFET. Therefore, the voltage across the leg of the current mirror which is connected to the gate of the JFET is V_GS. As V_GS goes more negative the reverse voltage that the two bipolar transistors in this leg have to block also increases. Putting a diode in this leg partially helps to block this reverse voltage.

Figure 4 illustrates a silicon carbide JFET gate driver circuit 400 along the lines illustrated in figure 3, showing in detail an example of incorporation of a silicon carbide JFET protection circuit of the type shown in Figure 2 with a silicon carbide gate driver circuit of a type illustrated in Figure 1 b. Again like elements to those previously described are indicated by like reference numerals. The protection circuit 200 is indicated by a dashed line. In the illustrated embodiment the protection circuit also includes an indicator to indicate the presence/absence of a gate driver power supply. As illustrated this is a visual indicator, more particularly an LED 402 in combination with a large value series resistor 404 (for reduced power consumption). Optionally the turn off signal on line 208 and/or the zener voltage V_z may be employed to trigger an "enable" (disable) signal on the MOSFET driver 120. Preferably diodes 214 and 132 are fast switching diodes. On Figure 4, V_power is reduced to a lower voltage and comprises only only one voltage source. This could be used if the gate-source avalanche breakdown voltage of the JFET is reduced (e.g. if |V_X| < 22V, V_power can be 24V; if |V_X| < 13V, V_power can be 15V). In this particular case, it might not be necessary to disable the gate driver when a fault in the power supply is detected, as the gate driver would stop working on its own if its power supply fails. Note that if the voltage source is 24V, care should be taken to ensure the MOSFET driver can handle this voltage, but also the MOSFETs 136, 128 and 122. The gate driver on Figure 4 is probably more suited to newer versions of the SIC JFETs.

Thus, broadly speaking, one preferred protection circuit for a normally-on silicon carbide JFET comprises a first power switching connection coupled to a drain of the JFET; a gate driver circuit; and a normally-off MOSFET connected in series between the source of the SiC JFET and a second power switching connection. The circuit includes a diode having an anode coupled to the gate of the SiC JFET and a cathode coupled between a second power switching connection and a source/drain connection of the MOSFET. A control circuit is coupled to the gate of the MOSFET to sense a failure of a power supply to the gate driver circuit and to switch off the MOSFET in response, for example using a bias circuit powered from the gate driver power supply. When the MOSFET is off the external (switched) power maintains the gate of the JFET negative with respect to the source, via a circuit including the internal capacitance of the off MOSFET and the diode. Embodiments of the circuits we describe provide a fast and effective way of protecting permanently a normally-on transistor such as the SiC JFET. This protection is resettable and does not add greatly to the complexity of the circuit; nor does it add any significant losses. Although we have described an example of a protection circuit which is used in association with a normally-on transistor. However, the protection circuit may also be used with so-called quasi normally-off transistors. These transistors can block only a fraction of their rated voltage when there is no bias on their gate-source junction. The protection circuits we describe may also be employed to protect this type of device. Similarly, a degree of protection can be achieved by turning the MOSFET only partially off.

The gate drivers described here use a current source to turn the JFET off. However the skilled person will appreciate that a gate driver could be made which uses a voltage to turn off the JFET. The protection technique described here would still work with such a circuit.

In embodiments a gate driver circuit as the above described may be configured to apply a small positive voltage to the gate of the SiC JFET gate to reduce its on-state resistance: The JFET is a normally-on semiconductor device - when zero volts is applied between the gate and the source, the device conducts (its rated current is usually calculated at this operating point). To switch the device off, a negative gate- source voltage is employed and, unlike a MOSFET device, the gate of a JFET behaves as a diode which has either zero or negative bias under these normal operating conditions. Because Silicon Carbide is a wide-bandgap semiconductor, the forward voltage of this diode (at which it starts to conduct significant current) is in the region of 2.5 to 3V. Thus a positive gate-source voltage up to around 2-2.5V can be safely applied to the gate without the SiC JFET starting to conduct significant current: Applying a positive gate-source voltage causes the conductive channel in the JFET to widen further than it would with zero bias, and this reduces the effective on-state resistance of the device compared to a device with a zero gate-source voltage. Thus it is advantageous to provide a gate driver that applies a small positive voltage to the gate during turn-on, to give better on-state performance. In theory a higher maximum current might also be obtained, but in practice this likely to be limited by other effects, such as bond wire current handling capability.

One implementation of this concept employs a floating isolated power supply ranging between ~+2V and a negative voltage required to turn off the JFET, referenced to the source of the JFET (OV). The circuit is configured such that on turn on the gate of the JFET is clamped to the positive rail.

Other additions/variations to the above described gate driver designs are also possible. For example a gate current source may be employed to hold the JFET gate diode at the point of forward conduction. Additionally or alternatively clamping diodes may be provided on the input to limit voltage spikes, for example from an inductive gate drive.

No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAIMS:

1 . A silicon carbide power semiconductor switching circuit, the circuit comprising: first and second power switching connections; a silicon carbide (SiC) junction field effect transistor (JFET) comprising a drain, a source and a gate terminal, wherein said first power switching connection is coupled to said drain connection of said SiC JFET; a gate driver circuit having a control input to control switching of said SiC JFET and a gate drive output connected to said gate terminal of said SiC JFET; a series-protection semiconductor switching device having first and second switched connections and a control connection to control switching of said semiconductor switching device, wherein said semiconductor switching device is connected in series between said source terminal of said SiC JFET and said second power switching connection via said switched connections of said semiconductor switching device; a diode having an anode coupled to said gate terminal of said SiC JFET and a cathode coupled to a junction between said second power switching connection and a said switched connection of said semiconductor switching device; and a control circuit coupled to said control connection of said semiconductor switching device to sense a fault condition and to control said semiconductor switching device to switch off responsive to said sensed fault condition.

2. A silicon carbide power semiconductor switching circuit as claimed in claim 1 further comprising first and second power supply rails to power said gate driver circuit, and wherein said control circuit is configured to sense a voltage on a said power supply rail and to control said semiconductor switching device to switch off responsive to said sensed voltage falling below a threshold value.

3. A silicon carbide power semiconductor switching circuit as claimed in claim 2 wherein said control circuit comprises a zener diode coupled in series with a resistance across said power supply rails and has an output from a connection between said zener diode and said resistance to control said semiconductor switching device.

4. A silicon carbide power semiconductor switching circuit as claimed in claim 2 or 3 further comprising a pull-down resistance coupled between said power supply rails.

5. A silicon carbide power semiconductor switching circuit as claimed in any preceding claim wherein said semiconductor switching device comprises a normally-off

MOSFET, wherein said first and second switched connections and said control connection of said semiconductor switching device comprise, respectively, source, drain and gate connections of said MOSFET, and wherein said control circuit comprises a bias circuit to bias said MOSFET on in the absence of said fault condition.

6. A silicon carbide power semiconductor switching circuit as claimed in claim 6 wherein said MOSFET is a PMOS MOSFET, and wherein said source connection of said PMOS MOSFET is connected to said source terminal of said SiC JFET.

7. A silicon carbide power semiconductor switching circuit as claimed in any preceding claim wherein, when said semiconductor switching device is off, a capacitance between said switched connections of said semiconductor switching device charges, via current from said source terminal of said JFET, such that a voltage on said source terminal becomes greater than a voltage on said gate terminal of said JFET to turn said JFET off.

8. A silicon carbide power semiconductor switching circuit as claimed in any preceding claim wherein said gate driver circuit comprises a constant current source to maintain a gate potential of said JFET at substantially a point of avalanche breakdown of a gate source junction of said JFET when said JFET is off.

9. A silicon carbide power semiconductor switching circuit as claimed in claim 8 wherein said gate driver circuit further comprises a speed-up capacitor connected in series with a first controllable switch, wherein said speed-up capacitor is coupled to said gate terminal of said JFET; and a second controllable switch coupled across said gate and source terminals of said JFET; and wherein said first and second controllable switches are controlled such that each one is on when the other is off, to charge said speed-up capacitor with a turn-off voltage for applying to said gate terminal of said JFET when said JFET is turned off.

10. A silicon carbide power semiconductor switching circuit as claimed in claim 9 wherein said first and second controllable switches are controlled such that said first controllable switch is pulsed on for a period then off when said second controllable switch is turned off.

1 1 . A silicon carbide power semiconductor switching circuit as claimed in any preceding claim wherein said diode is replaced by a further switching device having a first switched terminal coupled to said gate terminal of said SiC JFET and a second switched terminal coupled to said junction between said second power switching connection and said switched connection of said semiconductor switching device; wherein said further switching device is controlled to disconnect said gate terminal of said JFET from said source terminal of said JFET when said series-protection semiconductor switching device is on.

12. A method of protecting a silicon carbide (SiC) junction field effect transistor (JFET), the method comprising: connecting a normally-off semiconductor switch in series with said JFET such that a switched connection of said semiconductor switch is connected to a source terminal of said JFET; providing power to a drain terminal of said JFET; driving a gate terminal of said JFET to control a flow of said power from said drain terminal through said series-connected JFET and semiconductor switch; biasing said semiconductor switch on to provide a current path from said source terminal of said JFET; and arranging for said biasing to be removed on detection of a fault, such that on removal of said biasing said semiconductor switch reverts to a normally-off state and a voltage on said source terminal of said JFET rises to reverse bias a gate-source junction of said JFET to drive said JFET off.

13. A method as claimed in claim 12 comprising providing a current path from said source terminal to said gate terminal via a capacitance of said semiconductor switch in said normally-off state and a diode; and configuring said diode to block a negative voltage applied to said gate terminal.

14. A method as claimed in claim 12 or 13 wherein said arranging for said biasing to be removed on detection of a fault comprises biasing said semiconductor switch on from a power supply to a circuit driving said gate terminal.

15. A circuit protecting a silicon carbide (SiC) junction field effect transistor (JFET), the circuit comprising: a normally-off semiconductor switch connected in series with said JFET such that a switched connection of said semiconductor switch is connected to a source terminal of said JFET; a connection to a drain terminal of said JFET to receive power for switching; a gate driver for driving a gate terminal of said JFET to control a flow of said power from said drain terminal through said JFET and said semiconductor switch; a bias circuit to bias said semiconductor switch on to provide a current path to said source connection, wherein said bias circuit is configured to remove said bias on detection of a fault such that on removal of said biasing said semiconductor switch reverts to a normally-off state and a voltage on said source terminal rises to reverse bias a gate-source junction of said JFET to drive said JFET off.

16. A method of protecting a silicon carbide JFET, the method comprising: connecting a normally-off silicon MOSFET in series with said silicon carbide JFET such that a source terminal of said JFET is connected to a source/drain terminal of said MOSFET; biasing said MOSFET on; and switching said MOSFET off by removing said biasing, on detection of a fault.

17. A circuit or method as recited in any preceding claim wherein said silicon carbide junction field effect transistor is a normally-on silicon carbide junction field effect transistor.

18. A method of protecting a power semiconductor switching device, the method comprising: connecting a normally-off MOSFET in series with said power semiconductor switching device; biasing said MOSFET on; sensing a voltage across said MOSFET; and removing said biasing on said MOSFET to allow said MOSFET to switch off on detection that said voltage across said MOSFET is greater than a threshold value.

19. A circuit for protecting a power semiconductor switching device, the circuit comprising: a normally-off MOSFET connected in series with said power semiconductor switching device; a bias circuit for biasing said MOSFET on; a circuit for sensing a voltage across said MOSFET; and a system for removing said biasing on said MOSFET, to allow said MOSFET to switch off, on detection that said voltage across said MOSFET is greater than a threshold value.

20. A gate driver for a silicon carbide junction field effect transistor (JFET) comprising: a gate drive output for driving a gate terminal of said silicon carbide JFET; a constant current source to maintain a gate potential of said JFET at substantially a point of avalanche breakdown of a gate source junction of said JFET when said JFET is off; a speed-up capacitor connected in series with a first controllable switch, wherein said speed-up capacitor is coupled between said gate terminal of said JFET and a power rail via said first controllable switch; and a second controllable switch coupled across said gate and source terminals of said JFET; wherein said first and second controllable switches are controlled such that each one is on when the other is off, to charge said speed-up capacitor with a turn-off voltage for applying to said gate terminal of said JFET when said JFET is turned off; and wherein said first and second controllable switches are controlled said that said first controllable switch is pulsed on for a period then off when said second controllable switch is turned off.