WO2020125669A1 - Analog switch circuit and charge pump circuit - Google Patents

Abstract

Disclosed is an analog switch circuit, comprising a switch tube (Q), a control circuit (100), a first pull-down circuit (300), and a charge pump circuit (200). When an enable signal (PD) is a turn-off signal, the potential at a second terminal of the first pull-down circuit (300) is a ground level, and the potential at the output terminal of the control circuit (100) is a lower value between the ground level and the voltage value of a signal received by the input terminal of an analog switch, and the potential at a first output terminal of the charge pump circuit (200) is pulled down to a lower value to turn off the switch tube (Q); when the enable signal (PD) is a turn-on signal, the potential at the output terminal of the control circuit (100) is equal to the voltage value of the signal received by the input terminal of the analog switch, the charge pump circuit (200) works normally, and the potential at the first output terminal is equal to the sum of the voltage value of the signal received at the input terminal of the analog switch and a preset voltage, the switch (Q) is then turned on. A negative voltage signal can be conducted without a Zener diode (Z), thereby avoiding the problem of high process requirements in the prior art.

Description

Analog switch circuit and charge pump circuit

This application claims the priority of the Chinese patent application filed on December 20, 2018, with the application number 201811561655.0 and the invention titled "an analog switch circuit", the entire contents of which are incorporated by reference in this application.

Technical field

The invention relates to the technical field of power electronics, in particular to an analog switch circuit and a charge pump circuit.

Background technique

The analog switch is used to conduct the signal received at the input to the output. In general, it is mainly used to conduct positive voltage signals. However, in some application scenarios, such as audio application scenarios, the analog switch needs to support the input of negative voltage signals.

Figure 1 shows an analog switch circuit structure that supports negative voltage signal input, where M1 is an analog switch tube. The specific principle is: the booster circuit generates a high voltage, and the current source I is used to bias the Zener diode Z; when the analog switch is in the open state, due to the breakdown voltage regulation effect of the Zener diode Z, the analog switch tube M1 The voltage difference between the gate G and the source S is stabilized at the voltage regulation value of the Zener diode Z, thereby opening the analog switch and conducting the signal received at the input terminal VIN to the output terminal VOUT.

Although the circuit shown in FIG. 1 can realize the conduction of a negative voltage signal, based on design cost and process considerations, the Zener diode is not necessarily a design element that can be equipped, that is, the existing analog switch design The requirements are too high.

Summary of the invention

In view of this, the present invention provides an analog switch circuit and a charge pump circuit to solve the problem of high process requirements in the prior art.

To achieve the above purpose, the technical solutions provided by this application are as follows:

An analog switch circuit includes: a switch tube, a control circuit, a first pull-down circuit and a charge pump circuit; wherein:

The control terminal of the charge pump circuit and the control terminal of the first pull-down circuit both receive the enable signal;

The second end of the first pull-down circuit is grounded;

The first end of the first pull-down circuit, the first input end of the control circuit, and the first end of the switch tube are all connected to the output end of the analog switch circuit;

The second input terminal of the control circuit and the second terminal of the switch tube are connected to the input terminal of the analog switch circuit;

The output terminal of the control circuit, and, the third terminal of the switch tube are connected to the input terminal of the charge pump circuit;

The first output terminal of the charge pump circuit is connected to the control terminal of the control circuit and the control terminal of the switch tube;

The switch tube is a switch tube which is turned on when the control terminal potential is higher than the second terminal potential.

Optionally, when the enable signal is an off signal, the second terminal potential of the first pull-down circuit is a ground level, and the output terminal potential of the control circuit is a ground level and the analog switch The input of the input receives a lower value between the voltage values of the signal, pulls down the potential of the first output of the charge pump circuit to the lower value, and turns off the switch; and/or,

When the enable signal is a turn-on signal, the output terminal potential of the control circuit is equal to the voltage value of the received signal at the input terminal of the analog switch circuit, the charge pump circuit works normally and the first output terminal potential is equal to the The input terminal of the analog switch receives the sum of the voltage value of the signal and the preset voltage to turn on the switch.

Optionally, the switch tube is a first NMOS transistor;

The gate of the first NMOS transistor is the control end of the switch tube;

The drain of the first NMOS transistor is the first end of the switch tube;

The source of the first NMOS transistor is the second end of the switch tube;

The substrate of the first NMOS transistor is the third end of the switch tube.

Optionally, the first pull-down circuit includes: a second NMOS transistor;

The gate of the second NMOS transistor is the control end of the first pull-down circuit;

The drain of the second NMOS transistor is the first end of the first pull-down circuit;

The source of the second NMOS transistor is the second end of the first pull-down circuit;

The substrate of the second NMOS transistor is connected to the second output terminal of the charge pump circuit.

Optionally, the control circuit includes: a first low voltage selection circuit and a connection circuit; wherein:

The control end of the connection circuit is the control end of the control circuit;

The first input terminal of the first low voltage selection circuit is connected to the first input terminal of the connection circuit, and the connection point is the first input terminal of the control circuit;

The second input terminal of the first low voltage selection circuit is connected to the second input terminal of the connection circuit, and the connection point is the second input terminal of the control circuit;

The output terminal of the first low voltage selection circuit is connected to the third terminal of the connection circuit, and the connection point is the output terminal of the control circuit.

Optionally, the connection circuit includes: a third NMOS transistor and a fourth NMOS transistor;

The drain of the third NMOS transistor is the second input end of the connection circuit;

The drain of the fourth NMOS transistor is the first input end of the connection circuit;

The source and the substrate of the third NMOS transistor, and the source and the substrate of the fourth NMOS transistor are all connected and the connection point is the third end of the connection circuit;

The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the connection point is the control end of the connection circuit.

Optionally, the first low voltage selection circuit includes: a fifth NMOS transistor and a sixth NMOS transistor;

The drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the connection point is the second input terminal of the first low voltage selection circuit;

The gate of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the connection point is the first input terminal of the first low voltage selection circuit;

The source and the substrate of the fifth NMOS transistor, and the source and the substrate of the sixth NMOS transistor are connected and the connection point is the output end of the first low voltage selection circuit.

Optionally, the charge pump circuit includes: a generating circuit, a second low voltage selection circuit, and a second pull-down circuit; wherein:

The input terminal of the generating circuit is connected to the first input terminal of the second low voltage selection circuit, and the connection point is the input terminal of the charge pump circuit;

The output terminal of the generating circuit is connected to the first terminal of the second pull-down circuit, and the connection point is the first output terminal of the charge pump circuit;

Two power supply terminals of the generating circuit are respectively connected to two inverted clocks, and the driving voltage of the two inverted clocks is the preset voltage;

The second input terminal of the second low voltage selection circuit is grounded;

The output terminal of the second low voltage selection circuit is connected to the second terminal of the second pull-down circuit;

The control terminal of the second pull-down circuit is the control terminal of the charge pump circuit.

Optionally, the generating circuit includes: a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and first and second capacitors having the same capacitance value;

The source and substrate of the seventh NMOS transistor, and the source and substrate of the eighth NMOS transistor are connected and the connection point is the input end of the generating circuit;

The drain of the seventh NMOS transistor, the gate of the eighth NMOS transistor, one end of the first capacitor, the source of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected The point is the first charging point;

The drain of the eighth NMOS transistor, the gate of the seventh NMOS transistor, one end of the second capacitor, the source of the second PMOS transistor and the gate of the first PMOS transistor are connected and connected Point is the second charging point;

The other end of the first capacitor is connected to an inverted clock, and the other end of the second capacitor is connected to another inverted clock;

The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the connection point is the output end of the generating circuit.

Optionally, both the seventh NMOS transistor and the eighth NMOS transistor are NMOS transistors with DNW isolation.

Optionally, the second pull-down circuit includes: an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor;

The drain of the eleventh NMOS transistor is connected to the first charging point;

The drain of the twelfth NMOS transistor is connected to the second charging point;

The drain of the thirteenth NMOS transistor is the first end of the second pull-down circuit;

The source and substrate of the eleventh NMOS transistor, the source and substrate of the twelfth NMOS transistor, and the source and substrate of the thirteenth NMOS transistor are connected, and the connection point is the The second end of the second pull-down circuit;

The gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor are connected, and the connection point is the control terminal of the second pull-down circuit.

Optionally, the charge pump circuit further includes: a high voltage selection circuit;

The first input terminal of the high voltage selection circuit is connected to the output terminal of the generation circuit;

The second input terminal of the high voltage selection circuit is grounded;

The output terminal of the high voltage selection circuit is connected to the substrate of the first PMOS transistor and the substrate of the second PMOS transistor.

Optionally, the high voltage selection circuit includes: a third PMOS transistor and a fourth PMOS transistor;

The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the connection point is the first input terminal of the high voltage selection circuit;

The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the connection point is the second input terminal of the high voltage selection circuit;

The source and the substrate of the third PMOS transistor, and the source and the substrate of the fourth PMOS transistor are all connected and the connection point is the output end of the high voltage selection circuit.

Optionally, the second low voltage selection circuit includes: a ninth NMOS transistor and a tenth NMOS transistor;

The drain of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the connection point is the first input terminal of the second low voltage selection circuit;

The gate of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the connection point is the second input terminal of the second low voltage selection circuit;

The source and the substrate of the ninth NMOS transistor, and the source and the substrate of the tenth NMOS transistor are connected and the connection point is the output end of the second low voltage selection circuit.

The invention also provides a charge pump circuit, including: a generating circuit, a second low voltage selection circuit and a second pull-down circuit; wherein:

The input terminal of the generating circuit is connected to the first input terminal of the second low voltage selection circuit, and the connection point is the input terminal of the charge pump circuit;

The output terminal of the generating circuit is connected to the first terminal of the second pull-down circuit, and the connection point is the first output terminal of the charge pump circuit;

Two power supply terminals of the generating circuit are respectively connected to two inverted clocks, and the driving voltages of the two inverted clocks are preset voltages;

The second input terminal of the second low voltage selection circuit is grounded;

The output terminal of the second low voltage selection circuit is connected to the second terminal of the second pull-down circuit;

The control terminal of the second pull-down circuit is the control terminal of the charge pump circuit.

Optionally, the generating circuit includes: a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and first and second capacitors having the same capacitance value;

The source and substrate of the seventh NMOS transistor, and the source and substrate of the eighth NMOS transistor are connected and the connection point is the input end of the generating circuit;

The drain of the seventh NMOS transistor, the gate of the eighth NMOS transistor, one end of the first capacitor, the source of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected The point is the first charging point;

The drain of the eighth NMOS transistor, the gate of the seventh NMOS transistor, one end of the second capacitor, the source of the second PMOS transistor and the gate of the first PMOS transistor are connected and connected Point is the second charging point;

The other end of the first capacitor is connected to an inverted clock, and the other end of the second capacitor is connected to another inverted clock;

The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the connection point is the output end of the generating circuit.

Optionally, both the seventh NMOS transistor and the eighth NMOS transistor are NMOS transistors with DNW isolation.

Optionally, the second pull-down circuit includes: an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor;

The drain of the eleventh NMOS transistor is connected to the first charging point;

The drain of the twelfth NMOS transistor is connected to the second charging point;

The drain of the thirteenth NMOS transistor is the first end of the second pull-down circuit;

The source and substrate of the eleventh NMOS transistor, the source and substrate of the twelfth NMOS transistor, and the source and substrate of the thirteenth NMOS transistor are connected, and the connection point is the The second end of the second pull-down circuit;

The gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor are connected, and the connection point is the control terminal of the second pull-down circuit.

Optionally, it also includes: a high voltage selection circuit;

The first input terminal of the high voltage selection circuit is connected to the output terminal of the generation circuit;

The second input terminal of the high voltage selection circuit is grounded;

The output terminal of the high voltage selection circuit is connected to the substrate of the first PMOS transistor and the substrate of the second PMOS transistor.

Optionally, the high voltage selection circuit includes: a third PMOS transistor and a fourth PMOS transistor;

The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the connection point is the first input terminal of the high voltage selection circuit;

The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the connection point is the second input terminal of the high voltage selection circuit;

The source and the substrate of the third PMOS transistor, and the source and the substrate of the fourth PMOS transistor are all connected and the connection point is the output end of the high voltage selection circuit.

Optionally, the second low voltage selection circuit includes: a ninth NMOS transistor and a tenth NMOS transistor;

The drain of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the connection point is the first input terminal of the second low voltage selection circuit;

The gate of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the connection point is the second input terminal of the second low voltage selection circuit;

The source and the substrate of the ninth NMOS transistor, and the source and the substrate of the tenth NMOS transistor are connected and the connection point is the output end of the second low voltage selection circuit.

In the analog switch circuit provided by the present invention, when the enable signal is an on signal, the potential of the output terminal of the control circuit is equal to the input voltage of the input terminal of the analog switch circuit, so that the charge pump circuit can work normally. And the potential of the first output terminal of the charge pump circuit during normal operation is equal to the sum of the input voltage and the preset voltage of the input terminal of the analog switch circuit; and because the first output terminal of the charge pump circuit and the switch tube The control terminal is connected, and the second terminal of the switch tube is connected to the input terminal of the analog switch. Therefore, when the enable signal is an on signal, the potential of the control terminal of the switch tube is higher than the potential of the second terminal. When the tube is turned on, the signal conduction function can be realized. Moreover, since the control terminal potential of the switch is equal to the sum of the second terminal potential and the preset voltage, even if the input voltage of the input terminal of the analog switch circuit is a negative voltage, by setting the preset voltage, it is possible to Ensure that the control terminal potential of the switch is higher than the second terminal potential, that is, the switch can be turned on to achieve signal transmission. The analog switch circuit provided by the present invention can realize the conduction of a negative voltage signal without a Zener diode, and avoids the problem of high technological requirements in the prior art.

BRIEF DESCRIPTION

1 is a schematic diagram of an analog switch circuit provided by the prior art;

2 is a schematic diagram of an analog switch circuit disclosed in an embodiment of the present invention;

3 is a schematic diagram of an analog switch circuit disclosed in another embodiment of the present invention;

4 is a schematic diagram of an analog switch circuit disclosed in another embodiment of the present invention;

5 is a schematic diagram of an analog switch circuit disclosed in another embodiment of the present invention;

6 is a schematic diagram of a charge pump circuit in an analog switch circuit disclosed in an embodiment of the present invention;

7 is a simplified schematic diagram of a charge pump circuit in an analog switch circuit disclosed in an embodiment of the present invention;

8 is a schematic diagram of a charge pump circuit in an analog switch circuit disclosed by another embodiment of the present invention;

9 is a schematic diagram of a charge pump circuit in an analog switch circuit disclosed by another embodiment of the present invention;

10 is a schematic diagram of a charge pump circuit in an analog switch circuit disclosed by another embodiment of the present invention.

detailed description

In order to further understand the present invention, the following describes preferred embodiments of the present invention with reference to examples, but it should be understood that these descriptions are only to further illustrate the features and advantages of the present invention, not to limit the claims of the present invention.

The present invention provides an analog switch circuit to solve the problem of high technological requirements in the prior art.

Referring to FIG. 2, the analog switch circuit includes: a switch Q, a control circuit 100, a first pull-down circuit 300, and a charge pump circuit 200; wherein:

The control terminal of the charge pump circuit 200 and the control terminal of the first pull-down circuit 300 both receive the enable signal PD; the second terminal of the first pull-down circuit 300 is grounded.

The first terminal of the first pull-down circuit 300, the first input terminal of the control circuit 100, and the first terminal of the switch Q are all connected to the output terminal of the analog switch circuit.

The second input terminal of the control circuit 100 and the second terminal of the switch Q are connected to the input terminal of the analog switch circuit.

The output terminal of the control circuit 100 and the third terminal of the switch Q are connected to an input terminal of the charge pump circuit 200; the first output terminal of the charge pump circuit 200 is connected to the control terminal of the control circuit 100 and the switch Q The control terminal is connected.

It should be noted that the switch tube Q is a switch tube that is turned on when the control terminal potential is higher than the second terminal potential.

It should also be noted that, since the control circuit 100 is connected to the charge pump circuit 200 and the first pull-down circuit 300 respectively, the state of the enable signal PD will affect the charge pump circuit 200 and the first pull-down circuit 300, which will affect the control The circuit 100 functions. When the enable signal PD is a turn-off signal, the control circuit 100 uses the signal with a lower potential between the signal received at its first input and the signal received at the second input as its output signal PW; When the enable signal PD is an on signal, the potential of the signal PW at the output of the control circuit 100 is equal to the potential of the input signal at the input of the analog switch circuit.

The specific working principle is:

When the enable signal PD is an off signal, the potential of the signal PD received by the control terminal of the first pull-down circuit 300 is high level, and the potential of the second terminal of the first pull-down circuit 300 is ground level GND; The potential of the control terminal of the first pull-down circuit 300 is greater than the potential of the second terminal of the first pull-down circuit 300, so the first pull-down circuit 300 is turned on to pull down the potential of the output terminal of the analog switch circuit to the ground level GND.

Because the enable signal PD is an off signal, the potential of the signal PW at the output of the control circuit 100 is the input voltage VIN at the input of the analog switch circuit and the output voltage VOUT at the output (at this time, VOUT and ground level GND are equal) The lower value between them, namely PW=min(VIN, GND), so the potential of the signal G at the first output terminal of the charge pump circuit 200 is pulled down to the input voltage VIN and ground level GND of the input terminal of the analog switch circuit The lower value between G = min (VIN, GND); no matter whether the input voltage VIN at the input of the analog switch circuit is a positive voltage or a negative voltage, the switch Q will be turned off, thereby making the The analog switch circuit is completely turned off.

When the enable signal PD is an on signal, the potential of the signal PW at the output of the control circuit 100 is equal to the input voltage VIN at the output of the analog switch circuit, that is, PW=VIN, the charge pump circuit 200 works normally, and the charge pump circuit The potential of the signal G at the first output of 200 is equal to the sum of the potential of the signal PW at the output of the control circuit 100 and the preset voltage VDD, that is, G=PW+VDD, so the potential of the signal G at the first output of the charge pump circuit 200 It is equal to the sum of the input voltage VIN at the input end of the analog switch circuit and the preset voltage VDD, that is, G=VIN+VDD.

Because the potential of the signal G received by the control terminal of the switch Q is equal to the potential of the signal G of the first output terminal of the charge pump circuit 200, therefore when G=VIN+VDD, the potential of the control terminal of the switch Q is also equal to the analog switch circuit The input voltage VIN and the preset voltage VDD at the input of the switch, so the switch Q is turned on and can conduct signals.

In the analog switch circuit provided by the present invention, when the enable signal PD is an on signal, the potential of the output terminal of the control circuit 100 is equal to the input voltage VIN at the input terminal of the analog switch circuit, so that the charge pump circuit 200 can work normally and the charge During normal operation of the pump circuit 200, the potential of the first output terminal is equal to the sum of the input voltage VIN and the preset voltage VDD of the input terminal of the analog switch circuit; and due to the control of the first output terminal of the charge pump circuit 200 and the switch Q The terminal is connected, and the second end of the switch tube Q is connected to the input terminal of the analog switch. Therefore, when the enable signal PD is a turn-on signal, the control terminal potential of the switch tube Q is higher than the second terminal potential, and the switch tube Q is turned on , Can realize the signal conduction function. Moreover, since the control terminal potential of the switch Q is equal to the sum of the second terminal potential and the preset voltage VDD, even if the input voltage VIN at the input end of the analog switch circuit is a negative voltage, by setting the preset voltage VDD, It can also ensure that the control terminal potential of the switching tube Q is higher than the second terminal potential, that is, the switching tube Q can be turned on to realize signal transmission. The analog switch circuit provided by the present invention can realize the conduction of a negative voltage signal without a Zener diode, and avoids the problem of high technological requirements in the prior art.

Optionally, as shown in FIG. 3, in another embodiment of the present invention, an implementation of the switching transistor Q includes: a first NMOS transistor M1; where:

The gate of the first NMOS transistor M1 is the control end of the switch Q; the drain D of the first NMOS transistor M1 is the first end of the switch Q; the source S of the first NMOS transistor M1 is the second end of the switch Q ; The substrate of the first NMOS transistor M1 is the third end of the switch Q.

When the potential of the signal received by the gate of the first NMOS transistor M1 is greater than the potential received by the source S of the first NMOS transistor M1, the first NMOS transistor M1 is turned on.

Optionally, as shown in FIG. 3, an embodiment of the first pull-down circuit 300 includes: a second NMOS transistor M2; wherein:

The gate of the second NMOS transistor M2 is the control terminal of the first pull-down circuit 300; the drain of the second NMOS transistor M2 is the first terminal of the first pull-down circuit 300; the source of the second NMOS transistor M2 is the first pull-down circuit The second terminal of 300; the substrate of the second NMOS transistor M2 is connected to the second output terminal of the charge pump circuit 200.

When the potential of the signal received by the gate of the second NMOS transistor M2 is greater than the potential received by the source of the second NMOS transistor M2, the second NMOS transistor M2 is turned on.

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

Optionally, as shown in FIG. 4, in another embodiment of the present invention, an implementation manner of the control circuit 100 includes: a first low voltage selection circuit 101 and a connection circuit 102; wherein:

The control terminal of the connection circuit 102 is the control terminal of the control circuit 100.

The first input terminal of the first low voltage selection circuit 101 is connected to the first input terminal of the connection circuit 102, and the connection point is the first input terminal of the control circuit 100; the second input terminal of the first low voltage selection circuit 101 is connected to the connection circuit The second input terminal of 102 is connected, and the connection point is the second input terminal of the control circuit 100.

The output terminal of the first low voltage selection circuit 101 is connected to the third terminal of the connection circuit 102, and the connection point is the output terminal of the control circuit 100.

It should be noted that when the first low-voltage selection circuit 101 is in operation, its specific function is to use a signal with a lower potential between the signal received at its first input terminal and the signal received at its second input terminal as its The signal at the output.

The specific working principle is:

When the enable signal PD is an off signal, the potential of the output terminal of the analog switch circuit is pulled down to the ground level GND by the second NMOS transistor. At this time, the potential of the first input terminal of the control circuit 100 and the first low voltage The potential of the first input terminal of the selection circuit 101 is also the ground level GND.

Since the potential of the first input terminal of the first low voltage selection circuit 101 is the ground level GND, and the potential of the second input terminal of the low voltage selection circuit 101 is the input voltage VIN of the input terminal of the analog switch circuit, the first low voltage selection circuit 101 selects A signal with a lower potential between the input voltage VIN of the input terminal of the analog switch circuit and the ground level GND is used as the signal of its output terminal, and the signal PW of the output terminal of the first low voltage selection circuit 101, that is, PW=min(VIN, GND) .

When the enable signal PD is a turn-on signal, the substrate potential of the first NMOS transistor M1 is PW=VIN+1/2Vds. Since the on-resistance of the analog switch is small, the voltage between the source and drain of the first NMOS transistor M1 is The difference Vds is small, so that when the input voltage VIN at the input end of the analog switch circuit is a positive voltage, the substrate potential PW of the first NMOS transistor M1 is slightly larger than the input voltage VIN at the input end of the analog switch circuit; When the input voltage VIN at the input terminal of the analog switch circuit is a negative voltage, the substrate potential PW of the first NMOS transistor M1 is slightly smaller than the input voltage VIN at the input terminal of the analog switch circuit. Since the voltage difference Vds between the source and drain of the first NMOS transistor M1 is very small and can be ignored, it can be regarded as that the substrate voltage PW is approximately equal to the input voltage VIN of the input terminal of the analog switch circuit during the circuit driving process. At this time, the charge pump circuit 200 works normally, the potential of the control terminal of the first NMOS transistor M1, and the signal G received by the control terminal of the connection circuit 102 are equal to the input voltage VIN and the pre-voltage of the input terminal of the analog switch circuit Let the sum of the voltage VDD be G=VIN+VDD.

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

Optionally, as shown in FIG. 5, in another embodiment of the present invention, an implementation of the connection circuit 102 includes: a third NMOS transistor M3 and a fourth NMOS transistor M4; where:

The drain of the third NMOS transistor M3 is the second input terminal of the connection circuit 102;

The drain of the fourth NMOS transistor M4 is the first input terminal of the connection circuit 102;

The source and substrate of the third NMOS transistor M3, and the source and substrate of the fourth NMOS transistor M4 are all connected and the connection point is the third end of the connection circuit 102;

The gate of the third NMOS transistor M3 is connected to the gate of the fourth NMOS transistor M4, and the connection point is the control terminal of the connection circuit 102.

The specific working principle is:

When the charge pump circuit 200 operates normally, the signal G received by the gates of the first NMOS transistor M1, the third NMOS transistor M3, and the fourth NMOS transistor M4 is equal to the input voltage VIN and the preset voltage VDD of the input terminal of the analog switch circuit The sum, that is, G=VIN+VDD; and the potentials of the source of the first NMOS transistor M1 and the drain of the third NMOS transistor M3 are the input voltage VIN of the input terminal of the analog switch circuit, so the first NMOS transistor M1 And the third NMOS transistor M3 is turned on.

Moreover, after the first NMOS transistor M1 is turned on, the potential of the input terminal of the analog switch circuit is the same as the potential of the output terminal, and the potential of the drain of the fourth NMOS transistor M4 is the input voltage VIN of the input terminal of the analog switch circuit. The signal G received by the gate of the fourth switch NMOS transistor M4 is equal to the sum of the input voltage VIN of the input terminal of the analog switch circuit and the preset voltage VDD, that is, G=VIN+VDD, so the fourth NMOS transistor M4 is turned on .

In summary, when the charge pump circuit 200 operates normally, the first NMOS transistor M1, the third NMOS transistor M3, and the fourth NMOS transistor M4 are all turned on, and the source, drain, and substrate potentials of the first NMOS transistor M1 the same.

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

Optionally, as shown in FIG. 5, in another embodiment of the present invention, an implementation manner of the first low-voltage selection circuit 101 includes: a fifth NMOS transistor M5 and a sixth NMOS transistor M6; where:

The drain of the fifth NMOS transistor M5 is connected to the gate of the sixth NMOS transistor M6, and the connection point is the second input terminal of the first low voltage selection circuit 101.

The gate of the fifth NMOS transistor M5 is connected to the drain of the sixth NMOS transistor M6, and the connection point is the first input terminal of the first low voltage selection circuit 101.

The source and substrate of the fifth NMOS transistor M5 and the source and substrate of the sixth NMOS transistor M6 are connected and the connection point is the output of the first low voltage selection circuit 101.

The specific working principle is:

When the potential of the first input terminal of the first low voltage selection circuit 101 is less than the potential of the second input terminal of the first low voltage selection circuit 101, because the potential of the gate of the sixth NMOS transistor M6 is the second input of the first low voltage selection circuit 101 Potential of the terminal, and the potential of the drain of the sixth NMOS transistor M6 is the potential of the first input terminal of the first low voltage selection circuit 101, so the potential of the gate of the sixth NMOS transistor M6 is greater than the potential of the drain of the sixth NMOS transistor M6 , The sixth NMOS transistor M6 is turned on; because the potential of the gate of the fifth NMOS transistor M5 is the potential of the first input terminal of the first low voltage selection circuit 101, and the potential of the drain of the fifth NMOS transistor M5 is the first low voltage The potential of the second input terminal of the selection circuit 101, so the potential of the gate of the fifth NMOS transistor M5 is smaller than the potential of the drain of the fifth NMOS transistor M5, so the fifth NMOS transistor M5 is turned off.

Because the fifth NMOS transistor M5 is off and the sixth NMOS transistor M6 is on, the potential of the signal PW at the output of the first low-voltage selection circuit 101 is the potential of the first input of the first voltage selection circuit 101.

When the potential of the first input terminal of the first low voltage selection circuit 101 is greater than the potential of the second input terminal of the first low voltage selection circuit 101, because the potential of the gate of the sixth NMOS transistor M6 is the second input of the first low voltage selection circuit 101 Potential of the terminal, and the potential of the drain of the sixth NMOS transistor M6 is the potential of the first input terminal of the first low voltage selection circuit 101, so the potential of the gate of the sixth NMOS transistor M6 is less than the potential of the drain of the sixth NMOS transistor M6 , The sixth NMOS transistor is turned off; because the potential of the gate of the fifth NMOS transistor M5 is the potential of the first input terminal of the first low voltage selection circuit 101, and the potential of the drain of the fifth NMOS transistor M5 is the first low voltage selection The potential of the second input terminal of the circuit 101, so the potential of the gate of the fifth NMOS transistor M5 is greater than the potential of the drain of the fifth NMOS transistor M5, so the fifth NMOS transistor M5 is turned on.

Since the fifth NMOS transistor M5 is turned on and the sixth NMOS transistor M6 is turned off, the potential of the signal PW at the output terminal of the first low voltage selection circuit 101 is the potential of the second input terminal of the first voltage selection circuit 101.

In summary, when the potential of the first input terminal of the first low voltage selection circuit 101 is less than the potential of the second input terminal of the first low voltage selection circuit 101, the potential of the signal PW at the output terminal of the first low voltage selection circuit 101 is the first voltage The potential of the first input terminal of the selection circuit 101; and when the potential of the first input terminal of the first low voltage selection circuit 101 is greater than the potential of the second input terminal of the first low voltage selection circuit 101, the signal PW of the output terminal of the first low voltage selection circuit 101 Is the potential of the second input terminal of the first voltage selection circuit 101; for example, the enable signal PD is off, the potential of the output terminal of the analog switch circuit and the potential of the first input terminal of the first low voltage selection circuit 101 are When the NMOS transistor is pulled down to the ground level GND, if the potential of the input terminal of the analog switch circuit and the potential VIN of the second input terminal of the first low voltage selection circuit 101 are positive voltage signals, then PW=GND; if the input of the analog switch circuit The potential of the terminal and the potential VIN of the second input terminal of the first low voltage selection circuit 101 are negative voltage signals, then PW=VIN. Therefore, the signal PW at the output terminal of the first low-voltage selection circuit 101 is a signal with a low potential between the signals received at the two input terminals of the first low-voltage selection circuit 101.

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

Optionally, as shown in FIG. 6, in another embodiment of the present invention, an implementation manner of the charge pump circuit 200 includes: a generating circuit 201, a second voltage selection circuit 202, and a second pull-down circuit 203; wherein:

The input terminal of the generating circuit 201 is connected to the first input terminal of the second low voltage selection circuit 202, and the connection point is the input terminal of the charge pump circuit 200; the output terminal of the generating circuit 201 is connected to the first terminal of the second pull-down circuit 203, The connection point is the first output terminal of the charge pump circuit 200.

The two power supply terminals of the generating circuit 201 are respectively connected to two inverted clocks; wherein, the power supply terminal of the generating circuit 201 connected to the inverted clock CLKN is the first power supply terminal of the generating circuit 201, and the generating circuit connected to the inverted clock CLK The power supply terminal of 201 is the second power supply terminal of the generating circuit 201.

The second input terminal of the second low voltage selection circuit 202 is grounded; the output terminal of the second low voltage selection circuit 202 is connected to the second terminal of the second pull-down circuit 203; the control terminal of the second pull-down circuit 203 is the charge pump circuit 200 Control terminal.

It should be noted that, in the second low voltage selection circuit 202, a signal with a low potential between the signal received at the first input terminal and the signal received at the second input terminal is used as the signal GS at the output terminal. Moreover, when the charge pump circuit 200 operates normally, the generating circuit 201 can process the signal received at the input terminal of the generating circuit 201 to increase the potential of the signal G at the output terminal of the generating circuit 201. In addition, the driving voltage of the two inverted clocks is the preset voltage VDD.

The specific working principle is:

When the enable signal PD is an off signal, the signal PD received by the control terminal of the second pull-down circuit 203 is at a high level, and the potential of the signal PW received by the input terminal of the charge pump circuit 200 is that of the analog switch circuit. The lower value between the input voltage VIN at the input and the ground level GND, that is, PW=min(VIN, GND).

If the input voltage VIN of the input terminal of the analog switch circuit is a negative voltage signal, that is, less than the ground level GND, that is, VIN<GND, the potential of the signal PW received by the input terminal of the charge pump circuit 200 is the analog switch circuit The input voltage VIN at the input of the input terminal, that is, PW=VIN, the potential of the first input terminal of the corresponding second low-voltage selection circuit 202 is the input voltage VIN of the input terminal of the analog switching circuit, and because the second voltage of the second low-voltage selection circuit 202 The potential at the input terminal is the ground level GND, so the second low voltage selection circuit 202 selects the signal PW received at the input terminal of the charge pump circuit 200 as the signal GS at the output terminal of the second low voltage selection circuit 202, that is, GS=VIN. At this time, the potential of the signal PD received by the control terminal of the second pull-down circuit 203 is high, so the potential of the signal PD received by the control terminal of the second pull-down circuit 203 is greater than that received by the second terminal of the second pull-down circuit 203 The potential of the received signal GS, that is, PD>GS, so the second pull-down circuit 203 is turned on to pull down the potential of the signal G at the output of the charge pump circuit 200 to the input voltage VIN at the input of the analog switch circuit, that is, G= VIN.

If the input voltage VIN of the input terminal of the analog switch circuit is a positive voltage signal, that is, greater than the ground level GND, that is, VIN>GND, the potential of the signal PW received by the input terminal of the charge pump circuit 200 is the ground level GND, That is, PW=GND, the potential of the first input terminal of the corresponding second low voltage selection circuit 202 is the ground level GND, and because the potential of the second input terminal of the second low voltage selection circuit 202 is the ground level GND, the second low voltage selection The circuit 202 selects the signal PW received at the input terminal of the charge pump circuit 200 or the signal received at the second input terminal of the second low voltage selection circuit 202 as the signal GS at the output terminal of the second low voltage selection circuit 202, the second The potential of the signal GS at the output of the low-voltage selection circuit 202 is at the ground level GND, that is, GS=GND. At this time, the potential of the signal PD received by the control terminal of the second pull-down circuit 203 is high, so the potential of the signal PD received by the control terminal of the second pull-down circuit 203 is greater than that received by the second terminal of the second pull-down circuit 203 The potential of the received signal GS, that is, PD>GS, so the second pull-down circuit 203 is turned on to pull down the potential of the signal G at the output of the charge pump circuit 200 to the ground level GND, that is, G=GND.

When the enable signal PD is an on signal, the potential of the signal PW received at the input terminal of the charge pump circuit 200 is equal to the input voltage VIN at the output terminal of the analog switch circuit, that is, PW=VIN, and the control of the second pull-down circuit 203 The potential of the signal PD received by the terminal is a low level, regardless of whether the signal GS received by the second terminal of the second pull-down circuit 203 is the signal PW received by the input terminal of the charge pump circuit 200 or the second low voltage selection circuit 202 The signals received by the second input terminal are not turned on by the second pull-down circuit 203, so the charge pump circuit 200 can be simplified, as shown in FIG.

When the potential of the signal CLKN received by the first power supply terminal of the generating circuit 201 is the preset voltage VDD, that is, CLKN=VDD, and the potential of the signal CLK received by the second power supply terminal of the generating circuit 201 is 0, that is, CLK=0, Then, the potential of the signal G at the output of the generating circuit 201 is the sum of the potential of the signal PW received by the input of the power pump circuit 200 and the preset voltage VDD, that is, G=PW+VDD.

When the potential of the signal CLKN received by the first power supply terminal of the generating circuit 201 is 0, that is, CLKN=0, and the potential of the signal CLK received by the second power supply terminal of the generating circuit 201 is the preset voltage VDD, that is, CLK=VDD Then, the potential of the signal G at the output of the generating circuit 201 is the sum of the potential of the signal PW received by the input of the power supply pump circuit 200 and the preset voltage VDD, that is, G=PW+VDD.

In summary, when the enable signal PD is an on signal, the potential of the signal G at the output of the generating circuit 201 is the sum of the potential of the signal PW received by the input of the power pump circuit 200 and the preset voltage VDD, that is G=PW+VDD.

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

Optionally, as shown in FIG. 8, in another embodiment of the present invention, an implementation of the generating circuit 201 includes: a seventh NMOS transistor M7, an eighth NMOS transistor M8, a first PMOS transistor P1, and a second PMOS transistor P2 and the first capacitor C1 and the second capacitor C2 with the same capacitance; where:

The source and substrate of the seventh NMOS transistor M7 and the source and substrate of the eighth NMOS transistor M8 are connected and the connection point is the input terminal of the generation circuit 201.

The drain of the seventh NMOS transistor M7, the gate of the eighth NMOS transistor M8, one end of the first capacitor, the source of the first PMOS transistor P1 and the gate of the second PMOS transistor P2 are connected, and the connection point is the first charging point A.

The drain of the eighth NMOS transistor M8, the gate of the seventh NMOS transistor M7, one end of the second capacitor, the source of the second PMOS transistor P2 and the gate of the first PMOS transistor P1 are connected, and the connection point is the second charging point B.

The other end of the first capacitor C1 is connected to the inverted clock CLKN, and the other end of the second capacitor is connected to the inverted clock CLK; the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, and the connection point is the generating circuit 201 Output.

It should be noted that both the seventh NMOS transistor M7 and the eighth NMOS transistor M8 are NMOS transistors with DNW isolation.

It should also be noted that the seventh NMOS transistor M7 and the eighth NMOS transistor M8 form a low-voltage selection circuit similar to the first low-voltage selection circuit 101. When the potential of the first charging point A is less than the potential of the second charging point B, Seven NMOS transistor M7 is turned on; when the first charging point A is greater than the second charging point B, the eighth NMOS transistor M8 is turned on; In addition, the first PMOS transistor P1 and the second PMOS transistor P2 form a high voltage selection circuit, when the first When the potential at the charging point A is less than the potential at the second charging point B, the second PMOS transistor P2 is turned on; when the potential at the first charging point A is greater than the potential at the second charging point B, the first PMOS transistor P1 is turned on.

For the generating circuit 201, the potential of the signal CLKN received by the first power supply terminal is the preset voltage VDD, and the potential of the signal CLK received by the second power supply terminal is 0, that is, when the potential of the first charging point A is greater than At the potential of the second charging point B, the eighth NMOS transistor M8 is turned on, the first PMOS transistor P1 is turned on, and the potential of the first charging point A is charged to the potential of the signal PW received at the input of the generating circuit 201 Given the sum of the voltages VDD, the potential of the second charging point B is charged to the potential of the signal PW received by the input of the generating circuit 201, so the potential of the signal G output from the output of the generating circuit 201 is the potential of the first charging point A The sum of the potential of the signal PW received by the input terminal of the generating circuit 201 and the preset voltage VDD, that is, G=PW+VDD.

When the potential of the signal CLKN received by the first power terminal is 0 and the potential of the signal CLK received by the second power terminal is the preset voltage VDD, that is, when the potential of the first charging point A is less than that of the second charging point B At potential, the seventh NMOS transistor M7 is turned on, the second PMOS transistor P2 is turned on, and the potential at the second charging point B is charged to the sum of the potential of the signal PW received at the input of the generating circuit 201 and the preset voltage VDD, The potential of the first charging point A is charged to the potential of the signal PW received by the input of the generating circuit 201, so the potential of the signal G output from the output of the generating circuit 201 is the potential of the first charging point A and is charged to the generating circuit 201 The potential of the signal PW received at the input of the sum of the preset voltage VDD, that is, G=PW+VDD.

Optionally, as shown in FIG. 8, an embodiment of the second low-voltage selection circuit 202 includes: a ninth NMOS transistor M9 and a tenth NMOS transistor M10; where:

The drain of the ninth NMOS transistor M9 is connected to the gate of the tenth NMOS transistor M10, and the connection point is the first input terminal of the second low voltage selection circuit 202.

The gate of the ninth NMOS transistor M9 is connected to the drain of the tenth NMOS transistor M10, and the connection point is the second input terminal of the second low voltage selection circuit 202.

The source and substrate of the ninth NMOS transistor M9 and the source and substrate of the tenth NMOS transistor M10 are connected and the connection point is the output of the second low voltage selection circuit 202.

The specific working principle of the second low-voltage selection circuit 202 is the same as that of the first low-voltage selection circuit 101. For details, please refer to the specific working principle of the first low-voltage selection circuit 101.

Optionally, as shown in FIG. 8, an embodiment of the second pull-down circuit 203 includes: an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13; where:

The drain of the eleventh NMOS transistor M11 is connected to the first charging point; the drain of the twelfth NMOS transistor M12 is connected to the second charging point; the drain of the thirteenth NMOS transistor M13 is the first end of the second pull-down circuit 203 .

The source and substrate of the eleventh NMOS transistor M11, the source and substrate of the twelfth NMOS transistor M12, and the source and substrate of the thirteenth NMOS transistor M13 are connected, and the connection point is that of the second pull-down circuit 203 The second end.

The gate of the eleventh NMOS transistor M11, the gate of the twelfth NMOS transistor M12 and the gate of the thirteenth NMOS transistor M13 are connected, and the connection point is the control terminal of the second pull-down circuit 203.

For the second pull-down circuit 203, when the enable signal PD is an off signal, the potential of the signal PD received by the gates of the eleventh NMOS transistor M11, the twelfth NMOS transistor M12, and the thirteenth NMOS transistor M13 All of them are high level, and the source potential of the three is the ground level GND, so all three are turned on, respectively connecting the first charging point A, the second charging point B and the first end of the second pull-down circuit 203 The potential is pulled down to ground level.

When the enable signal PD is an on signal, the potentials of the gates of the eleventh NMOS transistor M11, the twelfth NMOS transistor M12, and the thirteenth NMOS transistor M13 are all low, and all three are turned off at this time. .

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

Optionally, as shown in FIG. 9, on the basis of the foregoing embodiment, the charge pump circuit 200 further includes: a high-voltage selection circuit 204; wherein:

The first input terminal of the high voltage selection circuit 204 is connected to the output terminal of the generation circuit 201; the second input terminal of the high voltage selection circuit 204 is grounded; the output terminal of the high voltage selection circuit 204 is connected to the substrate of the first PMOS transistor P1 and the first The substrates of the two PMOS transistors P2 are connected.

It should be noted that, in the high voltage selection circuit 204, a signal with a high potential between the signal received at the first input terminal and the signal received at the second input terminal is used as the signal NW at the output terminal of the high voltage selection circuit 204.

As an implementation, as shown in FIG. 10, the high-voltage selection circuit 204 includes: a third PMOS transistor P3 and a fourth PMOS transistor P4; where:

The drain of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4, and the connection point is the first input terminal of the high voltage selection circuit 204.

The gate of the third PMOS transistor P3 is connected to the drain of the fourth PMOS transistor P4, and the connection point is the second input terminal of the high voltage selection circuit 204.

The source and substrate of the third PMOS transistor P3, and the source and substrate of the fourth PMOS transistor P4 are connected and the connection point is the output of the high voltage selection circuit 204.

In the high voltage selection circuit 204:

When the potential of the first input terminal is less than the potential of the second input terminal, the potential of the gate of the fourth PMOS transistor P4 is less than the potential of the drain of the fourth PMOS transistor P4, so the fourth PMOS transistor P4 is turned on; and the third PMOS The potential of the gate of the transistor P3 is greater than the potential of the drain of the third PMOS transistor P3, so the third PMOS transistor P3 is turned off. At this time, the potential of the signal NW at the output of the high-voltage selection circuit 204 is the potential of the second input of the high-voltage selection circuit 204.

Moreover, when the potential of the first input terminal is greater than the potential of the second input terminal, the potential of the gate of the fourth PMOS transistor P4 is greater than the potential of the drain of the fourth PMOS transistor P4, so the fourth PMOS transistor P4 is turned off; and the first The potential of the gate of the three PMOS transistor P3 is lower than the potential of the drain of the third PMOS transistor P3, so the third PMOS transistor P3 is turned on. At this time, the potential of the signal NW at the output of the high-voltage selection circuit 204 is the potential of the first input of the high-voltage selection circuit 204.

In summary, the signal NW at the output of the high-voltage selection circuit 204 is a signal with a high potential between the signals received by the two input terminals of the high-voltage selection circuit 204, that is, max(G, GND). Therefore, the substrate NW of the first PMOS transistor P1 and the second PMOS transistor P2 is always equal to max (G, GND), which can ensure that the parasitic body diodes of the two will not be forward-conducted in any case, avoiding leakage or even burning The risk of two tubes.

It should be noted that the MOS transistors in the above embodiments of the present application can also use other types of switch tubes, and the implementation form of each circuit can also use other topologies or integrated chips, as long as they can achieve the corresponding functions. Within the scope of protection of this application.

The rest of the structure and principle are the same as those in the above embodiment, and will not be repeated here.

The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (21)

1. An analog switch circuit is characterized by comprising: a switch tube, a control circuit, a first pull-down circuit and a charge pump circuit; wherein:

   The control terminal of the charge pump circuit and the control terminal of the first pull-down circuit both receive the enable signal;

   The second end of the first pull-down circuit is grounded;

   The first end of the first pull-down circuit, the first input end of the control circuit, and the first end of the switch tube are all connected to the output end of the analog switch circuit;

   The second input terminal of the control circuit and the second terminal of the switch tube are connected to the input terminal of the analog switch circuit;

   The output terminal of the control circuit, and, the third terminal of the switch tube are connected to the input terminal of the charge pump circuit;

   The first output terminal of the charge pump circuit is connected to the control terminal of the control circuit and the control terminal of the switch tube;

   The switch tube is a switch tube which is turned on when the control terminal potential is higher than the second terminal potential.
2. The analog switch circuit according to claim 1, wherein when the enable signal is an off signal, the second terminal potential of the first pull-down circuit is a ground level, and the output of the control circuit The terminal potential is a lower value between the ground level and the voltage value of the signal received at the input terminal of the analog switch, and the first output terminal potential of the charge pump circuit is pulled down to the lower value to make the The switch is turned off; and/or,

   When the enable signal is a turn-on signal, the output terminal potential of the control circuit is equal to the voltage value of the received signal at the input terminal of the analog switch circuit, the charge pump circuit works normally and the first output terminal potential is equal to the The input terminal of the analog switch receives the sum of the voltage value of the signal and the preset voltage to turn on the switch.
3. The analog switch circuit according to claim 1, wherein the switch is a first NMOS transistor;

   The gate of the first NMOS transistor is the control end of the switch tube;

   The drain of the first NMOS transistor is the first end of the switch tube;

   The source of the first NMOS transistor is the second end of the switch tube;

   The substrate of the first NMOS transistor is the third end of the switch tube.
4. The analog switch circuit according to claim 1, wherein the first pull-down circuit comprises: a second NMOS transistor;

   The gate of the second NMOS transistor is the control end of the first pull-down circuit;

   The drain of the second NMOS transistor is the first end of the first pull-down circuit;

   The source of the second NMOS transistor is the second end of the first pull-down circuit;

   The substrate of the second NMOS transistor is connected to the second output terminal of the charge pump circuit.
5. The analog switch circuit according to claim 1, wherein the control circuit comprises: a first low voltage selection circuit and a connection circuit; wherein:

   The control end of the connection circuit is the control end of the control circuit;

   The first input terminal of the first low voltage selection circuit is connected to the first input terminal of the connection circuit, and the connection point is the first input terminal of the control circuit;

   The second input terminal of the first low voltage selection circuit is connected to the second input terminal of the connection circuit, and the connection point is the second input terminal of the control circuit;

   The output terminal of the first low voltage selection circuit is connected to the third terminal of the connection circuit, and the connection point is the output terminal of the control circuit.
6. The analog switch circuit according to claim 5, wherein the connection circuit comprises: a third NMOS transistor and a fourth NMOS transistor;

   The drain of the third NMOS transistor is the second input end of the connection circuit;

   The drain of the fourth NMOS transistor is the first input end of the connection circuit;

   The source and the substrate of the third NMOS transistor, and the source and the substrate of the fourth NMOS transistor are all connected and the connection point is the third end of the connection circuit;

   The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, and the connection point is the control end of the connection circuit.
7. The analog switch circuit according to claim 5, wherein the first low voltage selection circuit includes: a fifth NMOS transistor and a sixth NMOS transistor;

   The drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the connection point is the second input terminal of the first low voltage selection circuit;

   The gate of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the connection point is the first input terminal of the first low voltage selection circuit;

   The source and the substrate of the fifth NMOS transistor, and the source and the substrate of the sixth NMOS transistor are connected and the connection point is the output end of the first low voltage selection circuit.
8. The analog switch circuit according to any one of claims 1-7, wherein the charge pump circuit includes: a generating circuit, a second low voltage selection circuit, and a second pull-down circuit; wherein:

   The input terminal of the generating circuit is connected to the first input terminal of the second low voltage selection circuit, and the connection point is the input terminal of the charge pump circuit;

   The output terminal of the generating circuit is connected to the first terminal of the second pull-down circuit, and the connection point is the first output terminal of the charge pump circuit;

   Two power supply terminals of the generating circuit are respectively connected to two inverted clocks, and the driving voltage of the two inverted clocks is the preset voltage;

   The second input terminal of the second low voltage selection circuit is grounded;

   The output terminal of the second low voltage selection circuit is connected to the second terminal of the second pull-down circuit;

   The control terminal of the second pull-down circuit is the control terminal of the charge pump circuit.
9. The analog switch circuit according to claim 8, wherein the generating circuit includes: a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first capacitor and a Two capacitors;

   The source and substrate of the seventh NMOS transistor, and the source and substrate of the eighth NMOS transistor are connected and the connection point is the input end of the generating circuit;

   The drain of the seventh NMOS transistor, the gate of the eighth NMOS transistor, one end of the first capacitor, the source of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected The point is the first charging point;

   The drain of the eighth NMOS transistor, the gate of the seventh NMOS transistor, one end of the second capacitor, the source of the second PMOS transistor and the gate of the first PMOS transistor are connected and connected Point is the second charging point;

   The other end of the first capacitor is connected to an inverted clock, and the other end of the second capacitor is connected to another inverted clock;

   The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the connection point is the output end of the generating circuit.
10. The analog switch circuit according to claim 9, wherein the seventh NMOS transistor and the eighth NMOS transistor are NMOS transistors with DNW isolation.
11. The analog switch circuit according to claim 9, wherein the second pull-down circuit includes: an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor;

    The drain of the eleventh NMOS transistor is connected to the first charging point;

    The drain of the twelfth NMOS transistor is connected to the second charging point;

    The drain of the thirteenth NMOS transistor is the first end of the second pull-down circuit;

    The source and substrate of the eleventh NMOS transistor, the source and substrate of the twelfth NMOS transistor, and the source and substrate of the thirteenth NMOS transistor are connected, and the connection point is the The second end of the second pull-down circuit;

    The gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor are connected, and the connection point is the control terminal of the second pull-down circuit.
12. The analog switch circuit according to claim 9, wherein the charge pump circuit further comprises: a high voltage selection circuit;

    The first input terminal of the high voltage selection circuit is connected to the output terminal of the generation circuit;

    The second input terminal of the high voltage selection circuit is grounded;

    The output terminal of the high voltage selection circuit is connected to the substrate of the first PMOS transistor and the substrate of the second PMOS transistor.
13. The analog switch circuit according to claim 12, wherein the high voltage selection circuit includes: a third PMOS transistor and a fourth PMOS transistor;

    The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the connection point is the first input terminal of the high voltage selection circuit;

    The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the connection point is the second input terminal of the high voltage selection circuit;

    The source and the substrate of the third PMOS transistor, and the source and the substrate of the fourth PMOS transistor are all connected and the connection point is the output end of the high voltage selection circuit.
14. The analog switch circuit according to claim 8, wherein the second low voltage selection circuit includes: a ninth NMOS transistor and a tenth NMOS transistor;

    The drain of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the connection point is the first input terminal of the second low voltage selection circuit;

    The gate of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the connection point is the second input terminal of the second low voltage selection circuit;

    The source and the substrate of the ninth NMOS transistor, and the source and the substrate of the tenth NMOS transistor are connected and the connection point is the output end of the second low voltage selection circuit.
15. A charge pump circuit is characterized by comprising: a generating circuit, a second low voltage selection circuit and a second pull-down circuit; wherein:

    The input terminal of the generating circuit is connected to the first input terminal of the second low voltage selection circuit, and the connection point is the input terminal of the charge pump circuit;

    The output terminal of the generating circuit is connected to the first terminal of the second pull-down circuit, and the connection point is the first output terminal of the charge pump circuit;

    Two power supply terminals of the generating circuit are respectively connected to two inverted clocks, and the driving voltages of the two inverted clocks are preset voltages;

    The second input terminal of the second low voltage selection circuit is grounded;

    The output terminal of the second low voltage selection circuit is connected to the second terminal of the second pull-down circuit;

    The control terminal of the second pull-down circuit is the control terminal of the charge pump circuit.
16. The charge pump circuit according to claim 15, wherein the generation circuit includes: a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first capacitor and a Two capacitors;

    The source and substrate of the seventh NMOS transistor, and the source and substrate of the eighth NMOS transistor are connected and the connection point is the input end of the generating circuit;

    The drain of the seventh NMOS transistor, the gate of the eighth NMOS transistor, one end of the first capacitor, the source of the first PMOS transistor and the gate of the second PMOS transistor are connected and connected The point is the first charging point;

    The drain of the eighth NMOS transistor, the gate of the seventh NMOS transistor, one end of the second capacitor, the source of the second PMOS transistor and the gate of the first PMOS transistor are connected and connected Point is the second charging point;

    The other end of the first capacitor is connected to an inverted clock, and the other end of the second capacitor is connected to another inverted clock;

    The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the connection point is the output end of the generating circuit.
17. The charge pump circuit according to claim 16, wherein the seventh NMOS transistor and the eighth NMOS transistor are NMOS transistors with DNW isolation.
18. The charge pump circuit according to claim 16, wherein the second pull-down circuit includes: an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor;

    The drain of the eleventh NMOS transistor is connected to the first charging point;

    The drain of the twelfth NMOS transistor is connected to the second charging point;

    The drain of the thirteenth NMOS transistor is the first end of the second pull-down circuit;

    The source and substrate of the eleventh NMOS transistor, the source and substrate of the twelfth NMOS transistor, and the source and substrate of the thirteenth NMOS transistor are connected, and the connection point is the The second end of the second pull-down circuit;

    The gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor are connected, and the connection point is the control terminal of the second pull-down circuit.
19. The charge pump circuit according to claim 16, further comprising: a high voltage selection circuit;

    The first input terminal of the high voltage selection circuit is connected to the output terminal of the generation circuit;

    The second input terminal of the high voltage selection circuit is grounded;

    The output terminal of the high voltage selection circuit is connected to the substrate of the first PMOS transistor and the substrate of the second PMOS transistor.
20. The charge pump circuit according to claim 19, wherein the high voltage selection circuit includes: a third PMOS transistor and a fourth PMOS transistor;

    The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the connection point is the first input terminal of the high voltage selection circuit;

    The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the connection point is the second input terminal of the high voltage selection circuit;

    The source and the substrate of the third PMOS transistor, and the source and the substrate of the fourth PMOS transistor are all connected and the connection point is the output end of the high voltage selection circuit.
21. The charge pump circuit according to claim 15, wherein the second low voltage selection circuit includes: a ninth NMOS transistor and a tenth NMOS transistor;

    The drain of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the connection point is the first input terminal of the second low voltage selection circuit;

    The gate of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the connection point is the second input terminal of the second low voltage selection circuit;

    The source and the substrate of the ninth NMOS transistor, and the source and the substrate of the tenth NMOS transistor are connected and the connection point is the output end of the second low voltage selection circuit.

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