CN109379071A - A kind of analog switching circuit - Google Patents
A kind of analog switching circuit Download PDFInfo
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- CN109379071A CN109379071A CN201811561655.0A CN201811561655A CN109379071A CN 109379071 A CN109379071 A CN 109379071A CN 201811561655 A CN201811561655 A CN 201811561655A CN 109379071 A CN109379071 A CN 109379071A
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- circuit
- nmos transistor
- pull
- tie point
- grid
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
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Abstract
The present invention provides a kind of analog switching circuit, comprising: switching tube, control circuit, the first pull-down circuit and charge pump circuit；When enable signal is shutdown, second terminal potential of the first pull-down circuit is ground level, the output terminal potential of control circuit is lower value between the voltage value of the input terminal reception signal of ground level and analog switch, the first of charge pump circuit output terminal potential is pulled down as lower value, switching tube is turned off；When enable signal is conducting, the input terminal that the output terminal potential of control circuit is equal to analog switching circuit receives the voltage value of signal, charge pump circuit works normally and the first output terminal potential receives the sum of voltage value and predeterminated voltage of signal equal to the input terminal of analog switch, and switching tube is connected.The conduction for negative voltage signal can be realized without Zener diode in the present invention, avoids the demanding problem of technique in the prior art.
Description
Technical field
The present invention relates to power electronics field, in particular to a kind of analog switching circuit.
Background technique
Analog switch is used to input terminal received signal being transmitted to output end, it is being mainly used for conduction just under normal circumstances
Voltage signal, but in certain application scenarios, such as voice applications scene, analog switch is needed to support the defeated of negative voltage signal
Enter.
Fig. 1 show a kind of analog switching circuit structure for supporting negative voltage signal to input, and wherein M1 is analog switch pipe.
Its concrete principle is: booster circuit generates high voltage, and current source I is to bias Zener diode Z；It is opened when analog switch is in
It is due to the breakdown pressure stabilization function of Zener diode Z, the pressure difference between the grid G and source S of analog switch pipe M1 is steady when state
It is scheduled on the pressure stabilizing value of Zener diode Z, to open analog switch, input terminal VIN received signal is transmitted to output end
VOUT。
Although the conduction of negative voltage signal may be implemented in circuit shown in Fig. 1, still, be based on design cost and process aspect
The considerations of, the design element that Zener diode can be not necessarily equipped with, that is, the design of existing analog switch is to technique side
The requirement in face is excessively high.
Summary of the invention
The present invention provides a kind of analog switching circuit, to solve the problems, such as that technique is demanding in the prior art.
To achieve the above object, technical solution provided by the present application is as follows:
A kind of analog switching circuit, comprising: switching tube, control circuit, the first pull-down circuit and charge pump circuit；Its
In:
The control terminal of the charge pump circuit, and, the control terminal of first pull-down circuit, reception enable signal；
The second end of first pull-down circuit is grounded；
The first end of first pull-down circuit, the first input end of the control circuit, and, the of the switching tube
One end is connected with the output end of the analog switching circuit；
Second input terminal of the control circuit, and, the second end of the switching tube, with the analog switching circuit
Input terminal is connected；
The output end of the control circuit, and, the third end of the switching tube, the input terminal with the charge pump circuit
It is connected；
The control of first output end of the charge pump circuit and the control terminal of the control circuit and the switching tube
End is connected；
The switching tube is to control terminal potential to be higher than the switching tube be connected when the second terminal potential；
When the enable signal is shutdown, the second terminal potential of first pull-down circuit is ground level, the control
The output terminal potential of circuit is lower value between the voltage value of the input terminal reception signal of ground level and the analog switch, will
First output terminal potential drop-down of the charge pump circuit is the lower value, turns off the switching tube；
When the enable signal is conducting, the output terminal potential of the control circuit is equal to the analog switching circuit
Input terminal receives the voltage value of signal, and the charge pump circuit works normally and the first output terminal potential is equal to the analog switch
Input terminal receive the voltage value and the sum of predeterminated voltage of signal, the switching tube is connected.
Optionally, the switching tube is the first NMOS transistor；
The grid of first NMOS transistor is the control terminal of the switching tube；
The drain electrode of first NMOS transistor is the first end of the switching tube；
The source electrode of first NMOS transistor is the second end of the switching tube；
The substrate of first NMOS transistor is the third end of the switching tube.
Optionally, first pull-down circuit includes: the second NMOS transistor；
The grid of second NMOS transistor is the control terminal of first pull-down circuit；
The drain electrode of second NMOS transistor is the first end of first pull-down circuit；
The source electrode of second NMOS transistor is the second end of first pull-down circuit；
The substrate of second NMOS transistor is connected with the second output terminal of the charge pump circuit.
Optionally, the control circuit includes: the first low-voltage selection circuit and connection circuit；Wherein:
The control terminal of the connection circuit is the control terminal of the control circuit；
The first input end of the first low-voltage selection circuit is connected with the first input end of the connection circuit, connects
Point is the first input end of the control circuit；
Second input terminal of the first low-voltage selection circuit is connected with the second input terminal of the connection circuit, connects
Point is the second input terminal of the control circuit；
The output end of the first low-voltage selection circuit is connected with the third end of the connection circuit, and tie point is described
The output end of control circuit.
Optionally, the connection circuit includes: third NMOS transistor and the 4th NMOS transistor；
The drain electrode of the third NMOS transistor is the second input terminal of the connection circuit；
The drain electrode of 4th NMOS transistor is the first input end of the connection circuit；
The source electrode and substrate of the third NMOS transistor, and, the source electrode and substrate of the 4th NMOS transistor,
It is connected and tie point is the third end of the connection circuit；
The grid of the third NMOS transistor is connected with the grid of the 4th NMOS transistor, and tie point is the company
Connect the control terminal of circuit.
Optionally, the first low-voltage selection circuit includes: the 5th NMOS transistor and the 6th NMOS transistor；
The drain electrode of 5th NMOS transistor is connected with the grid of the 6th NMOS transistor, and tie point is described the
Second input terminal of one low-voltage selection circuit；
The grid of 5th NMOS transistor is connected with the drain electrode of the 6th NMOS transistor, and tie point is described the
The first input end of one low-voltage selection circuit；
The source electrode and substrate of 5th NMOS transistor, and, the source electrode and substrate of the 6th NMOS transistor,
It is connected and tie point is the output end of the first low-voltage selection circuit.
Optionally, the charge pump circuit includes: generative circuit, the second low-voltage selection circuit and the second pull-down circuit；
Wherein:
The input terminal of the generative circuit is connected with the first input end of the second low-voltage selection circuit, and tie point is
The input terminal of the charge pump circuit；
The output end of the generative circuit is connected with the first end of second pull-down circuit, and tie point is the charge pump
First output end of circuit；
Two power ends of the generative circuit connect two inversion clocks respectively, and the driving voltage of two inversion clocks is
The predeterminated voltage；
Second input end grounding of the second low-voltage selection circuit；
The output end of the second low-voltage selection circuit is connected with the second end of second pull-down circuit；
The control terminal of second pull-down circuit is the control terminal of the charge pump circuit.
Optionally, the generative circuit include: the 7th NMOS transistor, the 8th NMOS transistor, the first PMOS transistor,
Second PMOS transistor and the identical first capacitor of capacitance and the second capacitor；
The source electrode and substrate of 7th NMOS transistor, and, the source electrode and substrate of the 8th NMOS transistor,
It is connected and tie point is the input terminal of the generative circuit；
The drain electrode of 7th NMOS transistor, the grid of the 8th NMOS transistor, the first capacitor one end,
The source electrode of first PMOS transistor and the grid of second PMOS transistor are connected, and tie point is the first charge point；
The drain electrode of 8th NMOS transistor, the grid of the 7th NMOS transistor, second capacitor one end,
The source electrode of second PMOS transistor and the grid of first PMOS transistor are connected, and tie point is the second charge point；
One inversion clock of another termination of the first capacitor, when another reverse phase of another termination of second capacitor
Clock；
The drain electrode of first PMOS transistor is connected with the drain electrode of second PMOS transistor, and tie point is the life
At the output end of circuit.
Optionally, the 7th NMOS transistor and the 8th NMOS transistor are the NMOS crystal with DNW isolation
Pipe.
Optionally, second pull-down circuit includes: the 11st NMOS transistor, the tenth bi-NMOS transistor and the 13rd
NMOS transistor；
The drain electrode of 11st NMOS transistor is connected with first charge point；
The drain electrode of tenth bi-NMOS transistor is connected with second charge point；
The drain electrode of 13rd NMOS transistor is the first end of second pull-down circuit；
The source electrode and substrate of 11st NMOS transistor, the source electrode of the tenth bi-NMOS transistor and substrate and institute
The source electrode for stating the 13rd NMOS transistor is connected with substrate, and tie point is the second end of second pull-down circuit；
The grid and the 13rd NMOS of the grid of 11st NMOS transistor, the tenth bi-NMOS transistor
The grid of transistor is connected, and tie point is the control terminal of second pull-down circuit.
Optionally, the charge pump circuit further include: high voltage selection circuit；
The first input end of the high voltage selection circuit is connected with the output end of the generative circuit；
Second input end grounding of the high voltage selection circuit；
The substrate and the 2nd PMOS of the output end of the high voltage selection circuit and first PMOS transistor
The substrate of transistor is connected.
Optionally, the high voltage selection includes: third PMOS transistor and the 4th PMOS transistor；
The drain electrode of the third PMOS transistor is connected with the grid of the 4th PMOS transistor, and tie point is the height
The first input end of voltage selecting circuit；
The grid of the third PMOS transistor is connected with the drain electrode of the 4th PMOS transistor, and tie point is the height
Second input terminal of voltage selecting circuit；
The source electrode and substrate of the third PMOS transistor, and, the source electrode and substrate of the 4th PMOS transistor,
It is connected and tie point is the output end of the high voltage selection circuit.
Optionally, the second low-voltage selection circuit includes: the 9th NMOS transistor and the tenth NMOS transistor；
The drain electrode of 9th NMOS transistor is connected with the grid of the tenth NMOS transistor, and tie point is described the
The first input end of two low-voltage selection circuits；
The grid of 9th NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, and tie point is described the
Second input terminal of two low-voltage selection circuits；
The source electrode and substrate of 9th NMOS transistor, and, the source electrode and substrate of the tenth NMOS transistor,
It is connected and tie point is the output end of the second low-voltage selection circuit.
Analog switching circuit provided by the invention, when the enable signal is conducting, the output end of the control circuit
Current potential is equal to the input voltage of the input terminal of the analog switching circuit, so that the charge pump circuit is worked normally, and institute
The input for stating the charge pump circuit input terminal that its first output terminal potential is equal to the analog switching circuit in normal work is electric
The sum of pressure and predeterminated voltage；Again since the first output end of the charge pump circuit is connected with the control terminal of switching tube, and switch
The second end of pipe is connected with the input terminal of the analog switch, therefore, when the enable signal is conducting, the control terminal of switching tube
Current potential is higher than the second terminal potential, and the switching tube conducting can be realized signal transduction function.Also, due to the control of switching tube
Terminal potential is equal to the sum of the second terminal potential and predeterminated voltage, therefore, even if the input electricity of the input terminal of the analog switching circuit
Pressure is negative voltage, by the setting to the predeterminated voltage, can also ensure that the control terminal potential of switching tube is higher than second end electricity
Position, i.e. switching tube can be connected and then realize signal transduction.The analog switching circuit provided by the invention is not necessarily to Zener diode
The conduction for negative voltage signal can be realized, avoid the demanding problem of technique in the prior art.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly or in the prior art to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, it is only this that interior attached drawing, which is described below,
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of schematic diagram for analog switching circuit that the prior art provides；
Fig. 2 is a kind of schematic diagram of analog switching circuit disclosed by the embodiments of the present invention；
Fig. 3 is a kind of schematic diagram of analog switching circuit disclosed in another embodiment of the present invention；
Fig. 4 is a kind of schematic diagram of analog switching circuit disclosed in another embodiment of the present invention；
Fig. 5 is a kind of schematic diagram of analog switching circuit disclosed in another embodiment of the present invention；
Fig. 6 is the schematic diagram of the charge pump circuit in a kind of analog switching circuit disclosed by the embodiments of the present invention；
Fig. 7 is the simplified schematic diagram of charge pump circuit in a kind of analog switching circuit disclosed by the embodiments of the present invention；
Fig. 8 is the schematic diagram of the charge pump circuit in a kind of analog switching circuit disclosed in another embodiment of the present invention；
Fig. 9 is the schematic diagram of the charge pump circuit in a kind of analog switching circuit disclosed in another embodiment of the present invention；
Figure 10 is the schematic diagram of the charge pump circuit in a kind of analog switching circuit disclosed in another embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
The present invention provides a kind of analog switching circuit, to solve the problems, such as that technique is demanding in the prior art.
Refer to Fig. 2, the analog switching circuit include: switching tube Q, control circuit 100, the first pull-down circuit 300 and
Charge pump circuit 200；Wherein:
The control terminal of charge pump circuit 200, and, the control terminal of the first pull-down circuit 300, reception enable signal PD；The
The second end of one pull-down circuit 300 is grounded.
The first end of first pull-down circuit 300, the first input end of control circuit 100, and, the first end of switching tube Q,
It is connected with the output end of analog switching circuit.
Second input terminal of control circuit 100, and, the second end of switching tube Q, with the input terminal phase of analog switching circuit
Even.
The output end of control circuit 100, and, the third end of switching tube Q is connected with the input terminal of charge pump circuit 200；
First output end of charge pump circuit 200 is connected with the control terminal of the control terminal of control circuit 100 and switching tube Q.
It should be noted that switching tube Q is to control terminal potential to be higher than the switching tube be connected when the second terminal potential.
It should also be noted that, when enable signal PD is off, control circuit 100 is received with its first input end
Signal and the signal that receives of the second input terminal between the lower signal of current potential, the signal PW as its output end；When enabled
When signal PD is conducting, the current potential of the signal PW of 100 output end of control circuit is equal to the input terminal of the analog switching circuit
The current potential of input signal.
Specific working principle are as follows:
When enable signal PD is shutdown, the current potential for the signal PD that the control terminal of the first pull-down circuit 300 receives is height
Level, the current potential of the second end of the first pull-down circuit 300 are ground level GND；Because of the electricity of the control terminal of the first pull-down circuit 300
Position is greater than the current potential of the second end of the first pull-down circuit 300, so the first pull-down circuit 300 is connected, by the analog switch electricity
The output terminal potential on road pulls down to ground level GND.
Because when enable signal PD is shutdown, the current potential of the signal PW of the output end of control circuit 100 is that the simulation is opened
Lower value between the input voltage VIN and ground level GND of the input terminal on powered-down road, i.e. PW=min (VIN, GND), so electric
The current potential of the signal G of first output end of lotus pump circuit 200 pulled down to the input electricity of the input terminal of the analog switching circuit
Press the lower value between VIN and ground level GND, i.e. G=min (VIN, GND)；No matter the input terminal of the analog switching circuit
Input voltage VIN is positive voltage or negative voltage, and the switching tube Q can be turned off, and then make the analog switching circuit quilt
It complete switches off.
When enable signal PD is conducting, the current potential of the signal PW of the output end of control circuit 100 is equal to the simulation and opens
The input voltage VIN of the output end on powered-down road, i.e. PW=VIN, charge pump circuit 200 works normally, and charge pump circuit 200
The first output end signal G current potential be equal to control circuit 100 output end signal PW current potential and predeterminated voltage VDD it
With i.e. G=PW+VDD, so the current potential of the signal G of the first output end of charge pump circuit 200 is equal to the analog switching circuit
Input terminal input voltage VIN and the sum of predeterminated voltage VDD, i.e. G=VIN+VDD.
Because the current potential of the control terminal received signal G of switching tube Q is equal to the letter of the first output end of charge pump circuit 200
The current potential of number G, therefore when G=VIN+VDD, the current potential of the control terminal of switching tube Q is also equal to the input of the analog switching circuit
The sum of the input voltage VIN at end and predeterminated voltage VDD, so switching tube Q is connected, it can be with conducted signal.
Analog switching circuit provided by the invention, when enable signal PD is conducting, the output terminal potential of control circuit 100
Equal to the input voltage VIN of the input terminal of the analog switching circuit, charge pump circuit 200 is enable to work normally, and charge
Pump circuit 200 in normal work its first output terminal potential be equal to the analog switching circuit input terminal input voltage
The sum of VIN and predeterminated voltage VDD；Again since the first output end of charge pump circuit 200 is connected with the control terminal of switching tube Q, and
The second end of switching tube Q is connected with the input terminal of analog switch, therefore, when enable signal PD is conducting, the control terminal of switching tube Q
Current potential is higher than the second terminal potential, and switching tube Q conducting can be realized signal transduction function.Also, due to the control terminal of switching tube Q
Current potential is equal to the sum of the second terminal potential and predeterminated voltage VDD, therefore, even if the input electricity of the input terminal of the analog switching circuit
Pressure VIN is negative voltage, by the setting to predeterminated voltage VDD, can also ensure that the control terminal potential of switching tube Q is higher than second end
Current potential, i.e. switching tube Q can be connected and then realize signal transduction.The analog switching circuit provided by the invention is not necessarily to Zener two
The conduction for negative voltage signal can be realized in pole pipe, avoids the demanding problem of technique in the prior art.
Optionally, such as Fig. 3, in another embodiment of the invention, a kind of embodiment of switching tube Q includes: first
NMOS transistor M1；Wherein:
The grid of first NMOS transistor M1 is the control terminal of switching tube Q；The drain D of first NMOS transistor M1 is switch
The first end of pipe Q；The source S of first NMOS transistor M1 is the second end of switching tube Q；The substrate of first NMOS transistor M1 is
The third end of switching tube Q.
When the current potential for the signal that the grid of the first NMOS transistor M1 receives is greater than the source S of the first NMOS transistor M1
The current potential received, then the first NMOS tube M1 is connected.
Optionally, such as Fig. 3, a kind of embodiment of the first pull-down circuit 300 includes: the second NMOS transistor M2；Wherein:
The grid of second NMOS transistor M2 is the control terminal of the first pull-down circuit 300；The leakage of second NMOS transistor M2
The extremely first end of the first pull-down circuit 300；The source electrode of second NMOS transistor M2 is the second end of the first pull-down circuit 300；
The substrate of second NMOS transistor M2 is connected with the second output terminal of charge pump circuit 200.
When the current potential for the signal that the grid of the second NMOS transistor M2 receives is greater than the source electrode of the second NMOS transistor M2
The current potential received, then the second NMOS tube M2 is connected.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Optionally, such as Fig. 4, in another embodiment of the invention, a kind of embodiment of control circuit 100 includes:
One low-voltage selection circuit 101 and connection circuit 102；Wherein:
The control terminal for connecting circuit 102 is the control terminal of control circuit 100.
The first input end of first low-voltage selection circuit 101 is connected with the first input end for connecting circuit 102, tie point
For the first input end of control circuit 100；Second input terminal of the first low-voltage selection circuit 101 with connect the of circuit 102
Two input terminals are connected, and tie point is the second input terminal of control circuit 100.
The output end of first low-voltage selection circuit 101 is connected with the third end for connecting circuit 102, and tie point is control electricity
The output end on road 100.
It should be noted that the first low pressure selection circuit 101 in action when, specific effect is: it first is inputted
The low signal of current potential, the signal as its output end between the signal that the termination signal received and its second input terminal receive.
Specific working principle are as follows:
When enable signal PD is shutdown, the current potential of the output end of the analog switching circuit is by under the second NMOS transistor
Drawing is ground level GND, at this point, the current potential of the first input end of control circuit 100, and, the of the first low pressure selection circuit 101
The current potential of one input terminal is also ground level GND.
Because the current potential of the first input end of the first low pressure selection circuit 101 is ground level GND, low pressure selection circuit 101
The second input terminal current potential be the analog switching circuit input terminal input voltage VIN, so the first low pressure selection electricity
Road 101 selects the signal that current potential is low between the input voltage VIN of the input terminal of the analog switching circuit and ground level GND to make
For the signal PW of the output end of the first low pressure selection circuit 101, i.e. PW=min (VIN, GND).
When enable signal PD is conducting, the substrate electric potential PW=VIN+1/2Vds of the first NMOS transistor M1, due to mould
Quasi- switch on-resistance very little, therefore pressure difference Vds very little between the source-drain electrode of the first NMOS transistor M1, so that working as the simulation
When the input voltage VIN of the input terminal of switching circuit is positive voltage, the substrate electric potential PW of the first NMOS transistor M1 is slightly larger than institute
State the input voltage VIN of the input terminal of analog switching circuit；And the input voltage VIN of the input terminal when the analog switching circuit
When for negative voltage, the substrate electric potential PW of the first NMOS transistor M1 is slightly less than the input electricity of the input terminal of the analog switching circuit
Press VIN.Due to pressure difference Vds very little between the source-drain electrode of the first NMOS transistor M1, can be ignored, therefore in circuit drives
The input voltage VIN that its underlayer voltage PW is approximately equal to the input terminal of the analog switching circuit can be regarded as in the process.At this point, electric
Lotus pump circuit 200 works normally, then the control terminal potential of the first NMOS transistor M1, and, the control termination of connection circuit 102
The signal G received is equal to the sum of input voltage VIN and predeterminated voltage VDD of the input terminal of the analog switching circuit, i.e. G
=VIN+VDD.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Optionally, such as Fig. 5, in another embodiment of the invention, a kind of embodiment of connection circuit 102 includes: the
Three NMOS transistor M3 and the 4th NMOS transistor M4；Wherein:
The drain electrode of third NMOS transistor M3 is the second input terminal for connecting circuit 102；
The drain electrode of 4th NMOS transistor M4 is the first input end for connecting circuit 102；
The source electrode and substrate of third NMOS transistor M3, and, the source electrode and substrate of the 4th NMOS transistor M4 are connected
And tie point is the third end for connecting circuit 102；
The grid of third NMOS transistor M3 is connected with the grid of the 4th NMOS transistor M4, and tie point is connection circuit
102 control terminal.
Specific working principle are as follows:
Charge pump circuit 200 works normally, then the first NMOS transistor M1, third NMOS transistor M3 and the 4th NMOS are brilliant
The signal G that the grid of body pipe M4 receives is equal to the input voltage VIN and predeterminated voltage of the input terminal of the analog switching circuit
The sum of VDD, i.e. G=VIN+VDD；And the current potential of the drain electrode of the source electrode and third NMOS transistor M3 of the first NMOS transistor M1 is equal
For the input voltage VIN of the input terminal of the analog switching circuit, so the first NMOS transistor M1 and third NMOS transistor
M3 conducting.
Also, after the first NMOS transistor M1 conducting, the current potential of the input terminal of the analog switching circuit and output end
Current potential is identical, then the current potential of the drain electrode of the 4th NMOS transistor M4 is the input voltage of the input terminal of the analog switching circuit
VIN, and the signal G that the grid of the 4th switch NMOS transistor M4 receives is equal to the defeated of the input terminal of the analog switching circuit
Enter the sum of voltage VIN and predeterminated voltage VDD, i.e. G=VIN+VDD, so the 4th NMOS transistor M4 is connected.
It is to sum up available, when charge pump circuit 200 works normally, the first NMOS transistor M1, third NMOS transistor
M3 and the 4th NMOS transistor M4 are both turned on, and the current potential of the source electrode of the first NMOS transistor M1, drain electrode and substrate is identical.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Optionally, such as Fig. 5, in another embodiment of the invention, a kind of embodiment of the first low pressure selection circuit 101
It include: the 5th NMOS transistor M5 and the 6th NMOS transistor M6；Wherein:
The drain electrode of 5th NMOS transistor M5 is connected with the grid of the 6th NMOS transistor M6, and tie point is the first low-voltage
Second input terminal of selection circuit 101.
The grid of 5th NMOS transistor M5 is connected with the drain electrode of the 6th NMOS transistor M6, and tie point is the first low-voltage
The first input end of selection circuit 101.
The source electrode and substrate of 5th NMOS transistor M5, and, the source electrode and substrate of the 6th NMOS transistor M6 are connected
And tie point is the output end of the first low-voltage selection circuit 101.
Specific working principle are as follows:
When second of current potential less than the first low pressure selection circuit 101 of the first input end of the first low pressure selection circuit 101
When the current potential of input terminal, because the current potential of the grid of the 6th NMOS transistor M6 is the second defeated of the first low pressure selection circuit 101
Enter the current potential at end, and the current potential of the drain electrode of the 6th NMOS transistor M6 is the first input end of the first low pressure selection circuit 101
Current potential, so the current potential of the grid of the 6th NMOS transistor M6 greater than the 6th NMOS transistor M6 drain electrode current potential, so
6th NMOS transistor M6 conducting；Because the current potential of the grid of the 5th NMOS transistor M5 is the first low pressure selection circuit 101
The current potential of first input end, and the current potential of the drain electrode of the 5th NMOS transistor M5 is the second of the first low pressure selection circuit 101
The current potential of input terminal, so the electricity of drain electrode of the current potential of the grid of the 5th NMOS transistor M5 less than the 5th NMOS transistor M5
Position, so the 5th NMOS transistor M5 is turned off.
Because the 5th NMOS transistor M5 is turned off, and the 6th NMOS transistor M6 is connected, so the first low pressure selection circuit
The current potential of the signal PW of 101 output end is the current potential of the first input end of first voltage selection circuit 101.
When the current potential of the first input end of the first low pressure selection circuit 101 is greater than the second of the first low pressure selection circuit 101
When the current potential of input terminal, because the current potential of the grid of the 6th NMOS transistor M6 is the second defeated of the first low pressure selection circuit 101
Enter the current potential at end, and the current potential of the drain electrode of the 6th NMOS transistor M6 is the first input end of the first low pressure selection circuit 101
Current potential, so the current potential of drain electrode of the current potential of the grid of the 6th NMOS transistor M6 less than the 6th NMOS transistor M6, so
The shutdown of 6th NMOS transistor；Because the current potential of the grid of the 5th NMOS transistor M5 is the of the first low pressure selection circuit 101
The current potential of one input terminal, and the current potential of the drain electrode of the 5th NMOS transistor M5 is the second defeated of the first low pressure selection circuit 101
Enter the current potential at end, so the current potential of drain electrode of the current potential of the grid of the 5th NMOS transistor M5 greater than the 5th NMOS transistor M5,
So the 5th NMOS transistor M5 is connected.
Because the 5th NMOS transistor M5 is connected, and the 6th NMOS transistor M6 is turned off, so the first low pressure selection circuit
The current potential of the signal PW of 101 output end is the current potential of the second input terminal of first voltage selection circuit 101.
It is to sum up available, when the current potential of the first input end of the first low pressure selection circuit 101 is selected less than the first low pressure
When the current potential of the second input terminal of circuit 101, the current potential of the signal PW of the output end of the first low pressure selection circuit 101 is the first electricity
Press the current potential of the first input end of selection circuit 101；And when the current potential of the first input end of the first low pressure selection circuit 101 is greater than
When the current potential of the second input terminal of the first low pressure selection circuit 101, the signal PW's of the output end of the first low pressure selection circuit 101
Current potential is the current potential of the second input terminal of first voltage selection circuit 101；For example enable signal PD is shutdown, the analog switch
The current potential of the first input end of the current potential of the output end of circuit and the first low pressure selection circuit 101 is pulled down by the second NMOS transistor
When for ground level GND, if the second input terminal of the current potential of the input terminal of the analog switching circuit and the first low pressure selection circuit 101
Current potential VIN be positive voltage signal, then PW=GND；If the current potential of the input terminal of the analog switching circuit and the selection of the first low pressure
The current potential VIN of second input terminal of circuit 101 is negative voltage signal, then PW=VIN.So the first low pressure selection circuit 101
The low signal of current potential between the signal that the signal PW of output end receives for two input terminals of the first low pressure selection circuit 101.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Optionally, such as Fig. 6, in another embodiment of the invention, a kind of embodiment of charge pump circuit 200 includes:
Generative circuit 201, second voltage selection circuit 202 and the second pull-down circuit 203；Wherein:
The input terminal of generative circuit 201 is connected with the first input end of the second low-voltage selection circuit 202, and tie point is electricity
The input terminal of lotus pump circuit 200；The first end of the output end of generative circuit 201 and the second pull-down circuit 203 is connected, and tie point is
First output end of charge pump circuit 200.
Two power ends of generative circuit 201 connect two inversion clocks respectively；Wherein, the life being connected with inversion clock CLKN
Power end at circuit 201 is the first power end of generative circuit 201, the electricity for the generative circuit 201 being connected with inversion clock CLK
Source is the second source end of generative circuit 201.
Second input end grounding of the second low-voltage selection circuit 202；The output end of second low-voltage selection circuit 202 with
The second end of second pull-down circuit 203 is connected；The control terminal of second pull-down circuit 203 is the control terminal of charge pump circuit 200.
It should be noted that in the second low pressure selection circuit 202, signal and the second input that first input end receives
Terminate the signal that current potential is low between the signal received, the signal GS as its output end.Also, the normal work of charge pump circuit 200
When making, the signal that generative circuit 201 can receive the input terminal of generative circuit 201 is handled, and makes generative circuit 201
The current potential of the signal G of output end increases.In addition, the driving voltage of two inversion clocks is predeterminated voltage VDD.
Specific working principle are as follows:
When enable signal PD is shutdown, the signal PD that the control terminal of the second pull-down circuit 203 receives is high level, electricity
The current potential for the signal PW that the input terminal of lotus pump circuit 200 receives is the input voltage of the input terminal of the analog switching circuit
Lower value between VIN and ground level GND, i.e. PW=min (VIN, GND).
If the input voltage VIN of the input terminal of the analog switching circuit is negative voltage signal, that is, it is less than ground level
GND, i.e. VIN < GND, the then current potential for the signal PW that the input terminal of charge pump circuit 200 receives are the analog switching circuit
The current potential of the input voltage VIN of input terminal, i.e. PW=VIN, the first input end of corresponding second low pressure selection circuit 202 is institute
State the input voltage VIN of the input terminal of analog switching circuit, and the electricity of the second input terminal because of the second low pressure selection circuit 202
Position is ground level GND, so the signal PW that the input terminal of the second low pressure selection circuit 202 selection charge pump circuit 200 receives,
The signal GS of output end as the second low pressure selection circuit 202, i.e. GS=VIN.And the control of the second pull-down circuit 203 at this time
The current potential for terminating the signal PD received is high level, so the electricity for the signal PD that the control terminal of the second pull-down circuit 203 receives
The current potential for the signal GS that the second end that position is greater than the second pull-down circuit 203 receives, i.e. PD > GS, so the second pull-down circuit 203
The current potential of the signal G of the output end of charge pump circuit 200, is pulled down to the input of the input terminal of the analog switching circuit by conducting
Voltage VIN, i.e. G=VIN.
If the input voltage VIN of the input terminal of the analog switching circuit is positive voltage signal, that is, it is greater than ground level
GND, i.e. VIN > GND, the then current potential for the signal PW that the input terminal of charge pump circuit 200 receives are ground level GND, i.e. PW=
GND, the current potential of the first input end of corresponding second low pressure selection circuit 202 are ground level GND, and because the second low pressure selects
The current potential of second input terminal of circuit 202 is ground level GND, so the second low pressure selection circuit 202 is regardless of selection charge pump electricity
The signal PW that the input terminal on road 200 receives, or the letter for selecting the second input terminal of the second low pressure selection circuit 202 to receive
Number, the signal GS of the output end as the second low pressure selection circuit 202, the signal of the output end of the second low pressure selection circuit 202
The current potential of GS is all ground level GND, i.e. GS=GND.And the signal PD that the control terminal of the second pull-down circuit 203 receives at this time
Current potential is high level, so the current potential for the signal PD that the control terminal of the second pull-down circuit 203 receives is greater than the second pull-down circuit
The current potential for the signal GS that 203 second end receives, i.e. PD > GS, so the second pull-down circuit 203 is connected, by charge pump circuit
The current potential of the signal G of 200 output end pulls down to ground level GND, i.e. G=GND.
When enable signal PD is conducting, the current potential for the signal PW that the input terminal of charge pump circuit 200 receives is equal to institute
The input voltage VIN of the output end of analog switching circuit, i.e. PW=VIN are stated, what the control terminal of the second pull-down circuit 203 received
The current potential of signal PD is low level, regardless of the signal GS that the second end of the second pull-down circuit 203 receives is charge pump circuit 200
The signal that receives of the second input terminal of signal PW or the second low pressure selection circuit 202 for receiving of input terminal, under second
Puller circuit 203 is not turned on, it is possible to be simplified charge pump circuit 200, such as Fig. 7.
When the current potential for the signal CLKN that the first power end of generative circuit 201 receives is predeterminated voltage VDD i.e. CLKN=
When the current potential of VDD, the signal CLK that the second source termination of raw circuit 201 receives are 0, i.e. CLK=0, then generative circuit 201
The current potential of the signal G of output end be the current potential of signal PW that the input terminal of power supply pump circuit 200 receives and predeterminated voltage VDD it
With i.e. G=PW+VDD.
When the signal CLKN that the first power end of generative circuit 201 receives current potential be 0, i.e. CLKN=0, generative circuit
When the current potential of signal CLK that 201 second source termination receives is predeterminated voltage VDD, i.e. CLK=VDD, then generative circuit 201
Output end signal G current potential be power supply pump circuit 200 the input terminal current potential of signal PW and predeterminated voltage VDD that receive
The sum of, i.e. G=PW+VDD.
In conclusion the current potential of the signal G of the output end of generative circuit 201 is power supply when enable signal PD is conducting
The sum of current potential and predeterminated voltage VDD of the signal PW that the input terminal of pump circuit 200 receives, i.e. G=PW+VDD.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Optionally, such as Fig. 8, in another embodiment of the invention, a kind of embodiment of generative circuit 201 includes:
Seven NMOS transistor M7, the 8th NMOS transistor M8, the first PMOS transistor P1, the second PMOS transistor P2 and capacitance are identical
First capacitor C1 and the second capacitor C2；Wherein:
The source electrode and substrate of 7th NMOS transistor M7, and, the source electrode and substrate of the 8th NMOS transistor M8 are connected
And tie point is the input terminal of generative circuit 201.
The drain electrode of 7th NMOS transistor M7, the grid of the 8th NMOS transistor M8, one end of first capacitor, the first PMOS
The grid of the source electrode of transistor P1 and the second PMOS transistor P2 are connected, and tie point is the first charge point A.
The drain electrode of 8th NMOS transistor M8, the grid of the 7th NMOS transistor M7, one end of the second capacitor, the 2nd PMOS
The grid of the source electrode of transistor P2 and the first PMOS transistor P1 are connected, and tie point is the second charge point B.
The reversed phase clock CLKN of the other end of first capacitor C1, the reversed phase clock CLK of the other end of the second capacitor；First
The drain electrode of PMOS transistor P1 is connected with the drain electrode of the second PMOS transistor P2, and tie point is the output end of generative circuit 201.
It should be noted that the 7th NMOS transistor M7 and the 8th NMOS transistor M8 are the NMOS with DNW isolation brilliant
Body pipe.
It is selected it should also be noted that, the 7th NMOS transistor M7 and the 8th NMOS transistor M8 composition is similar to the first low pressure
The low pressure selection circuit for selecting circuit 101, when current potential of the current potential of the first charge point A less than the second charge point B, the 7th NMOS is brilliant
Body pipe M7 conducting；When the first charge point A is greater than the second charge point B, the 8th NMOS transistor M8 conducting；In addition, the first PMOS
Transistor P1 and the second PMOS transistor P2 forms high pressure selection circuit, when the current potential of the first charge point A is less than the second charge point B
Current potential when, the second PMOS transistor P2 conducting；When the current potential of the first charge point A is greater than the current potential of the second charge point B, first
PMOS transistor P1 conducting.
For generative circuit 201, the current potential of the signal CLKN that the first power end receives be predeterminated voltage VDD,
When the current potential for the signal CLK that second source termination receives is 0, i.e., when the current potential of the first charge point A is greater than the electricity of the second charge point B
When position, the 8th NMOS transistor M8 conducting, the first PMOS transistor P1 is connected, and the current potential of the first charge point A is charged to generation
The sum of current potential and predeterminated voltage VDD of the signal PW that the input terminal of circuit 201 receives, the current potential of the second charge point B is electrically charged
The current potential of the signal PW received to the input of generative circuit 201, so the signal G that the output end of generative circuit 201 exports
The current potential that current potential is the first charge point A is charged to the current potential of the signal PW that the input terminal of generative circuit 201 receives and default
The sum of voltage VDD, i.e. G=PW+VDD.
When the electricity that the current potential for the signal CLKN that its first power end receives is the signal CLK that 0, second source termination receives
When position is predeterminated voltage VDD, i.e., when current potential of the current potential of the first charge point A less than the second charge point B, the 7th NMOS transistor
M7 conducting, the second PMOS transistor P2 conducting, the input terminal that the current potential of the second charge point B is charged to generative circuit 201 receive
The current potential of the sum of current potential and predeterminated voltage VDD of the signal PW arrived, the first charge point A is charged to the input of generative circuit 201
The current potential of the signal PW received, so the current potential for the signal G that the output end of generative circuit 201 exports is the first charge point A's
The sum of current potential and predeterminated voltage VDD of the signal PW that the input terminal that current potential is charged to generative circuit 201 receives, i.e. G=PW+
VDD。
Optionally, such as Fig. 8, a kind of embodiment of the second low pressure selection circuit 202 include: the 9th NMOS transistor M9 and
Tenth NMOS transistor M10；Wherein:
The drain electrode of 9th NMOS transistor M9 is connected with the grid of the tenth NMOS transistor M10, and tie point is the second low electricity
Press the first input end of selection circuit 202.
The grid of 9th NMOS transistor M9 is connected with the drain electrode of the tenth NMOS transistor M10, and tie point is the second low electricity
Press the second input terminal of selection circuit 202.
The source electrode and substrate of 9th NMOS transistor M9, and, the source electrode and substrate of the tenth NMOS transistor M10, homogeneously
Connect and tie point is the output end of the second low-voltage selection circuit 202.
The specific working principle of second low pressure selection circuit 202 is identical as the first low pressure selection circuit 101, reference can be made to first
The specific working principle of low pressure selection circuit 101, no longer repeats one by one here.
Optionally, such as Fig. 8, a kind of embodiment of the second pull-down circuit 203 includes: the 11st NMOS transistor M11,
Ten bi-NMOS transistor M12 and the 13rd NMOS transistor M13；Wherein:
The drain electrode of 11st NMOS transistor M11 is connected with the first charge point；The drain electrode of tenth bi-NMOS transistor M12 with
Second charge point is connected；The drain electrode of 13rd NMOS transistor M13 is the first end of the second pull-down circuit 203.
The source electrode and substrate and the tenth of the source electrode and substrate of 11st NMOS transistor M11, the tenth bi-NMOS transistor M12
The source electrode of three NMOS transistor M13 is connected with substrate, and tie point is the second end of the second pull-down circuit 203.
The grid and the 13rd NMOS transistor of the grid of 11st NMOS transistor M11, the tenth bi-NMOS transistor M12
The grid of M13 is connected, and tie point is the control terminal of the second pull-down circuit 203.
For the second pull-down circuit 203, when enable signal PD is shutdown, the 11st NMOS transistor M11, the tenth
The current potential for the signal PD that the grid of bi-NMOS transistor M12 and the 13rd NMOS transistor M13 receive is high level, and three
The source potential of person is ground level GND, therefore three is both turned on, respectively by the first charge point A, the second charge point B and second
The current potential of the first end of pull-down circuit 203 pulls down to ground level.
And when enable signal PD is conducting, the 11st NMOS transistor M11, the tenth bi-NMOS transistor M12 and the tenth
The current potential of the grid of three NMOS transistor M13 is low level, and three is turned off at this time.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Optionally, such as Fig. 9, on the basis of above-described embodiment, charge pump circuit 200 further include: high pressure selection circuit
204；Wherein:
The first input end of high voltage selection circuit 204 is connected with the output end of generative circuit 201；High voltage selection circuit
204 the second input end grounding；The substrate and second of the output end of high voltage selection circuit 204 and the first PMOS transistor P1
The substrate of PMOS transistor P2 is connected.
It should be noted that the signal and the second input that first input end receives terminate in high pressure selection circuit 204
The high signal of current potential between the signal received, the signal NW of the output end as high pressure selection circuit 204.
As a kind of implementation, as shown in Figure 10, high pressure selection circuit 204 includes: third PMOS transistor P3 and
Four PMOS transistor P4；Wherein:
The drain electrode of third PMOS transistor P3 is connected with the grid of the 4th PMOS transistor P4, and tie point is high voltage selection
The first input end of circuit 204.
The grid of third PMOS transistor P3 is connected with the drain electrode of the 4th PMOS transistor P4, and tie point is high voltage selection
Second input terminal of circuit 204.
The source electrode and substrate of third PMOS transistor P3, and, the source electrode and substrate of the 4th PMOS transistor P4 are connected
And tie point is the output end of high voltage selection circuit 204.
In high pressure selection circuit 204:
When current potential of the current potential of its first input end less than the second input terminal, the electricity of the grid of the 4th PMOS transistor P4
The current potential of drain electrode of the position less than the 4th PMOS transistor P4, so the 4th PMOS transistor P4 is connected；And third PMOS transistor
The current potential of drain electrode of the current potential of the grid of P3 greater than third PMOS transistor P3, so third PMOS transistor P3 is turned off.At this point,
The current potential of the signal NW of the output end of high pressure selection circuit 204 is the current potential of the second input terminal of high pressure selection circuit 204.
Also, when the current potential of its first input end is greater than the current potential of the second input terminal, the grid of the 4th PMOS transistor P4
The current potential of drain electrode of the current potential of pole greater than the 4th PMOS transistor P4, so the 4th PMOS transistor P4 is turned off；And the 3rd PMOS
The current potential of drain electrode of the current potential of the grid of transistor P3 less than third PMOS transistor P3, so third PMOS transistor P3 is led
It is logical.At this point, the current potential of the signal NW of the output end of high pressure selection circuit 204 is the first input end of high pressure selection circuit 204
Current potential.
In conclusion the signal NW of the output end of high pressure selection circuit 204 is two input terminals of high pressure selection circuit 204
The high signal of current potential between the signal received, i.e. max (G, GND).Therefore, the first PMOS transistor P1 and the 2nd PMOS crystal
The substrate NW of pipe P2 is consistently equal to max (G, GND), it is ensured that under any circumstance, the parasitic body diode of the two will not be just
To conducting, avoids electric leakage or even burn the risk of two pipes.
It should be noted that each MOS transistor in the above embodiments of the present application can also be opened using other kinds of
The way of realization of Guan Guan, each circuit can also be using other topologys or integrated chips etc., as long as being able to achieve corresponding function
, within the scope of protection of this application.
Remaining structure and principle are same as the previously described embodiments, no longer repeat one by one herein.
Each embodiment is described in a progressive manner in the present invention, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method part illustration
?.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention.It is any to be familiar with those skilled in the art
Member, without departing from the scope of the technical proposal of the invention, all using the methods and technical content of the disclosure above to the present invention
Technical solution makes many possible changes and modifications or equivalent example modified to equivalent change.Therefore, it is all without departing from
The content of technical solution of the present invention, according to the technical essence of the invention any simple modification made to the above embodiment, equivalent
Variation and modification, all of which are still within the scope of protection of the technical scheme of the invention.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Claims (13)
1. a kind of analog switching circuit characterized by comprising switching tube, control circuit, the first pull-down circuit and charge pump
Circuit；Wherein:
The control terminal of the charge pump circuit, and, the control terminal of first pull-down circuit, reception enable signal；
The second end of first pull-down circuit is grounded；
The first end of first pull-down circuit, the first input end of the control circuit, and, the first of the switching tube
End, is connected with the output end of the analog switching circuit；
Second input terminal of the control circuit, and, the second end of the switching tube, the input with the analog switching circuit
End is connected；
The output end of the control circuit, and, the third end of the switching tube, with the input terminal phase of the charge pump circuit
Even；
The control terminal phase of first output end of the charge pump circuit and the control terminal of the control circuit and the switching tube
Even；
The switching tube is to control terminal potential to be higher than the switching tube be connected when the second terminal potential；
When the enable signal is shutdown, the second terminal potential of first pull-down circuit is ground level, the control circuit
Output terminal potential be that the input terminal of ground level and the analog switch receives lower value between the voltage value of signal, will be described
First output terminal potential drop-down of charge pump circuit is the lower value, turns off the switching tube；
When the enable signal is conducting, the output terminal potential of the control circuit is equal to the input of the analog switching circuit
The voltage value of the termination collection of letters number, the charge pump circuit works normally and the first output terminal potential is equal to the defeated of the analog switch
The sum of voltage value and the predeterminated voltage for entering the termination collection of letters number, are connected the switching tube.
2. analog switching circuit according to claim 1, which is characterized in that the switching tube is the first NMOS transistor；
The grid of first NMOS transistor is the control terminal of the switching tube；
The drain electrode of first NMOS transistor is the first end of the switching tube；
The source electrode of first NMOS transistor is the second end of the switching tube；
The substrate of first NMOS transistor is the third end of the switching tube.
3. analog switching circuit according to claim 1, which is characterized in that first pull-down circuit includes: second
NMOS transistor；
The grid of second NMOS transistor is the control terminal of first pull-down circuit；
The drain electrode of second NMOS transistor is the first end of first pull-down circuit；
The source electrode of second NMOS transistor is the second end of first pull-down circuit；
The substrate of second NMOS transistor is connected with the second output terminal of the charge pump circuit.
4. analog switching circuit according to claim 1, which is characterized in that the control circuit includes: the first low-voltage
Selection circuit and connection circuit；Wherein:
The control terminal of the connection circuit is the control terminal of the control circuit；
The first input end of the first low-voltage selection circuit is connected with the first input end of the connection circuit, and tie point is
The first input end of the control circuit；
Second input terminal of the first low-voltage selection circuit is connected with the second input terminal of the connection circuit, and tie point is
Second input terminal of the control circuit；
The output end of the first low-voltage selection circuit is connected with the third end of the connection circuit, and tie point is the control
The output end of circuit.
5. analog switching circuit according to claim 4, which is characterized in that the connection circuit includes: the 3rd NMOS crystalline substance
Body pipe and the 4th NMOS transistor；
The drain electrode of the third NMOS transistor is the second input terminal of the connection circuit；
The drain electrode of 4th NMOS transistor is the first input end of the connection circuit；
The source electrode and substrate of the third NMOS transistor, and, the source electrode and substrate of the 4th NMOS transistor are connected
And tie point is the third end of the connection circuit；
The grid of the third NMOS transistor is connected with the grid of the 4th NMOS transistor, and tie point is the connection electricity
The control terminal on road.
6. analog switching circuit according to claim 4, which is characterized in that the first low-voltage selection circuit includes:
5th NMOS transistor and the 6th NMOS transistor；
The drain electrode of 5th NMOS transistor is connected with the grid of the 6th NMOS transistor, and tie point is described first low
Second input terminal of voltage selecting circuit；
The grid of 5th NMOS transistor is connected with the drain electrode of the 6th NMOS transistor, and tie point is described first low
The first input end of voltage selecting circuit；
The source electrode and substrate of 5th NMOS transistor, and, the source electrode and substrate of the 6th NMOS transistor are connected
And tie point is the output end of the first low-voltage selection circuit.
7. -6 any analog switching circuit according to claim 1, which is characterized in that the charge pump circuit includes: life
At circuit, the second low-voltage selection circuit and the second pull-down circuit；Wherein:
The input terminal of the generative circuit is connected with the first input end of the second low-voltage selection circuit, and tie point is described
The input terminal of charge pump circuit；
The output end of the generative circuit is connected with the first end of second pull-down circuit, and tie point is the charge pump circuit
The first output end；
Two power ends of the generative circuit connect two inversion clocks respectively, and the driving voltage of two inversion clocks is described
Predeterminated voltage；
Second input end grounding of the second low-voltage selection circuit；
The output end of the second low-voltage selection circuit is connected with the second end of second pull-down circuit；
The control terminal of second pull-down circuit is the control terminal of the charge pump circuit.
8. analog switching circuit according to claim 7, which is characterized in that the generative circuit includes: the 7th NMOS crystalline substance
Body pipe, the 8th NMOS transistor, the first PMOS transistor, the second PMOS transistor and the identical first capacitor of capacitance and second
Capacitor；
The source electrode and substrate of 7th NMOS transistor, and, the source electrode and substrate of the 8th NMOS transistor are connected
And tie point is the input terminal of the generative circuit；
The drain electrode of 7th NMOS transistor, the grid of the 8th NMOS transistor, the first capacitor one end, described
The source electrode of first PMOS transistor and the grid of second PMOS transistor are connected, and tie point is the first charge point；
The drain electrode of 8th NMOS transistor, the grid of the 7th NMOS transistor, second capacitor one end, described
The source electrode of second PMOS transistor and the grid of first PMOS transistor are connected, and tie point is the second charge point；
One inversion clock of another termination of the first capacitor, another inversion clock of another termination of second capacitor；
The drain electrode of first PMOS transistor is connected with the drain electrode of second PMOS transistor, and tie point is the generation electricity
The output end on road.
9. analog switching circuit according to claim 8, which is characterized in that the 7th NMOS transistor and the described 8th
NMOS transistor is the NMOS transistor with DNW isolation.
10. analog switching circuit according to claim 8, which is characterized in that second pull-down circuit includes: the 11st
NMOS transistor, the tenth bi-NMOS transistor and the 13rd NMOS transistor；
The drain electrode of 11st NMOS transistor is connected with first charge point；
The drain electrode of tenth bi-NMOS transistor is connected with second charge point；
The drain electrode of 13rd NMOS transistor is the first end of second pull-down circuit；
The source electrode and substrate of 11st NMOS transistor, the source electrode of the tenth bi-NMOS transistor and substrate and described
The source electrode of 13 NMOS transistors is connected with substrate, and tie point is the second end of second pull-down circuit；
The grid and the 13rd NMOS crystal of the grid of 11st NMOS transistor, the tenth bi-NMOS transistor
The grid of pipe is connected, and tie point is the control terminal of second pull-down circuit.
11. analog switching circuit according to claim 8, which is characterized in that the charge pump circuit further include: high voltage
Selection circuit；
The first input end of the high voltage selection circuit is connected with the output end of the generative circuit；
Second input end grounding of the high voltage selection circuit；
The substrate and the 2nd PMOS crystal of the output end of the high voltage selection circuit and first PMOS transistor
The substrate of pipe is connected.
12. analog switching circuit according to claim 11, which is characterized in that the high voltage selection includes: third
PMOS transistor and the 4th PMOS transistor；
The drain electrode of the third PMOS transistor is connected with the grid of the 4th PMOS transistor, and tie point is the high voltage
The first input end of selection circuit；
The grid of the third PMOS transistor is connected with the drain electrode of the 4th PMOS transistor, and tie point is the high voltage
Second input terminal of selection circuit；
The source electrode and substrate of the third PMOS transistor, and, the source electrode and substrate of the 4th PMOS transistor are connected
And tie point is the output end of the high voltage selection circuit.
13. analog switching circuit according to claim 7, which is characterized in that the second low-voltage selection circuit includes:
9th NMOS transistor and the tenth NMOS transistor；
The drain electrode of 9th NMOS transistor is connected with the grid of the tenth NMOS transistor, and tie point is described second low
The first input end of voltage selecting circuit；
The grid of 9th NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, and tie point is described second low
Second input terminal of voltage selecting circuit；
The source electrode and substrate of 9th NMOS transistor, and, the source electrode and substrate of the tenth NMOS transistor are connected
And tie point is the output end of the second low-voltage selection circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811561655.0A CN109379071B (en) | 2018-12-20 | 2018-12-20 | Analog switch circuit |
| PCT/CN2019/126251 WO2020125669A1 (en) | 2018-12-20 | 2019-12-18 | Analog switch circuit and charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811561655.0A CN109379071B (en) | 2018-12-20 | 2018-12-20 | Analog switch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109379071A true CN109379071A (en) | 2019-02-22 |
| CN109379071B CN109379071B (en) | 2023-09-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811561655.0A Active CN109379071B (en) | 2018-12-20 | 2018-12-20 | Analog switch circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109379071B (en) |
| WO (1) | WO2020125669A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020125669A1 (en) * | 2018-12-20 | 2020-06-25 | 上海艾为电子技术股份有限公司 | Analog switch circuit and charge pump circuit |
| CN111446948A (en) * | 2020-05-12 | 2020-07-24 | 河北新华北集成电路有限公司 | PMOS drive circuit and drive device |
| CN113839652A (en) * | 2021-09-17 | 2021-12-24 | 广芯电子技术（上海）股份有限公司 | Bidirectional withstand voltage switch circuit and analog switch |
| CN117895932A (en) * | 2024-03-15 | 2024-04-16 | 江苏润石科技有限公司 | Analog switch with turn-off isolation function |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346887B (en) * | 2021-06-10 | 2024-05-14 | 广东大普通信技术有限公司 | Power supply change-over switch, power supply change-over switch circuit and chip |
| CN113765081A (en) * | 2021-09-17 | 2021-12-07 | 深圳南云微电子有限公司 | Gate-source voltage protection circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020125669A1 (en) * | 2018-12-20 | 2020-06-25 | 上海艾为电子技术股份有限公司 | Analog switch circuit and charge pump circuit |
| CN111446948A (en) * | 2020-05-12 | 2020-07-24 | 河北新华北集成电路有限公司 | PMOS drive circuit and drive device |
| CN113839652A (en) * | 2021-09-17 | 2021-12-24 | 广芯电子技术（上海）股份有限公司 | Bidirectional withstand voltage switch circuit and analog switch |
| CN117895932A (en) * | 2024-03-15 | 2024-04-16 | 江苏润石科技有限公司 | Analog switch with turn-off isolation function |
| CN117895932B (en) * | 2024-03-15 | 2024-06-11 | 江苏润石科技有限公司 | Analog switch with turn-off isolation function |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020125669A1 (en) | 2020-06-25 |
| CN109379071B (en) | 2023-09-19 |
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