CN116208133A - Control circuit of maximum voltage selection circuit - Google Patents
Control circuit of maximum voltage selection circuit Download PDFInfo
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- CN116208133A CN116208133A CN202111454265.5A CN202111454265A CN116208133A CN 116208133 A CN116208133 A CN 116208133A CN 202111454265 A CN202111454265 A CN 202111454265A CN 116208133 A CN116208133 A CN 116208133A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The application discloses a control circuit and a method of a maximum voltage selection circuit, wherein the control circuit comprises a comparison module, a current source module, a first inverter, a second inverter and a switch module, wherein the comparison module is connected with one end of the current source module and the first inverter; the first inverter and the second inverter are connected with a switch module, and the switch module is connected with a first voltage V1, a second voltage V2 and an output voltage VOUT node of the maximum voltage selection circuit; the comparison module compares the first voltage V1 with the second voltage V2, and the current source module is combined to realize pull-up or pull-down of the output voltage of the comparison module; the first inverter and the second inverter control the switching module based on the output voltage, so that the output voltage VOUT node of the maximum voltage selection circuit outputs the maximum voltage of the first voltage V1 and the second voltage V2. The invention can turn off the power consumption branch of the control circuit while generating the control signal of the maximum voltage selection circuit, thereby ensuring no quiescent current.
Description
Technical Field
The invention belongs to the technical field of circuit control, and relates to a novel control circuit of a maximum voltage selection circuit.
Background
In a conventional maximum voltage selection circuit, for example, in the process of selecting two different voltages, when two voltages are similar, a comparator is generally added to compare the different voltages in order to increase the driving capability of the output voltage, so as to generate a control signal, and the control signal is used to further drive the MOS transistor to increase the driving capability of the output signal. In particular, in a circuit where two maximum voltages are present, one maximum voltage needs to be selected to power the subsequent part of the circuit of the chip. The conventional simple maximum voltage selection circuit is shown in fig. 1 and consists of MP1 and MP 2. The grid electrode of MP1 is connected with the drain electrode of MP2, the voltage is V1, and the grid electrode of MP2 tube is connected with the drain electrode of MP1, the voltage is V2. When V1 > V2, MP2 is on and vout=v1. When V2 > V1, MP1 is on and vout=v2. Since MP1 and MP2 are well turned on, a certain condition is required, i.e., |vgs| > |vth|. So when V1 and V2 differ little, one of MP1 and MP2 is weakly conductive, resulting in weak driving capability of VOUT.
In order to solve the above problem, a comparator is generally added to compare V1 and V2 to generate a control signal, and the control signal is used to further drive the PMOS transistor to increase the driving capability of the output signal VOUT. However, this approach typically introduces a quiescent current because of the addition of the comparator module. Under certain operating conditions, it is desirable to have no quiescent current, which is generally difficult due to the introduction of the comparator.
In particular, in some applications, the chip is required to be free of quiescent current. The working state of the device can have two conditions, one is that under normal working conditions, V1 is more than or equal to V2. Another condition is that v1=0 and V2 is set to a voltage value greater than 0, such as any voltage value of 1.8V to 5.5V in low voltage applications. Under both conditions, the chip is required to have no quiescent current, and at this time, a comparator is introduced to compare different voltages of the maximum voltage selection circuit so as to generate a control signal, and the control signal is used for further driving the MOS tube, so that the scheme of increasing the driving capability of the output signal is not applicable any more.
Disclosure of Invention
In order to solve the defects in the prior art, the application provides a novel control circuit of a maximum voltage selection circuit.
In order to achieve the above object, the present invention adopts the following technical scheme:
a control circuit of a maximum voltage selection circuit comprises a comparison module, a current source module, a first inverter, a second inverter and a switch module;
the comparison module is respectively connected with one end of the current source module and the first inverter, and the other end of the current source module is connected with GND;
the first inverter and the second inverter are connected with a switch module, and the switch module is connected with a first voltage V1, a second voltage V2 and an output voltage VOUT node of the maximum voltage selection circuit;
the comparison module is used for comparing the first voltage V1 with the second voltage V2, and the current source module is combined to realize the pull-up or pull-down of the voltage of the output node B of the comparison module;
the first inverter and the second inverter are used for controlling the switch module based on the voltage of the output node B, so that the maximum voltage of the first voltage V1 and the second voltage V2 is output by the output voltage VOUT node of the maximum voltage selection circuit.
The invention further comprises the following preferable schemes:
preferably, the maximum voltage selection circuit comprises PMOS tubes MP1 and MP2;
the grid electrode of the MP1 is connected with the drain electrode of the MP2, the voltage of the connecting point is V1, the grid electrode of the MP2 tube is connected with the drain electrode of the MP1, and the voltage of the connecting point is V2;
the sources of MP1 and MP2 are connected, and the voltage of the connection point is the output voltage VOUT.
Preferably, the comparison module comprises a PMOS tube MP3 and an NMOS tube MN1;
the grid electrodes of the MP3 and the MN1 are connected with the V1, the connection point is a node A, the drain electrodes of the MP3 and the MN1 are connected with the first inverter, and the connection point is an output node B;
the source of MP3 is connected to V2 and the source of MN1 is connected to the current source module.
Preferably, the current source module comprises an NMOS tube MN2 and a resistor R1;
the drain of MN2 is connected with the source of MN1, the source of MN2 is connected with one end of a resistor R1, and the other end of R1 is connected with GND together with the gate of MN 2.
Preferably, the first inverter includes a PMOS transistor MP4 and an NMOS transistor MN3;
the grid electrodes of MP4 and MN3 are connected with an output node B, the drain electrode is connected with a node C, and the node C is an output node of the first inverter;
the source of MP4 connects the second inverter and the switch module, and the source of MN3 is grounded.
Preferably, the second inverter includes a PMOS transistor MP5 and an NMOS transistor MN4;
the grid electrodes of MP5 and MN4 are connected with a node C, the drain electrode is connected with a node D, and the node D is an output node of the second inverter;
the source of MP5 is connected with the source of MP4 and the switch module, and the source of MN4 is grounded.
Preferably, the switch module comprises PMOS tubes MP6 and MP7;
the gates of MP6 and MP7 are connected with node D and node C respectively, the sources of MP6 and MP7 are connected with the source of MP5 and the output voltage VOUT simultaneously, and the drains are connected with V1 and V2 respectively.
Preferably, the control method of the maximum voltage selection circuit based on the control circuit of the maximum voltage selection circuit specifically includes:
the comparison module inputs a first voltage V1 and a second voltage V2;
when V1 is more than or equal to V2, the comparison module and the current source module pull down the voltage of the output node B of the comparison module to GND;
the voltage of the output node B passes through the first inverter and the second inverter and then controls the switch module to enable the output voltage VOUT=V1;
when V1 is less than V2, the comparing module and the current source module pull up the voltage of the output node B of the comparing module to V2, and the voltage of the output node B passes through the first inverter and the second inverter and then controls the switching module to enable the output voltage vout=v2.
Preferably, the control method of the maximum voltage selection circuit based on the control circuit of the maximum voltage selection circuit specifically includes:
the sources of the nodes A and MP3 are respectively input with V1 and V2;
when V1 is more than or equal to V2, MP3 is turned off, MN1 is turned on, and MN1, MN2 and R1 pull down the output node B to GND;
after the voltage of the output node B passes through the first inverter, the voltage of the output node C becomes VOUT, and the grid electrode of MP7 is controlled to turn off MP7;
after the voltage of the output node C passes through the second inverter, the voltage of the output node D becomes GND, the grid electrode of MP6 is controlled, MP6 is conducted, and VOUT=V1;
when V1 is less than V2, MP3 is conducted, the voltage of node B is pulled up to V2, and after the voltage passes through the first inverter and the second inverter, the voltage of the output node C is GND, and the voltage of the node D is VOUT;
the voltage at output node C turns MP7 on, vout=v2, and the voltage at node D turns MP6 off.
Preferably, when v1=0, V2 is set to a voltage value greater than 0.
The beneficial effect that this application reached:
the invention can turn off the power consumption branch of the control circuit while generating the control signal of the maximum voltage selection circuit, thereby ensuring no quiescent current.
Drawings
FIG. 1 is a block diagram of a conventional maximum voltage selection circuit;
fig. 2 is a control circuit configuration diagram of a maximum voltage selection circuit according to the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.
As shown in fig. 2, a control circuit of a maximum voltage selection circuit of the present invention includes a comparison module, a current source module, a first inverter, a second inverter and a switch module;
the comparison module is respectively connected with one end of the current source module and the first inverter, and the other end of the current source module is connected with GND;
the first inverter and the second inverter are connected with a switch module, and the switch module is connected with a first voltage V1, a second voltage V2 and an output voltage VOUT node of the maximum voltage selection circuit;
the comparison module is used for comparing the first voltage V1 with the second voltage V2, and the current source module is combined to realize the pull-up or pull-down of the voltage of the output node B of the comparison module;
the first inverter and the second inverter are used for controlling the switch module based on the voltage of the output node B, so that the maximum voltage of the first voltage V1 and the second voltage V2 is output by the output voltage VOUT node of the maximum voltage selection circuit.
In specific implementation, the comparison module inputs a first voltage V1 and a second voltage V2;
when V1 is more than or equal to V2, the comparison module and the current source module pull down the voltage of the output node B of the comparison module to GND;
the voltage of the output node B passes through the first inverter and the second inverter and then controls the switch module to enable the output voltage VOUT=V1;
when V1 is less than V2, the comparing module and the current source module pull up the voltage of the output node B of the comparing module to V2, and the voltage of the output node B passes through the first inverter and the second inverter and then controls the switching module to enable the output voltage vout=v2.
In practice, the control circuit in the left-hand dashed box of fig. 2 is added to the maximum voltage selection circuit shown in fig. 1.
The maximum voltage selection circuit comprises PMOS tubes MP1 and MP2;
the grid electrode of the MP1 is connected with the drain electrode of the MP2, the voltage of the connecting point is V1, the grid electrode of the MP2 tube is connected with the drain electrode of the MP1, and the voltage of the connecting point is V2;
the sources of MP1 and MP2 are connected, and the voltage of the connection point is the output voltage VOUT.
The comparison module comprises a PMOS tube MP3 and an NMOS tube MN1;
the grid electrodes of the MP3 and the MN1 are connected with the V1, the connection point is a node A, the drain electrodes of the MP3 and the MN1 are connected with the first inverter, and the connection point is an output node B;
the source of MP3 is connected to V2 and the source of MN1 is connected to the current source module.
The current source module comprises an NMOS tube MN2 and a resistor R1;
the drain of MN2 is connected with the source of MN1, the source of MN2 is connected with one end of a resistor R1, and the other end of R1 is connected with GND together with the gate of MN 2.
The transistor MN2 is a Native type NMOS transistor, and has a negative threshold voltage, so that the gate thereof is connected to GND and is normally turned on.
The MN2 is connected in series with a resistor R1 from the source to the GND, and a circuit formed by MN2 and R1 is a current source with pull-down capability.
The first inverter comprises a PMOS tube MP4 and an NMOS tube MN3;
the grid electrodes of MP4 and MN3 are connected with an output node B, the drain electrode is connected with a node C, and the node C is an output node of the first inverter;
the source of MP4 connects the second inverter and the switch module, and the source of MN3 is grounded.
The second inverter comprises a PMOS tube MP5 and an NMOS tube MN4;
the grid electrodes of MP5 and MN4 are connected with a node C, the drain electrode is connected with a node D, and the node D is an output node of the second inverter;
the source of MP5 is connected with the source of MP4 and the switch module, and the source of MN4 is grounded.
The switch module comprises PMOS tubes MP6 and MP7;
the gates of MP6 and MP7 are connected with node D and node C respectively, the sources of MP6 and MP7 are connected with the source of MP5 and the output voltage VOUT simultaneously, and the drains are connected with V1 and V2 respectively.
The control method of the maximum voltage selection circuit based on the control circuit specifically comprises the following steps:
the sources of the nodes A and MP3 are respectively input with V1 and V2;
when V1 is more than or equal to V2, MP3 is turned off, MN1 is turned on, MN1, MN2 and R1 pull down the output node B to GND, and the branch has no quiescent current;
after the voltage of the output node B passes through a first inverter consisting of MP4 and MN3, the voltage of the output node C becomes VOUT, and the grid electrode of MP7 is controlled to turn off MP7;
after the voltage of the output node C passes through the second inverter consisting of MP5 and MN4, the voltage of the output node D becomes GND, controlling the gate of MP6, MP6 being turned on, vout=v1.
Thus, under this operating condition, VOUT still has a strong driving capability and the control circuit has no quiescent current because of the introduction of MP6 even when output V2 is close to V1.
When v1=0, V2 is set to a voltage value greater than 0, such as any voltage value of 1.8V to 5.5V in low voltage applications. Since v1=0, MN1 turns off, the network of MN1, MN2 and R1 has no pull-down capability, and this branch has no quiescent current.
When V1 is less than V2, MP3 is conducted, the voltage of node B is pulled up to V2, and after the voltage passes through the first inverter and the second inverter, the voltage of the output node C is GND, and the voltage of the node D is VOUT;
the voltage at output node C turns MP7 on, vout=v2, and the voltage at node D turns MP6 off.
The invention ensures that the VOUT correctly selects larger voltage in V1 and V2 under different working conditions, has strong driving capability and ensures no static current.
The invention can turn off the power consumption branch of the control circuit while generating the control signal of the maximum voltage selection circuit, thereby ensuring no quiescent current.
While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.
Claims (10)
1. The utility model provides a control circuit of maximum voltage selection circuit, includes comparison module, current source module, first inverter, second inverter and switch module, its characterized in that:
the comparison module is respectively connected with one end of the current source module and the first inverter, and the other end of the current source module is connected with GND;
the first inverter and the second inverter are connected with a switch module, and the switch module is connected with a first voltage V1, a second voltage V2 and an output voltage VOUT node of the maximum voltage selection circuit;
the comparison module is used for comparing the first voltage V1 with the second voltage V2, and the current source module is combined to realize the pull-up or pull-down of the voltage of the output node B of the comparison module;
the first inverter and the second inverter are used for controlling the switch module based on the voltage of the output node B, so that the maximum voltage of the first voltage V1 and the second voltage V2 is output by the output voltage VOUT node of the maximum voltage selection circuit.
2. The control circuit of a maximum voltage selection circuit according to claim 1, wherein:
the maximum voltage selection circuit comprises PMOS tubes MP1 and MP2;
the grid electrode of the MP1 is connected with the drain electrode of the MP2, the voltage of the connecting point is V1, the grid electrode of the MP2 tube is connected with the drain electrode of the MP1, and the voltage of the connecting point is V2;
the sources of MP1 and MP2 are connected, and the voltage of the connection point is the output voltage VOUT.
3. A control circuit for a maximum voltage selection circuit as claimed in claim 2, wherein:
the comparison module comprises a PMOS tube MP3 and an NMOS tube MN1;
the grid electrodes of the MP3 and the MN1 are connected with the V1, the connection point is a node A, the drain electrodes of the MP3 and the MN1 are connected with the first inverter, and the connection point is an output node B;
the source of MP3 is connected to V2 and the source of MN1 is connected to the current source module.
4. A control circuit for a maximum voltage selection circuit according to claim 3, wherein:
the current source module comprises an NMOS tube MN2 and a resistor R1;
the drain of MN2 is connected with the source of MN1, the source of MN2 is connected with one end of a resistor R1, and the other end of R1 is connected with GND together with the gate of MN 2.
5. The control circuit of a maximum voltage selection circuit according to claim 4, wherein:
the first inverter comprises a PMOS tube MP4 and an NMOS tube MN3;
the grid electrodes of MP4 and MN3 are connected with an output node B, the drain electrode is connected with a node C, and the node C is an output node of the first inverter;
the source of MP4 connects the second inverter and the switch module, and the source of MN3 is grounded.
6. The control circuit of a maximum voltage selection circuit according to claim 5, wherein:
the second inverter comprises a PMOS tube MP5 and an NMOS tube MN4;
the grid electrodes of MP5 and MN4 are connected with a node C, the drain electrode is connected with a node D, and the node D is an output node of the second inverter;
the source of MP5 is connected with the source of MP4 and the switch module, and the source of MN4 is grounded.
7. The control circuit of a maximum voltage selection circuit according to claim 6, wherein:
the switch module comprises PMOS tubes MP6 and MP7;
the gates of MP6 and MP7 are connected with node D and node C respectively, the sources of MP6 and MP7 are connected with the source of MP5 and the output voltage VOUT simultaneously, and the drains are connected with V1 and V2 respectively.
8. A control method of a maximum voltage selection circuit based on a control circuit of a maximum voltage selection circuit according to any one of claims 1 to 7, characterized by:
the control method specifically comprises the following steps:
the comparison module inputs a first voltage V1 and a second voltage V2;
when V1 is more than or equal to V2, the comparison module and the current source module pull down the voltage of the output node B of the comparison module to GND;
the voltage of the output node B passes through the first inverter and the second inverter and then controls the switch module to enable the output voltage VOUT=V1;
when V1 is less than V2, the comparing module and the current source module pull up the voltage of the output node B of the comparing module to V2, and the voltage of the output node B passes through the first inverter and the second inverter and then controls the switching module to enable the output voltage vout=v2.
9. A control method of the maximum voltage selection circuit based on the control circuit of the maximum voltage selection circuit according to claim 7, characterized by:
the method specifically comprises the following steps:
the sources of the nodes A and MP3 are respectively input with V1 and V2;
when V1 is more than or equal to V2, MP3 is turned off, MN1 is turned on, and MN1, MN2 and R1 pull down the output node B to GND;
after the voltage of the output node B passes through the first inverter, the voltage of the output node C becomes VOUT, and the grid electrode of MP7 is controlled to turn off MP7;
after the voltage of the output node C passes through the second inverter, the voltage of the output node D becomes GND, the grid electrode of MP6 is controlled, MP6 is conducted, and VOUT=V1;
when V1 is less than V2, MP3 is conducted, the voltage of node B is pulled up to V2, and after the voltage passes through the first inverter and the second inverter, the voltage of the output node C is GND, and the voltage of the node D is VOUT;
the voltage at output node C turns MP7 on, vout=v2, and the voltage at node D turns MP6 off.
10. The control method of a maximum voltage selection circuit according to claim 9, wherein:
when v1=0, V2 is set to a voltage value greater than 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111454265.5A CN116208133A (en) | 2021-12-01 | 2021-12-01 | Control circuit of maximum voltage selection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111454265.5A CN116208133A (en) | 2021-12-01 | 2021-12-01 | Control circuit of maximum voltage selection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN116208133A true CN116208133A (en) | 2023-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111454265.5A Pending CN116208133A (en) | 2021-12-01 | 2021-12-01 | Control circuit of maximum voltage selection circuit |
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| CN (1) | CN116208133A (en) |
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2021
- 2021-12-01 CN CN202111454265.5A patent/CN116208133A/en active Pending
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