CN110729999B - Mode control circuit and apparatus - Google Patents

Mode control circuit and apparatus Download PDF

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Publication number
CN110729999B
CN110729999B CN201910843307.0A CN201910843307A CN110729999B CN 110729999 B CN110729999 B CN 110729999B CN 201910843307 A CN201910843307 A CN 201910843307A CN 110729999 B CN110729999 B CN 110729999B
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circuit
switching tube
voltage
latch circuit
latch
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CN110729999A (en
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张潜龙
张维琛
刘泰源
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Electronic Switches (AREA)

Abstract

The embodiment of the invention provides a mode control circuit and a mode control device. The circuit comprises: the circuit comprises a detection circuit, a latch circuit and a pull-up and pull-down circuit, wherein the pull-up and pull-down circuit comprises a voltage pull-up circuit and a voltage pull-down circuit; the detection circuit is used for detecting whether DVDD is powered down; the latch circuit is used for controlling the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to be related to the pull-up circuit after DVDD is powered down; the voltage pull-up circuit is used for pulling up the power voltage of the normally-on region of the first output end of the latch circuit, so that the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a power-down mode; the voltage pull-Down circuit is used for pulling Down the voltage of the second output end of the latch circuit to the ground, so that the controlled circuit, such as an ADC circuit, enters a Power Down mode after DVDD is powered Down, thereby avoiding unnecessary Power consumption of the controlled circuit and preventing electric leakage of the input end of the controlled circuit.

Description

Mode control circuit and apparatus
Technical Field
Embodiments of the present invention relate to communication technologies, and in particular, to a mode control circuit and device.
Background
Analog-to-Digital Converter (ADC) is often used in battery voltage monitoring, key identification, sensors, etc., and the ADC may be integrated into some processing chips for enabling control by the corresponding processing chip. In the above-mentioned battery voltage monitoring, key identification, sensor, etc., when both the digital power supply and the analog power supply of the chip are powered down, since the digital power supply is the power supply that generates the signal for controlling the operation mode of the ADC, after the DVDD of the chip is powered down, the current mode of the ADC enters an uncertain state, for example, after the DVDD is powered down, the ADC is still in the normal operation mode (normal), so as to generate corresponding power consumption. As shown in fig. 1, both the digital power supply DVDD and the analog power supply AVDD of the ADC are powered down, the current mode of the ADC enters an uncertain state, and since the N-well potential in the ADC is changed from high voltage to zero, the P-type Metal-Oxide-semiconductor field effect transistor (MOSFET) substrate serving as a transmission gate has no high voltage, leading to forward bias of the PN junction, and at this time, current flowing backward from the ADC input terminal to the ADC interior (ADC CORE in the figure is an ADC CORE) is generated, forming a current loop from the device under test (Device Under Test, DUT) to the N-well in the ADC interior, thereby leading to leakage current in standby.
Therefore, how to ensure that the ADC circuit can correctly enter the Power Down mode when the DVDD is powered Down, and that no leakage current at the input end of the ADC is generated is a technical problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a mode control circuit and equipment, which are used for solving the technical problems that an ADC circuit cannot accurately enter a Power Down mode when DVDD is powered Down so as to generate corresponding Power consumption and input electric leakage of the ADC circuit in the prior art.
In a first aspect, an embodiment of the present invention provides a mode control circuit, including: the circuit comprises a detection circuit, a latch circuit and a pull-up circuit, wherein the pull-up circuit comprises a voltage pull-up circuit and a voltage pull-down circuit; wherein,
the first input end of the detection circuit is connected with a digital power DVDD, the second input end of the detection circuit is connected with a power-off control input end, the first output end of the detection circuit is connected with a first control end of the latch circuit, the second output end of the detection circuit is connected with a second control end of the latch circuit, the power-off control input end is connected with a third control end of the latch circuit, the first end of the voltage pull-up circuit is connected with a power supply of a normally-on region, the second end of the voltage pull-up circuit is connected with the first output end of the latch circuit, the first end of the voltage pull-down circuit is connected with the second output end of the latch circuit, and the second end of the voltage pull-down circuit is grounded;
The detection circuit is used for detecting whether the DVDD is powered down or not;
the latch circuit is used for controlling the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to be related to the pull-up and pull-down circuit after the detection circuit detects that the DVDD is powered down;
the voltage pull-up circuit is used for pulling up the voltage of the first output end of the latch circuit to be the power supply voltage of the normally-on area so as to control the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to enter a locking state and enable the first output end of the latch circuit to output a control signal for controlling the controlled circuit to enter a power-down mode;
the voltage pull-down circuit is used for pulling down the voltage of the second output end of the latch circuit to the ground so as to control the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to enter a locking state.
The controlled circuit can be an ADC circuit in a chip or a dual-power supply circuit. The Power-Down mode may be a Power Down mode, or a sleep mode, a standby mode, or the like. The pull-down or pull-up referred to above refers to the rise or fall of the voltage.
Through the mode control circuit provided by the first aspect, after the detection circuit detects that the DVDD is powered Down, the voltages of the first output end of the latch circuit and the second output end of the latch circuit are automatically triggered to be associated with the pull-up and pull-Down circuit, so that the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit enter a locking state under the action of the pull-up and pull-Down circuit, the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a Power-Down mode, and the controlled circuit is controlled to enter a Power Down mode. The circuit provided by the embodiment of the invention can enable the controlled circuit such as an ADC circuit to enter a Power Down mode after DVDD is powered Down, thereby avoiding unnecessary Power consumption of the controlled circuit; in addition, the circuit provided by the embodiment of the invention can trigger the subsequent controlled circuit to automatically enter the Power Down mode after DVDD is powered Down only by connecting the corresponding detection circuit under DVDD, and an additional trigger circuit such as a circuit for generating an isolation signal Viso is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; further, the mode control circuit in the embodiment can be connected with a power supply of a normally-on region, so that PN junction reverse bias of a PMOS tube serving as a transmission gate is ensured, electric leakage of an input end of the mode control circuit is avoided, and reliability of the circuit is ensured.
In one possible design, the detection circuit includes a first switching tube and an inverter; the first input end of the detection circuit is connected with the digital power supply DVDD, the second input end of the detection circuit is connected with the power-off control input end, the first output end of the detection circuit is connected with the first control end of the latch circuit, and the second output end of the detection circuit is connected with the second control end of the latch circuit, and the method specifically comprises the following steps:
the grid electrode of the first switching tube is connected with the power-off control input end, the source electrode of the first switching tube is connected with the first control end of the latch circuit, and the drain electrode of the first switching tube is respectively connected with the DVDD and the first input end of the inverter;
and a second input end of the inverter is connected with the power-off control input end, and an output end of the inverter is connected with a second control end of the latch circuit.
In one possible design, the inverter includes a second switching tube and a third switching tube; the drain electrode of the first switching tube is connected with the first input end of the inverter, the second input end of the inverter is connected with the power-off control input end, and the output end of the inverter is connected with the second control end of the latch circuit, specifically:
The drain electrode of the first switching tube is connected with the source electrode of the second switching tube, the grid electrode of the second switching tube and the grid electrode of the third switching tube are respectively connected with the power-off control input end, the drain electrode of the second switching tube is connected with the drain electrode of the third switching tube and respectively connected with the second control end of the latch circuit, and the source electrode of the third switching tube is grounded.
In one possible design, the voltage pull-up circuit includes a fourth switching tube and the voltage pull-down circuit includes a fifth switching tube; the first end of the voltage pull-up circuit is connected with a power supply of a normally-on area, the second end of the voltage pull-up circuit is connected with the first output end of the latch circuit, the first end of the voltage pull-down circuit is connected with the second output end of the latch circuit, and the second end of the voltage pull-down circuit is grounded specifically:
the source electrode of the fourth switching tube is connected with the power supply of the normally-on region, the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube, and the drain electrode of the fourth switching tube is connected with the first output end of the latch circuit;
the grid electrode of the fifth switching tube is connected with the drain electrode of the fifth switching tube, the source electrode of the fifth switching tube is grounded, and the drain electrode of the fifth switching tube is connected with the second output end of the latch circuit.
In one possible design, the latch circuit includes a first switch circuit, a second switch circuit, and a latch circuit; the first switching circuit comprises a sixth switching tube and a seventh switching tube, the second switching circuit comprises an eighth switching tube and a ninth switching tube, and the latch circuit comprises a tenth switching tube and an eleventh switching tube;
the grid electrode of the sixth switching tube and the grid electrode of the eighth switching tube are respectively connected with the source electrode of the first switching tube, the source electrode of the sixth switching tube is connected with the drain electrode of the seventh switching tube, the drain electrode of the sixth switching tube is connected with the drain electrode of the tenth switching tube, the grid electrode of the seventh switching tube is respectively connected with the drain electrode of the second switching tube and the drain electrode of the third switching tube, and the source electrode of the seventh switching tube is grounded;
the source electrode of the eighth switching tube is connected with the drain electrode of the ninth switching tube, the drain electrode of the eighth switching tube is connected with the drain electrode of the eleventh switching tube, the grid electrode of the ninth switching tube is connected with the power failure control input end, and the source electrode of the ninth switching tube is grounded;
the source electrode of the tenth switching tube and the source electrode of the eleventh switching tube are respectively connected with a power supply of a normally-on region, the grid electrode of the tenth switching tube is connected with the drain electrode of the eleventh switching tube, the drain electrode of the tenth switching tube is respectively connected with the drain electrode of the fourth switching tube and the grid electrode of the eleventh switching tube, and the drain electrode of the eleventh switching tube is connected with the drain electrode of the fifth switching tube.
In one possible design, the first switching circuit further comprises a twelfth switching tube, and the second switching circuit further comprises a thirteenth switching tube;
the drain electrode of the sixth switching tube is connected with the drain electrode of the tenth switching tube, and specifically comprises:
the drain electrode of the sixth switching tube is connected with the source electrode of the twelfth switching tube, the drain electrode of the twelfth switching tube is connected with the drain electrode of the tenth switching tube, and the grid electrode of the twelfth switching tube is connected with the grid electrode of the seventh switching tube;
the drain electrode of the eighth switching tube is connected with the drain electrode of the eleventh switching tube, and specifically comprises:
the drain electrode of the eighth switching tube is connected with the source electrode of the thirteenth switching tube, the drain electrode of the thirteenth switching tube is connected with the drain electrode of the eleventh switching tube, and the grid electrode of the thirteenth switching tube is connected with the grid electrode of the ninth switching tube.
The mode control circuit provided by the above possible designs can enable the controlled circuit such as an ADC circuit to enter a Power Down mode after DVDD is powered Down, thereby avoiding unnecessary Power consumption of the controlled circuit and saving the Power consumption overhead of the whole system; in addition, in the state of no external control signal, the circuit provided by the embodiment of the invention can automatically trigger the subsequent controlled circuit to automatically enter the Power Down mode after the DVDD is powered Down by only connecting the corresponding detection circuit under the DVDD, and an additional trigger circuit is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; furthermore, the mode control circuit provided by the embodiment of the invention can not generate leakage current under the condition of DVDD power-down, so that the reliability of the whole circuit is ensured.
In a second aspect, an embodiment of the present invention provides an apparatus, including a controlled circuit, further including: a mode control circuit as claimed in any one of claims 1 to 6;
the mode control circuit is connected with the controlled circuit.
The advantages of the device provided by this second aspect may be seen in the above-mentioned first aspect and in each possible design of the first aspect, which are not described in detail here.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a chip according to an embodiment of the present invention when the chip enters a sleep state;
FIG. 2 is a schematic block diagram of a mode control circuit for an ADC circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a first embodiment of a mode control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a second embodiment of a mode control circuit according to the present invention;
FIG. 5 is a schematic circuit diagram of a third embodiment of a mode control circuit according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a fourth embodiment of a mode control circuit according to the present invention;
fig. 7 is a schematic diagram of an embodiment of an apparatus provided in an embodiment of the present invention.
Reference numerals illustrate:
10: a detection circuit; 11: a latch circuit; 12: a pull-up and pull-down circuit;
101: a first input of the detection circuit; 102: a second input of the detection circuit;
13: a power-off control input; 103: a first output of the detection circuit;
104: a second output of the detection circuit; 111: a first control terminal of the latch circuit;
112: a second control terminal of the latch circuit; 113: a third control terminal of the latch circuit;
114: a first output of the latch circuit; 115: a second output of the latch circuit;
121: a voltage pull-up circuit; 122: a voltage pull-down circuit;
1211: a first end of the circuit pull-up circuit; 1212: a second end of the voltage pull-up circuit;
1221: a first end of the voltage pull-down circuit; 1222: a second end of the voltage pull-down circuit;
105: an inverter; 1051: a first input of the inverter;
1052: a second input of the inverter; 1053: an output of the inverter;
M1: a first switching tube; m2: a second switching tube; m3: a third switching tube;
m4: a fourth switching tube; m5: a fifth switching tube; m6: a sixth switching tube;
m7: a seventh switching tube; m8: an eighth switching tube; m9: a ninth switching tube;
m10: a tenth switching tube; m11: an eleventh switching tube; m12: a twelfth switching tube;
m13: a thirteenth switching tube; 116: a first switching circuit; 117: a second switching circuit;
118: a latch circuit; 20: a controlled circuit; 21: a mode control circuit;
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The mode control circuit related to the embodiment of the invention can be used for controlling any controlled circuit which enters an uncertain state after the digital power DVDD is powered down, such as an ADC circuit in a chip or a dual power supply circuit. The mode control circuit can control the controlled circuit to enter a power-down mode along with the power-down of the DVDD after the DVDD is powered down, so that the generation of extra power consumption is avoided. Taking the controlled circuit as an ADC circuit as an example, the schematic block diagram of the mode control circuit acting on the ADC circuit can be seen in fig. 2, the mode control circuit and the digital power supply DVDD are the power supply of the normal power-on region, and after the DVDD is powered down, the mode control circuit is provided with an analog power supply voltage, so that the PN junction of the PMOS transistor in fig. 2 is reversed biased, and no leakage current is generated at the input end of the ADC circuit. It should be noted that, the signal for controlling the ADC circuit to enter the Power Down mode is generated by the digital Power supply DVDD, and the ADC circuit in the prior art enters the uncertain state when the DVDD is powered Down, but in the embodiment of the present invention, the ADC circuit automatically enters the Power Down mode when the DVDD is powered Down, which is described in detail in the following embodiments.
In addition, the embodiment of the invention relates to a Power-Down mode, which can be a Power Down mode; the power-down control input terminal may be a Power Down control input terminal, and the voltage of the power-down control input terminal is low when the digital power supply DVDD in the circuit where the mode control circuit according to the embodiment of the present invention is located is powered down. Optionally, when the digital power supply DVDD in the circuit where the mode control circuit according to the embodiment of the present invention is located is electrified, the voltage at the power-off control input terminal may be a high potential or a low potential. When the DVDD is electrified and the voltage of the Power-off control input end is high, the mode control circuit outputs high potential and controls the controlled circuit to enter a Power Down mode, and when the DVDD is electrified and the voltage of the Power-off control input end is low, the mode control circuit outputs low potential and controls the controlled circuit to work normally.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 3 is a circuit schematic diagram of a first embodiment of a mode control circuit according to an embodiment of the present invention. The present embodiment relates to a specific process of ensuring that the first output terminal 114 of the latch circuit 11 outputs a control signal to control the controlled circuit to enter the Power Down mode through the latch circuit 11 and the pull-up/Down circuit 12 after the detection circuit 10 detects the DVDD Power-Down. As shown in fig. 3, the mode control circuit may include: the circuit comprises a detection circuit 10, a latch circuit 11 and a pull-up and pull-down circuit 12, wherein the pull-up and pull-down circuit 12 comprises a voltage pull-up circuit 121 and a voltage pull-down circuit 122.
The first input terminal 101 of the detection circuit 10 is connected to a digital power supply DVDD, the second input terminal 102 of the detection circuit 10 is connected to a power-down control input terminal 13, the first output terminal 103 of the detection circuit 10 is connected to the first control terminal 111 of the latch circuit 11, the second output terminal 104 of the detection circuit 10 is connected to the second control terminal 112 of the latch circuit 11, the power-down control input terminal 13 is connected to the third control terminal 113 of the latch circuit 11, the first terminal 1211 of the voltage pull-up circuit 121 is connected to a power supply of a normally-on region, the second terminal 1212 of the voltage pull-up circuit 121 is connected to the first output terminal 114 of the latch circuit 11, the first terminal 1221 of the voltage pull-down circuit 122 is connected to the second output terminal 115 of the latch circuit 11, and the second terminal 1222 of the voltage pull-down circuit 122 is grounded;
the detection circuit 10 is configured to detect whether the DVDD is powered down; the latch circuit 11 is configured to control, after the detection circuit 10 detects that the DVDD is powered down, a voltage of a first output terminal 114 of the latch circuit 11 and a voltage of a second output terminal 115 of the latch circuit 11 to be associated with the pull-up and pull-down circuit 12; the voltage pull-up circuit 121 is configured to pull up the voltage of the first output terminal 114 of the latch circuit 11 to be the power supply voltage of the normally-on region, so as to control the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 to enter a locked state, and make the first output terminal 114 of the latch circuit 11 output a control signal for controlling the controlled circuit to enter a power-down mode; the voltage pull-down circuit 122 is configured to pull down the voltage of the second output terminal 115 of the latch circuit 11 to ground to control the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 to enter a locked state.
Specifically, since the detection circuit 10 is directly connected to the DVDD, the detection circuit 10 can detect whether the DVDD is powered down. When the detection circuit 10 detects that DVDD is powered down, it is known that the controlled circuit of the back end has entered an uncertain state, and that the voltage of the power-off control input terminal 13 connected to the second input terminal 102 of the detection circuit 10 is low. Thus, the detection circuit 10 controls the voltage of the first output 114 of the latch circuit 11 and the voltage of the second output 115 of the latch circuit 11 to be associated with the pull-up and pull-down circuit 12 described above by detecting the voltage of the first output 103 of the circuit 10 and the voltage of the second output 104 of the circuit 10 and the voltage of the power down control input 13 triggering the latch circuit 11. Alternatively, the association here may be: the voltage level of the first output 114 of the latch circuit 11 and the voltage level of the second output 115 of the latch circuit 11 may be controlled by the pull-up action of the voltage pull-up circuit 121 and the pull-down action of the voltage pull-down circuit 122 after the DVDD is powered down, which may not be controlled by the power-down control input 13. Alternatively, the detection circuit 10 may detect whether the DVDD is powered down by using a simple switching tube, for example, may detect whether the DVDD is powered down by using a PMOS tube, which has low cost.
Thus, when the latch circuit 11 controls the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 to be associated with the pull-up and pull-down circuit 12, the voltage pull-up circuit 121 pulls up the voltage of the first output terminal 114 of the latch circuit 11 while the voltage pull-down circuit 122 pulls down the voltage of the second output terminal 115 of the latch circuit 11, thereby ensuring that the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 enter the latch state. It should be noted that, the "locked state" herein refers to that the voltage pull-up circuit 121 and the voltage pull-Down circuit 122 interact, the voltage pull-up circuit 121 continuously pulls Down the voltage of the second output terminal 115 of the latch circuit 11 under the action of the voltage pull-Down circuit 122, the voltage pull-up circuit 121 continuously pulls up the voltage of the first output terminal 114 of the latch circuit 11 to the Power supply voltage of the normal Power region, and the voltage pull-Down circuit 122 continuously pulls up the voltage of the second output terminal 115 of the latch circuit 11 under the action of the voltage pull-up circuit 121 continuously pulls up the voltage of the first output terminal 114 of the latch circuit 11 to the ground, so that the latch circuit 11 enters the locked state, and the first output terminal 114 of the latch circuit 11 outputs a control signal, so that the controlled circuit is controlled to enter the Power Down mode by using the control signal. The potential of the control signal is the same as the potential of the first output 114 of the latch circuit 11, i.e. the first output 114 of the latch circuit 11 is connected to the controlled circuit.
Alternatively, the voltage pull-up circuit 121 may be any circuit having a pull-up function, and the specific form of the voltage pull-up circuit 121 is not limited in this embodiment, as long as it can pull up the voltage of the first output terminal 114 of the latch circuit 11 to the power supply voltage of the normally-on region; in addition, the voltage pull-down circuit 122 may be any circuit having a pull-down function, and the specific form of the voltage pull-down circuit 122 is not limited in this embodiment, as long as it can pull down the voltage of the second output terminal 115 of the latch circuit 11 to a low level.
According to the mode control circuit provided by the embodiment of the invention, after the detection circuit detects that DVDD is powered Down, the voltages of the first output end of the latch circuit and the second output end of the latch circuit are automatically triggered to be associated with the pull-up and pull-Down circuit, so that the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit enter a locking state under the action of the pull-up and pull-Down circuit, and the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a Power-Down mode and controls the controlled circuit to enter a Power Down mode. The circuit provided by the embodiment of the invention can enable the controlled circuit such as an ADC circuit to enter a Power Down mode after DVDD is powered Down, thereby avoiding unnecessary Power consumption of the controlled circuit; in addition, the circuit provided by the embodiment of the invention can trigger the subsequent controlled circuit to automatically enter the Power Down mode after DVDD is powered Down only by connecting the corresponding detection circuit under DVDD, and an additional trigger circuit such as a circuit for generating an isolation signal Viso is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; further, the mode control circuit in the embodiment can be connected with a power supply of a normally-on region, so that PN junction reverse bias of a PMOS tube serving as a transmission gate is ensured, electric leakage of an input end of the mode control circuit is avoided, and reliability of the circuit is ensured.
Fig. 4 is a circuit schematic diagram of a second embodiment of a mode control circuit according to an embodiment of the present invention. This embodiment relates to a specific implementation of the detection circuit 10 described above. On the basis of the above embodiment, the above detection circuit 10 may include the first switching transistor M1 and the inverter 105. The first switch tube M1 may be a PMOS tube. The first input terminal 101 of the detection circuit 10 is connected to the digital power supply DVDD, the second input terminal 102 of the detection circuit 10 is connected to the power-off control input terminal 13, the first output terminal 103 of the detection circuit 10 is connected to the first control terminal 111 of the latch circuit 11, and the second output terminal 104 of the detection circuit 10 is connected to the second control terminal 112 of the latch circuit 11, which specifically includes: the gate of the first switching tube M1 is connected to the power-off control input terminal 13, the source of the first switching tube M1 is connected to the first control terminal 111 of the latch circuit 11, and the drain of the first switching tube M1 is connected to the DVDD and the first input terminal 1051 of the inverter 105, respectively; a second input 1052 of the inverter 105 is connected to the power down control input 13 and an output 1053 of the inverter 105 is connected to the second control 112 of the latch circuit 11.
Specifically, the inverter 105 according to the present embodiment may be any inverter 105, for example, a logic not gate circuit, or a circuit with an inverting function built through a corresponding switching tube, so long as it can invert the voltage of the power-off control input terminal 13. The inverter 105 in the detection circuit 10 shown in fig. 4 is merely an example, and the form of the inverter 105 is not limited in the present invention.
Taking fig. 4 as an example, in fig. 4, the inverter 105 includes a second switching tube M2 and a third switching tube M3, the first input terminal 1051 of the inverter 105 is a source of the second switching tube M2, the second input terminal 1052 of the inverter 105 is a gate of the second switching tube M2 and a gate of the third switching tube M3 (the second input terminal 1052 of the inverter 105 and the second input terminal 102 of the detection circuit 10 are the same ports), and the output terminal 1053 of the inverter 105 is a drain of the second switching tube M2 and a drain of the third switching tube M3 (the output terminal 1053 of the inverter 105 and the second output terminal 104 of the detection circuit 10 are the same ports). Then, "the drain of the first switching transistor M1 is connected to the first input terminal 1051 of the inverter 105, the second input terminal 1052 of the inverter 105 is connected to the power-down control input terminal 13, and the output terminal 1053 of the inverter 105 is connected to the second control terminal 112 of the latch circuit 11" may be specifically: the drain electrode of the first switching tube M1 is connected with the source electrode of the second switching tube M2, the grid electrode of the second switching tube M2 and the grid electrode of the third switching tube M3 are respectively connected with the power-off control input end 13, the drain electrode of the second switching tube M2 is connected with the drain electrode of the third switching tube M3 and respectively connected with the second control end 112 of the latch circuit 11, and the source electrode of the third switching tube M3 is grounded.
In the detection circuit 10 of fig. 4, when DVDD is powered down, the voltage at the power-off control input terminal 13 is low, and therefore, the low voltage is inverted by the inverter 105 composed of the second switching transistor M2 and the third switching transistor M3 and becomes high, that is, the drain of the second switching transistor M2 and the drain output of the third switching transistor M3 are both high, and the high voltage is output to the first control terminal 111 of the latch circuit 11; after the DVDD is powered down, the voltage (Vctrl) at the source of the first switching transistor M1 is continuously pulled down and is output to the second control terminal 112 of the latch circuit 11 at the rear end. And, correspondingly, the low potential of the power-down control input terminal 13 is also output to the third control terminal 113 of the latch circuit 11. That is, the two outputs of the detection circuit 10 and the power-down control input 13 cooperate to trigger and control the operation state of the latch circuit 11 of the rear end.
Fig. 5 is a circuit schematic diagram of a third embodiment of a mode control circuit according to an embodiment of the present invention. This embodiment relates to one possible implementation of the voltage pull-up circuit 121 and the voltage pull-down circuit 122 described above. In fig. 5, the voltage pull-up circuit 121 includes a fourth switch tube M4, the voltage pull-down circuit 122 includes a fifth switch tube M5, the first end 1211 of the voltage pull-up circuit 121 is a source of the fourth switch tube M4, the second end 1212 of the voltage pull-up circuit 121 is a drain of the fourth switch tube M4, the first end 1221 of the voltage pull-down circuit 122 is a drain of the fifth switch tube M5, and the second end 1222 of the voltage pull-down circuit 122 is a source of the fifth switch tube M5. Therefore, the first terminal 1211 of the voltage pull-up circuit 121 is connected to the power supply of the normally-on region, the second terminal 1212 of the voltage pull-up circuit 121 is connected to the first output terminal 114 of the latch circuit 11, the first terminal 1221 of the voltage pull-down circuit 122 is connected to the second output terminal 115 of the latch circuit 11, and the second terminal 1222 of the voltage pull-down circuit 122 is grounded, which may be specifically:
The source electrode of the fourth switching tube M4 is connected with a power supply of a normally-on region, the grid electrode of the fourth switching tube M4 is connected with the drain electrode of the fourth switching tube M4, and the drain electrode of the fourth switching tube M4 is connected with the first output end 114 of the latch circuit 11; the gate of the fifth switching tube M5 is connected to the drain of the fifth switching tube M5, the source of the fifth switching tube M5 is grounded, and the drain of the fifth switching tube M5 is connected to the second output terminal 115 of the latch circuit 11.
Specifically, in this embodiment, after the DVDD is powered down, the latch circuit 11 may be associated with the voltage pull-up circuit 121 and the voltage pull-down circuit 122 under the enabling action of the voltages of the detection circuit 10 and the power-down control input terminal 13, where the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 are not controlled by the voltage of the power-down control terminal. Therefore, when the fifth switching transistor M5 is turned on, the second output terminal 115 of the latch circuit 11 is turned on to the ground, and the voltage of the second output terminal 115 of the latch circuit 11 is low, the fifth switching transistor M5 functions to pull down the second output terminal 115 of the latch circuit 11; in addition, the fourth switching tube M4 continuously pulls Down the voltage of the second output terminal 115 of the latch circuit 11 under the action of the fifth switching tube M5, the fourth switching tube M4 continuously pulls up the voltage of the first output terminal 114 of the latch circuit 11 to the Power supply voltage of the Power Down region, meanwhile, the fifth switching tube M5 continuously pulls Down the voltage of the second output terminal 115 of the latch circuit 11 to the ground under the action of the fourth switching tube M4 continuously pulls up the voltage of the first output terminal 114 of the latch circuit 11, so that the latch circuit 11 is repeatedly acted, and finally, the voltage of the first output terminal 114 of the latch circuit 11 is ensured to be high, so that a control signal (the control signal is a voltage signal of a terminal Power Down Output in fig. 5) for controlling the controlled circuit to enter the Power Down mode is output, and the controlled circuit enters the Power Down mode after the DVDD is powered Down.
Fig. 6 is a circuit schematic diagram of a fourth embodiment of a mode control circuit according to an embodiment of the present invention. This embodiment relates to a specific implementation of the mode control circuit. On the basis of the above-described embodiment, in fig. 6, the latch circuit 11 may include a first switch circuit 116, a second switch circuit 117, and a latch circuit 118; the first switching circuit 116 may include a sixth switching tube M6 and a seventh switching tube M7, the second switching circuit 117 may include an eighth switching tube M8 and a ninth switching tube M9, and the latch circuit 118 may include a tenth switching tube M10 and an eleventh switching tube M11.
The grid electrode of the sixth switching tube M6 and the grid electrode of the eighth switching tube M8 are respectively connected with the source electrode of the first switching tube M1, the source electrode of the sixth switching tube M6 is connected with the drain electrode of the seventh switching tube M7, the drain electrode of the sixth switching tube M6 is connected with the drain electrode of the tenth switching tube M10, the grid electrode of the seventh switching tube M7 is respectively connected with the drain electrode of the second switching tube M2 and the drain electrode of the third switching tube M3, and the source electrode of the seventh switching tube M7 is grounded; the source electrode of the eighth switching tube M8 is connected with the drain electrode of the ninth switching tube M9, the drain electrode of the eighth switching tube M8 is connected with the drain electrode of the eleventh switching tube M11, the grid electrode of the ninth switching tube M9 is connected with the power-off control input end 13, and the source electrode of the ninth switching tube M9 is grounded; the source of the tenth switching tube M10 and the source of the eleventh switching tube M11 are respectively connected with a power supply of a normally-on region, the grid electrode of the tenth switching tube M10 is connected with the drain electrode of the eleventh switching tube M11, the drain electrode of the tenth switching tube M10 is respectively connected with the drain electrode of the fourth switching tube M4 and the grid electrode of the eleventh switching tube M11, and the drain electrode of the eleventh switching tube M11 is connected with the drain electrode of the fifth switching tube M5.
Optionally, the first switching circuit 116 may further include a twelfth switching tube M12, and the second switching circuit 117 may further include a thirteenth switching tube M13; the drain of the sixth switching tube M6 is connected to the drain of the tenth switching tube M10, specifically, the drain of the sixth switching tube M6 is connected to the source of the twelfth switching tube M12, the drain of the twelfth switching tube M12 is connected to the drain of the tenth switching tube M10, and the gate of the twelfth switching tube M12 is connected to the gate of the seventh switching tube M7, that is, the sixth switching tube M6 is connected to the tenth switching tube M10 through the twelfth switching tube M12; the drain of the eighth switching transistor M8 is connected to the drain of the eleventh switching transistor M11, and specifically may be: the drain electrode of the eighth switching tube M8 is connected with the source electrode of the thirteenth switching tube M13, the drain electrode of the thirteenth switching tube M13 is connected with the drain electrode of the eleventh switching tube M11, the grid electrode of the thirteenth switching tube M13 is connected with the grid electrode of the ninth switching tube M9, namely, the eighth switching tube M8 is connected with the eleventh switching tube M11 through the thirteenth switching tube M13.
Specifically, taking the example that the first switching circuit 116 includes the sixth switching tube M6, the seventh switching tube M7 and the twelfth switching tube M12, the second switching circuit 117 includes the eighth switching tube M8, the ninth switching tube M9 and the thirteenth switching tube M13, the first control terminal 111 of the latch circuit 11 is the gate of the sixth switching tube M6 and the gate of the eighth switching tube M8, the second control terminal 112 of the latch circuit 11 is the gate of the seventh switching tube M7 and the gate of the twelfth switching tube M12, the third control terminal 113 of the latch circuit 11 is the gate of the ninth switching tube M9 and the gate of the thirteenth switching tube M13, the first output terminal 114 of the latch circuit 11 is the drain of the fourth switching tube M4 and the drain of the tenth switching tube M10 (the first output terminal 114 of the latch circuit 11 is the point X in fig. 6), and the second output terminal 115 of the latch circuit 11 is the drain of the fifth switching tube M5 and the drain of the eleventh switching tube M11 (the second output terminal 115 in the latch circuit 11 is the point Y in fig. 6).
After the DVDD is powered down, the voltage (Vctrl) at the source of the first switching tube M1 is continuously pulled down, and since the gates of the sixth switching tube M6 and the eighth switching tube M8 are both connected to the source of the first switching tube M1, and the sixth switching tube M6 and the eighth switching tube M8 are both NMOS tubes, when the voltage (Vctrl) at the source of the first switching tube M1 is continuously pulled down, the voltages at the gates of the sixth switching tube M6 and the eighth switching tube M8 are both low, and therefore, the sixth switching tube M6 and the eighth switching tube M8 are both turned off, and in addition, the first switching tube 116 and the second switching tube 117 are both turned off, and the first switching tube M4 and the fifth switching tube M5 are both in a high-resistance state, so that the pull-up and pull-down of the first switching tube 116 and the second switching tube 117 are realized. That is, since the first switching circuit 116 and the second switching circuit 117 are both in a high-resistance state, the pull-up and pull-down actions of the fourth switching transistor M4 and the fifth switching transistor M5 are stronger than those of the first switching circuit 116 and the second switching circuit 117, and thus the fourth switching transistor M4 and the fifth switching transistor M5 can effectively lock the latch circuit 118 formed by the tenth switching transistor M10 and the eleventh switching transistor M11. At this time, the potentials of the X point and the Y point are controlled by the fourth switching transistor M4 and the fifth switching transistor M5 at this time.
The latch circuit 118 described herein latches, and can be explained in two ways: when DVDD is powered down, both the voltage of the power-down control input terminal 13 and the DVDD voltage drop down to the vicinity of GND (ground), resulting in uncertainty in the voltage state of the first output terminal 114 of the latch circuit 11 and the second output terminal 115 of the latch circuit 11, i.e., the potential at the X point and the potential at the Y point are actually unknown states, which are assumed to be divided into two states:
first kind: after the DVDD is powered down, the X point is at a low potential, and the Y point is at a high potential.
When the X point is at low potential, the fourth switching tube M4 is conducted to pull up the potential of the X point to the power voltage of the normally-on region, and the potential of the Y point is at high potential, the fifth switching tube M5 is conducted to enable the potential of the Y point to be pulled down to the ground by the fifth switching tube M5, and at the moment, the potential of the Y point becomes low potential. Because the grid electrode of the tenth switching tube M10 is connected with the Y point, the grid voltage of the tenth switching tube M10 is low (the tenth switching tube M10 is a PMOS tube), so the tenth switching tube M10 is turned on, and the potential of the X point is continuously pulled up to the power supply voltage of the normally-on region (at the moment, the fourth switching tube M4 is turned off); since the gate of the eleventh switch tube M11 is connected to the X point, the voltage of the gate of the eleventh switch tube M11 is at a high level (the eleventh switch tube M11 is a PMOS tube), so that the eleventh switch tube M11 is turned off, the Y point potential is continuously pulled Down by the fifth switch tube M5, and the X point potential is continuously pulled up again, and the latch circuit 118 is repeatedly operated in such a manner that the latch circuit 118 is in a latch state, so as to ensure that the X point potential is high, the Y point potential is low, and further the control signal (Power Down Output) output by the X point is at a high level, so as to control the controlled circuit to enter a Power Down mode.
Second kind: after the DVDD is powered down, the X point is at a high potential, and the Y point is at a low potential.
When the X point is at high potential, the fourth switching tube M4 is turned off, when the Y point is at low potential, the fifth switching tube M5 is also turned off, at the moment, the fourth switching tube M4 loses the pull-up effect, the fifth switching tube M5 loses the pull-down effect, at the moment, the eleventh switching tube M11 is turned off, the tenth switching tube M10 is turned on, the potential of the X point is continuously at high potential, the potential of the Y point is always at low potential, and at the moment, the latch also enters a locking state.
In summary, in either of the lockup states, the potential of the first output terminal 114 of the latch circuit 11 is always high, and the potential of the second output terminal 115 of the latch circuit 11 is always low, thereby ensuring that the first output terminal 114 of the latch circuit 11 outputs a control signal that controls the controlled circuit.
When the fourth switching transistor M4 and the fifth switching transistor M5 pull up and down the potential (X point) of the first output terminal 114 of the latch circuit 11 and the potential (Y point) of the second output terminal 115 of the latch circuit 11, respectively, that is, when the potential at the X point is 1 and the potential at the Y point is 0, the drain voltages of the source of the fourth switching transistor M4 and the drain voltage of the fourth switching transistor M4 are equal, no leakage current is generated, and the source voltage of the fifth switching transistor M5 and the drain voltage of the fifth switching transistor M5 are also equal, so no leakage current is generated.
On the other hand, the mode control circuit according to the embodiment of the invention does not affect the normal operation of the controlled circuit, and is specifically described in two cases:
first kind: when the DVDD is charged, the voltage of the Power-off control input terminal 13 is high, and the controlled circuit is controlled to enter the Power Down mode.
Because the grid electrode of the ninth switching tube M9 and the grid electrode of the thirteenth switching tube M13 are connected with the power-off control input end 13 (the grid electrode of the ninth switching tube M9 and the grid electrode of the thirteenth switching tube M13 are NMOS tubes), the ninth switching tube M9 and the thirteenth switching tube M13 are conducted; meanwhile, the voltage of the power-down control input terminal 13 is low through the inverter 105 formed by the second switching tube M2 and the third switching tube M3 (the seventh switching tube M7 and the twelfth switching tube M12 are NMOS tubes), so that the seventh switching tube M7 and the twelfth switching tube M12 are turned off. In addition, when DVDD is charged, the voltages of the gates of the sixth switching transistor M6 and the eighth switching transistor M8 are high (the sixth switching transistor M6 and the eighth switching transistor M8 are both NMOS transistors), and therefore the sixth switching transistor M6 and the eighth switching transistor M8 are turned on. That is, the first switching circuit 116 is turned off to a high-resistance state, and the second switching circuit 117 is turned on, which results in the potential of the Y point being a low potential (the fifth switching transistor M5 is turned off); and because the potential of the Y point causes the tenth switching tube M10 to be conducted, the potential of the X point is high (at the moment, the fourth switching tube M4 is turned off), namely, the pull-up action of the fourth switching tube M4 and the pull-down action of the fifth switching tube M5 are invalid at the moment, and the potential of the X point is influenced by the voltage of the power-off control input end 13. That is, when the voltage of the Power-Down control input terminal 13 is high, the potential of the X point is high, and a control signal of high potential is surely output, so that the controlled circuit enters the Power Down mode. That is, the fourth switching tube M4 and the fifth switching tube M5 do not affect the normal control of the entire circuit.
Second kind: when the DVDD is charged, the voltage of the power-off control input terminal 13 is low, and the controlled circuit is controlled to enter the operation mode.
Because the grid electrode of the ninth switching tube M9 and the grid electrode of the thirteenth switching tube M13 are connected with the power-off control input end 13 (the grid electrode of the ninth switching tube M9 and the grid electrode of the thirteenth switching tube M13 are NMOS tubes), the ninth switching tube M9 and the thirteenth switching tube M13 are turned off; meanwhile, the voltage of the power-down control input terminal 13 is high through the inverter 105 formed by the second switching tube M2 and the third switching tube M3 (the seventh switching tube M7 and the twelfth switching tube M12 are NMOS tubes), so that the seventh switching tube M7 and the twelfth switching tube M12 are turned on. In addition, when DVDD is charged, the voltages of the gates of the sixth switching transistor M6 and the eighth switching transistor M8 are high (the sixth switching transistor M6 and the eighth switching transistor M8 are both NMOS transistors), and therefore the sixth switching transistor M6 and the eighth switching transistor M8 are turned on. That is, the first switching circuit 116 is turned on, the second switching circuit 117 is turned off to a high-resistance state, which results in the potential at the X point being low (the fourth switching transistor M4 is turned on), but since the impedance of the fourth switching transistor M4 is greater than that of the first switching circuit 116, the pull-up action of the fourth switching transistor M4 is smaller than that of the first switching circuit 116 to pull down the potential at the X point to the ground, so the potential at the X point is kept low; since the low potential at the X point causes the eleventh switching transistor M11 to turn on, the potential at the Y point becomes high, and at this time, the fifth switching transistor M5 turns on, and the potential at the Y point is pulled down to the low potential again. At this time, the potential of the point X is affected by the voltage of the power-off control input terminal 13, so as to ensure that a control signal of low potential is output, so that the controlled circuit enters a working mode, that is, the fourth switching tube M4 and the fifth switching tube M5 can not affect the normal operation of the whole circuit.
In addition, when the DVDD electrified controlled circuit works normally (i.e., the X point is low and the Y point is high), the fourth switching tube M4 and the fifth switching tube M5 are both turned on, and although a small amount of leakage current is generated, the leakage current is generated when the ADC works normally, so that the ADC is not affected to enter the Power Down mode.
After detecting that DVDD is powered Down, the mode control circuit provided by the embodiment of the invention enables the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to enter a locking state under the action of the pull-Down circuit, so that the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a Power-Down mode and controls the controlled circuit to enter a Power Down mode. The circuit provided by the embodiment of the invention can enable the controlled circuit such as an ADC circuit to enter a Power Down mode after DVDD is powered Down, thereby avoiding unnecessary Power consumption of the controlled circuit and saving the overall Power consumption expense of the system; in addition, in the state of no external control signal, the circuit provided by the embodiment of the invention can automatically trigger the subsequent controlled circuit to automatically enter the Power Down mode after the DVDD is powered Down by only connecting the corresponding detection circuit under the DVDD, and an additional trigger circuit is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; furthermore, the mode control circuit provided by the embodiment of the invention can not generate leakage current under the condition of DVDD power-down, so that the reliability of the whole circuit is ensured.
Fig. 7 is a schematic diagram of an embodiment of an apparatus provided in an embodiment of the present invention. As shown in fig. 7, the apparatus may include a controlled circuit 20 and a mode control circuit 21 in the above embodiment, the mode control circuit 21 being connected to the controlled circuit 20 for controlling the controlled circuit 20 to automatically enter the PowerDown mode after the DVDD is powered down. Alternatively, the controlled circuit 20 may be the ADC circuit in fig. 2, a dual power supply circuit, or other circuits to be controlled.
The specific process and the beneficial effects of the device provided by the embodiment of the present invention for controlling the controlled circuit to automatically enter the Power Down mode after the DVDD is powered Down can be seen in the embodiment of the mode control circuit, and will not be described herein.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (10)

1. A mode control circuit, comprising: the circuit comprises a detection circuit, a latch circuit and a pull-up circuit, wherein the latch circuit comprises a first control end, a first output end and a second output end, and the pull-up circuit comprises a voltage pull-up circuit and a voltage pull-down circuit; wherein,
the detection circuit is connected with the digital power supply DVDD, the detection circuit is coupled with the first control end of the latch circuit, the first output end of the latch is coupled with the voltage pull-up circuit, and the second output end of the latch circuit is coupled with the voltage pull-down circuit;
the first end of the voltage pull-up circuit is connected with a power supply of the normally-on region and is used for pulling up the voltage of the first output end of the latch circuit to be the power supply voltage of the normally-on region;
the detection circuit is used for controlling the first control end of the latch circuit when the DVDD is powered down, so that the first output end of the latch is pulled up to be high level by the voltage pull-up circuit, and the second output end of the latch circuit is pulled down to be low level by the voltage pull-down circuit;
the latch control circuit includes: a first switch circuit and a second switch circuit, a first output terminal of the latch circuit being grounded through the first switch circuit, a second output terminal of the latch circuit being grounded through the second switch circuit, a first control terminal of the latch circuit being coupled to the first switch circuit and the second switch circuit;
When the first control end of the latch circuit is at a low level, the first switch circuit and the second switch circuit are both opened, so that the voltage of the first output end of the latch circuit is pulled up to be the power supply voltage of a normally-on region by the voltage pull-up circuit, and the second output end of the latch circuit is pulled down to be at a low level by the voltage pull-down circuit.
2. The circuit of claim 1, wherein the detection circuit comprises a first switching tube, a drain of the first switching tube is coupled to the DVDD, a source of the first switching tube is coupled to a first control terminal of the latch circuit, and a gate of the first switching tube is connected to a power down control input terminal;
when the DVDD is powered down, the source voltage of the first switch tube is pulled down, so that the first control end of the latch circuit is in a low level.
3. The circuit of claim 1, wherein the first switching circuit comprises a sixth switching tube, the second switching circuit comprises an eighth switching tube, the sixth switching tube and the eighth switching tube are both NMOS tubes, a first control terminal of the latch circuit is coupled to gates of the sixth switching tube and the eighth switching tube, and when the first control terminal of the latch circuit is at a low level, both the sixth switching tube and the eighth switching tube are turned off.
4. The circuit of claim 3, wherein the detection circuit further comprises: an inverter, the first switching circuit further including a seventh switching tube and a twelfth switching tube, the second switching circuit further including a ninth switching tube and a thirteenth switching tube;
the input end of the inverter is connected with a power-off control input end, the output end of the inverter is coupled with the gates of the seventh switching tube and the twelfth switching tube, and the power-off control input end is coupled with the gates of the ninth switching tube and the thirteenth switching tube;
the grid electrode of the sixth switching tube and the grid electrode of the eighth switching tube are respectively connected with the source electrode of the first switching tube, the source electrode of the sixth switching tube is connected with the drain electrode of the seventh switching tube, the drain electrode of the sixth switching tube is connected with the drain electrode of the tenth switching tube, the grid electrode of the seventh switching tube is respectively connected with the drain electrode of the second switching tube and the drain electrode of the third switching tube, and the source electrode of the seventh switching tube is grounded;
the source electrode of the eighth switching tube is connected with the drain electrode of the ninth switching tube, and the drain electrode of the eighth switching tube is connected with the drain electrode of the eleventh switching tube.
5. The circuit of claim 4, wherein the inverter comprises a second switching tube and a third switching tube, wherein a source electrode of the second switching tube is connected with a drain electrode of the first switching tube, a gate electrode of the second switching tube and a gate electrode of the third switching tube are connected and led out of an input end of the inverter, a drain electrode of the second switching tube is connected with a drain electrode of the third switching tube and led out of an output end of the inverter, and a source electrode of the third switching tube is grounded.
6. A circuit according to claim 3, wherein the source of the seventh switching tube is connected to ground, the drain of the seventh switching tube is connected to the source of the sixth switching tube, the drain of the sixth switching tube is connected to the source of the twelfth switching tube, and the drain of the twelfth switching tube is connected to the first output of the latch circuit;
the source electrode of the ninth switching tube is grounded, the drain electrode of the ninth switching tube is connected with the source electrode of the eighth switching tube, the drain electrode of the eighth switching tube is connected with the source electrode of the thirteenth switching tube, and the drain electrode of the thirteenth switching tube is connected with the second output end of the latch circuit.
7. The circuit of claim 1, wherein the voltage pull-up circuit comprises a fourth switching tube, the voltage pull-down circuit comprises a fifth switching tube, a source of the fourth switching tube is connected with a power supply of the normally-on region, and a gate of the fourth switching tube is connected with a drain of the fourth switching tube and connected to a first output terminal of the latch circuit;
The source electrode of the fifth switching tube is grounded, and the grid electrode of the fifth switching tube is connected with the drain electrode of the fifth switching tube and is connected to the second output end of the latch circuit.
8. The circuit of claim 1, wherein the latch circuit further comprises a latch circuit comprising a tenth switching tube and an eleventh switching tube, the source of the tenth switching tube and the source of the eleventh switching tube being respectively connected to a power supply of a normally-on region, the gate of the tenth switching tube being connected to the drain of the eleventh switching tube, the gate of the eleventh switching tube being connected to the drain of the tenth switching tube, the first output of the latch circuit being pulled from the drain of the tenth switching tube, the second output of the latch circuit being pulled from the drain of the eleventh switching tube.
9. An apparatus comprising a controlled circuit, further comprising: a mode control circuit as claimed in any one of claims 1 to 8;
the mode control circuit is connected with the controlled circuit.
10. The apparatus of claim 9, the controlled circuit comprising: an analog to digital converter ADC circuit or a dual power supply circuit.
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CN104638887A (en) * 2015-01-30 2015-05-20 北京时代民芯科技有限公司 Output driving circuit capable of realizing output high level conversion

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